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| printed in europe document no. u17830ee1v0um00 date published november 2005-ns cp(k) user?s manual v850es/fx2 32-bit single-chip microcontroller hardware pd703230(a) pd70(f)3231(a) pd703230(a1) pd70(f)3231(a1) pd703230(a2) pd70(f)3231(a2) pd70(f)3232(a) pd70(f)3233(a) pd70(f)3232(a1) pd70(f)3233(a1) pd70(f)3232(a2) pd70(f)3233(a2) pd70(f)3234(a) pd70(f)3235(a) pd70f3236(a) pd70(f)3234(a1) pd70(f)3235(a1) pd70f3236(a1) pd70(f)3234(a2) pd70(f)3235(a2) pd70f3236(a2) pd70f3237(a) pd70f3238(a) pd70f3239(a) pd70f3237(a1) pd70f3238(a1) pd70f3239(a1) pd70f3237(a2) pd70f3238(a2) pd70f3239(a2) 2005
user?s manual u17830ee1v0um00 2 [memo] user?s manual u17830ee1v0um00 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 user?s manual u17830ee1v0um00 4 the information in this document is current as of november, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate suffici ent safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u17830ee1v0um00 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: user?s manual u17830ee1v0um00 6 preface readers for the whole document it shall be agreed that v850es/fx2 st ands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. this manual is intended for users who wish to understand the functions of the v850es/fx2 and design applicati on systems using these products. the target products are as follows. purpose this manual is intended to give users an understanding of the hardware functions of the v850es/fx2 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? cpu function ? on-chip peripheral functions ? flash memory programming ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the details of an instruction function refer to the v850es architecture user?s manual . register format the name of the bit whose number is in angl e brackets (< >) in the figure of the register format of each register is defined as a reserved word in the device file. regarding the pin functions and internal pe ripheral functions of products, please read and change the products as follows. ? pd703230 pd703230(a), pd703230(a1), pd703230(a2) ? pd70f3231 pd70(f)3231(a), pd70(f)3231(a1), pd70(f)3231(a2) ? pd70f3232 pd70(f)3232(a), pd70(f)3232(a1), pd70(f)3232(a2) ? pd70f3233 pd70(f)3233(a), pd70(f)3233(a1), pd70(f)3233(a2) ? pd70f3234 pd70(f)3234(a), pd70(f)3235(a1), pd70(f)3234(a2) ? pd70f3235 pd70(f)3235(a), pd70(f)3235(a1), pd70(f)3235(a2) ? pd70f3236 pd70f3236(a), pd70f3236(a1), pd70f3236(a2) ? pd70f3237 pd70f3237(a), pd70f3237(a1), pd70f3237(a2) ? pd70f3238 pd70f3238(a), pd70f3238(a1), pd70f3238(a2) ? pd70f3239 pd70f3239(a), pd70f3239(a1), pd70f3239(a2) to understand the overall f unctions of the v850es/fx2 read this manual according to the contents . the mark shows major revised points. user?s manual u17830ee1v0um00 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove r score over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/fx2 and sub series (v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2) document name document no. v850es architecture user?s manual u15943e v850es/fx2 hardware user?s manual u17830ee1v0um00 v850es/fe2 data sheet u17834ee1v0ds00 v850es/fg2 data sheet u17832ee1v0ds00 v850es/ff2 data sheet u17833ee1v0ds00 v850es/fj2 data sheet u17831ee1v0ds00 user?s manual u17830ee1v0um00 8 documents related to developm ent tools (user?s manuals) document name document no. ie-v850es-g1 (in-circ uit emulator) u16313e ie-703239-g1-em1 (in-circuit emulat or option board) sud-ft-04-0105 operation u16053e c language u16054e pm plus u16055e ca850 ver. 2.70 c compiler package assembly language u16042e id850 ver. 2.51 integrated debugger operation u16217e fundamental u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e fundamental u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.2 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e ie-v850e1-cd-nw(n-wire) u16647e qb-v850esf x 2(iecube) zud-bd-04-0085 sm plus ver1.00 system simulation u16906j user?s manual u17830ee1v0um00 9 contents chapter 1 introduction ...................................................................................................... ...........19 1.1 general .................................................................................................................... ...................19 1.2 product development of v850es/fe2, v850es/ ff2, v850es/fg2, and v850es/fj2.........20 1.3 features................................................................................................................... ...................21 1.4 ordering information ....................................................................................................... .........23 1.5 applications ............................................................................................................... ................26 1.6 pin configuration (top view) .................................... ........................................................... ....27 1.7 function block configuration....................................... ...........................................................3 3 1.7.1 internal bl ock di agram ......................................................................................................... .......... 33 1.7.2 internal units ................................................................................................................. ................ 38 chapter 2 pin funct ions.................................................................................................... ............40 2.1 pin function list .............................................................................................................. .........40 2.1.1 v850es/ fe2 ..................................................................................................................... ............ 40 2.1.2 v850es/ ff2 ..................................................................................................................... ............ 45 2.1.3 v850es/ fg2..................................................................................................................... ............ 50 2.1.4 v850es/ fj2..................................................................................................................... ............. 55 2.2 pin status (v850es/fj2) .................................................................................................... .......63 2.3 description of pin functions ........................................... ........................................................ 64 2.3.1 v850es/ fe2 ..................................................................................................................... ............ 64 2.3.2 v850es/ ff2 ..................................................................................................................... ............ 71 2.3.3 v850es/ fg2..................................................................................................................... ............ 78 2.3.4 v850es/ fj2..................................................................................................................... ............. 84 2.4 pin i/o circuit types and recommended connection of unused pins ..............................94 2.4.1 v850es/ fe2 ..................................................................................................................... ............ 94 2.4.2 v850es/ ff2 ..................................................................................................................... ............ 96 2.4.3 v850es/ fg2..................................................................................................................... ............ 98 2.4.4 v850es/ fj2..................................................................................................................... ........... 100 2.5 pin i/o circuits............................................................................................................... ..........104 chapter 3 cpu funct ions .................................................................................................... ........106 3.1 features................................................................................................................... .................106 3.2 cpu register set ........................................................................................................... ..........107 3.2.1 program r egister set ..................................................................................................... .............. 108 3.2.2 system regi ster set ............................................................................................................ ......... 109 3.3 operation modes ................................................................................................................ .....115 3.4 address space.................................................................................................................. .......116 3.4.1 cpu address space .............................................................................................................. ...... 116 3.4.2 image.......................................................................................................................... ................ 117 3.4.3 wraparound of cpu addr ess spac e ........................................................................................... 118 3.4.4 memory map..................................................................................................................... .......... 119 3.4.5 areas .......................................................................................................................... ................ 121 3.4.6 recommended use of address s pace ......................................................................................... 134 3.4.7 peripheral i/o regist ers ....................................................................................................... ........ 137 3.4.8 programmable peripher al i/o regi ster......................................................................................... 17 6 3.4.9 special regist ers ........................................................................................................ ................. 177 3.4.10 cauti ons....................................................................................................................... ............... 181 user?s manual u17830ee1v0um00 10 chapter 4 port functio ns ................................................................................................... ...... 184 4.1 features ....................................................................................................................... ............ 184 4.2 basic port configuration ....................................................................................................... 184 4.2.1 basic port configurat ion on v850 es/fe2 ....................................................................................184 4.2.2 port configurati on on v850 es/ff2..............................................................................................1 85 4.2.3 port configurati on on v850es/ fg2 .............................................................................................18 6 4.2.4 port configurati on on v850es/ fj2 ..............................................................................................1 87 4.3 port configuration ................................................................ ............................................. ..... 188 4.3.1 port 0 ......................................................................................................................... .................194 4.3.2 port 1 ......................................................................................................................... .................201 4.3.3 port 3 ......................................................................................................................... .................206 4.3.4 port 4 ......................................................................................................................... .................216 4.3.5 port 5 ......................................................................................................................... .................219 4.3.6 port 6 ......................................................................................................................... .................226 4.3.7 port 7 ......................................................................................................................... .................236 4.3.8 port 8 ......................................................................................................................... .................239 4.3.9 port 9 ......................................................................................................................... .................244 4.3.10 port 12 ........................................................................................................................ ................257 4.3.11 port cd ........................................................................................................................ ...............259 4.3.12 port cm........................................................................................................................ ...............261 4.3.13 port cs ........................................................................................................................ ...............265 4.3.14 port ct........................................................................................................................ ................269 4.3.15 port dl........................................................................................................................ ................273 4.3.16 port pins that function alter nately as on-chip debug func tion ......................................................278 4.3.17 register settings to use port pins as alternate- function pins .......................................................279 4.3.18 operation of port func tion..................................................................................................... .......286 4.4 cautions ....................................................................................................................... ........... 287 4.4.1 cautions of se tting port pins.................................................................................................. ......287 4.4.2 cautions of bit manilulation inst ruction for port r egister (pn) .......................................................288 4.4.3 cautions on on- chip debug pins................................................................................................. .288 4.4.4 cautions on p05/in tp2/drst pin ..............................................................................................288 chapter 5 bus control function ................................ .......................................................... 28 9 5.1 features ....................................................................................................................... ............ 289 5.2 bus control pins............................................................................................................... ...... 290 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed ..................290 5.2.2 pin status in eac h operati on m ode .............................................................................................. 290 5.3 memory block function ......................................................................................................... 2 91 5.3.1 memory space................................................................................................................... ..........291 5.3.2 chip select func tion........................................................................................................... ..........292 5.4 bus access ..................................................................................................................... ........ 293 5.4.1 number of clo cks for a ccess .................................................................................................... ...293 5.4.2 bus size setti ng func tion ...................................................................................................... .......293 5.4.3 access according to bus size ................................................................................................... ...294 5.5 wait function .................................................................................................................. ........ 300 5.5.1 programmable wa it func tion..................................................................................................... ...300 5.5.2 external wait func tion ......................................................................................................... .........301 5.5.3 relationship between programmabl e wait and exte rnal wa it....................................................... 301 user?s manual u17830ee1v0um00 11 5.5.4 programmable address wait func tion .......................................................................................... 302 5.6 idle state insertion function ......................................... ......................................................... 303 5.7 bus hold function .............................................................................................................. ....304 5.7.1 functional outlin e............................................................................................................. ........... 304 5.7.2 bus hold pr ocedur e............................................................................................................. ........ 305 5.7.3 operation in pow er save mode ................................................................................................... 305 5.8 bus priority ................................................................................................................... ...........306 5.9 boundary operation conditions...................................... ......................................................306 5.9.1 program spac e.................................................................................................................. .......... 306 5.9.2 data s pace..................................................................................................................... ............. 306 5.10 bus timing ..................................................................................................................... ..........307 5.10.1 multiple xed bus ................................................................................................................ ........... 307 chapter 6 clock generation function ................ ...............................................................313 6.1 overview....................................................................................................................... ............313 6.2 configuration .................................................................................................................. .........314 6.3 control registers .............................................................................................................. ......316 6.4 operation...................................................................................................................... ............319 6.4.1 operation of each cl ock ........................................................................................................ ...... 319 6.4.2 clock output functi on .......................................................................................................... ........ 320 6.5 pll function................................................................................................................... .........320 6.5.1 overvi ew....................................................................................................................... .............. 320 6.5.2 control r egisters.............................................................................................................. ............ 320 6.5.3 usage .......................................................................................................................... ............... 323 chapter 7 16-bit timer/event coun ter p .............................................................................324 7.1 features....................................................................................................................... .............324 7.2 functional outline ............................................................................................................. ......324 7.3 configuration .................................................................................................................. .........325 7.4 control registers .............................................................................................................. ......330 7.5 operation...................................................................................................................... ............339 7.5.1 anytime writ e and re load ....................................................................................................... ..... 339 7.5.2 interval timer mode (tpn md2 to tpnm d0 = 000) ....................................................................... 344 7.5.3 external event count mode (t pnmd2 to tpnm d0 = 001)........................................................... 347 7.5.4 external trigger pulse mode (tpnmd2 to tp nmd0 = 010).......................................................... 351 7.5.5 one-shot pulse mode (tpn md2 to tpnm d0 = 011) ................................................................... 354 7.5.6 pwm mode (tpnmd2 to tpnmd0 = 100) ................................................................................... 357 7.5.7 free-running mode (tpnmd2 to tpnmd0 = 101) ....................................................................... 362 7.5.8 pulse width measurement mode (tpnmd2 to tp nmd0 = 110) .................................................. 367 7.6 timer synchronized operation function.................... ..........................................................369 7.7 selector function .............................................................................................................. ......373 7.8 cautions ....................................................................................................................... ............377 chapter 8 16-bit timer/event coun ter q.............................................................................380 8.1 features....................................................................................................................... .............380 8.2 functional outline ............................................................................................................. ......380 8.3 configuration .................................................................................................................. .........381 8.4 control registers .............................................................................................................. ......388 user?s manual u17830ee1v0um00 12 8.5 operation ...................................................................................................................... ........... 398 8.5.1 anytime writ e and re load ....................................................................................................... ......398 8.5.2 interval timer mode (tqn md2 to tqnm d0 = 000) ......................................................................403 8.5.3 external event count mode (t qnmd2 to tqnm d0 = 001) .......................................................... 406 8.5.4 external trigger pulse mode (tqnmd2 to tq nmd0 = 010) ......................................................... 410 8.5.5 one-shot pulse mode (tqn md2 to tqnm d0 = 011) ...................................................................413 8.5.6 pwm mode (tqnmd2 to tqnmd0 = 100) ..................................................................................416 8.5.7 free-running mode (tqnmd2 to tqnmd0 = 101) ...................................................................... 42" 8.5.8 pulse width measurement mode (tqnmd2 to tq nmd0 = 110).................................................. 422 8.5.9 triangular wave pwm mode (t qnmd2 to tqnm d0 = 111)........................................................ 431 8.6 timer synchronized operation function ........................ ..................................................... 433 8.7 cautions ....................................................................................................................... ........... 437 chapter 9 16-bit interval timer m........................ ................................................................ . 440 9.1 features ....................................................................................................................... ............ 440 9.2 configuration .................................................................................................................. ........ 441 9.3 control register............................................................................................................... ....... 443 9.4 operation ...................................................................................................................... ........... 445 9.4.1 interval ti mer m ode ............................................................................................................ .........445 9.5 cautions ....................................................................................................................... ........... 446 chapter 10 watch timer functions ............................ .......................................................... 447 10.1 functions...................................................................................................................... ........... 447 10.2 configuration .................................................................................................................. ........ 449 10.3 control registers.............................................................................................................. ...... 450 10.4 operation ...................................................................................................................... ........... 452 10.4.1 operation as watch ti mer ....................................................................................................... .....452 10.4.2 operation as in terval timer .................................................................................................... ......452 10.4.3 cauti ons ....................................................................................................................... ...............453 10.5 prescaler 3.................................................................................................................... ........... 454 10.5.1 control r egister s.............................................................................................................. ............454 10.5.2 generation of watch ti mer count clock ........................................................................................45 5 chapter 11 functions of watchdog timer 2 .. ................................................................. 456 11.1 functions...................................................................................................................... ........... 456 11.2 configuration .................................................................................................................. ........ 457 11.3 control registers.............................................................................................................. ...... 457 chapter 12 a/d converter ................................................................................................... ...... 461 12.1 overview ....................................................................................................................... ........... 461 12.2 functions...................................................................................................................... ........... 461 12.3 configuration .................................................................................................................. ........ 463 12.4 control registers.............................................................................................................. ...... 464 12.5 operation ...................................................................................................................... ........... 473 12.5.1 basic oper ation ................................................................................................................ ...........473 12.5.2 trigger mode................................................................................................................... ............475 12.5.3 operati on m ode ................................................................................................................. .........477 12.5.4 power-fail co mpare mode ........................................................................................................ ...481 user?s manual u17830ee1v0um00 13 12.6 cautions ....................................................................................................................... ............486 12.7 how to read a/d converter characteristics table..... .........................................................491 chapter 13 asynchronous serial interface a (uarta) ..............................................495 13.1 features....................................................................................................................... .............496 13.2 configuration .................................................................................................................. .........497 13.2.1 control r egisters.............................................................................................................. ............ 499 13.3 control registers .............................................................................................................. ......500 13.4 interrupt request signals............................................. ......................................................... .508 13.5 operation...................................................................................................................... ............509 13.5.1 data fo rmat .................................................................................................................... ............. 509 13.5.2 sbf transmission/rec eption fo rmat ............................................................................................. 5 10 13.5.3 sbf trans missi on............................................................................................................... ......... 512 13.5.4 sbf rec eptio n .................................................................................................................. ........... 513 13.5.5 uart trans missi on .............................................................................................................. ....... 514 13.5.6 procedure of conti nuous transmi ssion ........................................................................................ 515 13.5.7 uart rec eptio n ................................................................................................................. ......... 517 13.5.8 reception errors ............................................................................................................... .......... 518 13.5.9 types and operati on of par ity.................................................................................................. .... 520 13.5.10 noise filter of rece ive dat a .......................................................................................... ................ 521 13.6 dedicated baud rate generator ................................... .........................................................522 13.7 cautions ....................................................................................................................... ............528 chapter 14 3-wire serial interface (csib) ......... ................................................................529 14.1 features....................................................................................................................... .............529 14.2 configuration .................................................................................................................. .........530 14.3 control registers .............................................................................................................. ......533 14.4 transfer data length change function................... .............................................................538 14.5 interrupt request signals............................................. ......................................................... .539 14.6 operation...................................................................................................................... ............540 14.6.1 single transfer mode (master mode, transmission/rec eption m ode) ........................................... 540 14.6.2 single transfer mode (master mode, recept ion m ode) ................................................................ 541 14.6.3 continuous mode (master mode, transmission/rec eption m ode) ................................................ 542 14.6.4 continuous mode (master m ode, recepti on mode) ..................................................................... 543 14.6.5 continuous recepti on mode (e rror) ............................................................................................. 5 44 14.6.6 continuous mode (slave mode, transmission/rec eption m ode)................................................... 545 14.6.7 continuous mode (slave m ode, recepti on mode) ........................................................................ 546 14.6.8 clock ti ming ................................................................................................................... ............. 547 14.7 output pins .................................................................................................................... ..........549 14.8 operation flow ................................................................................................................. .......550 14.9 prescaler 3 .................................................................................................................... ...........556 14.9.1 control registers of presca ler 3 ............................................................................................... .... 556 14.9.2 generation of count cl ock ...................................................................................................... ..... 557 14.10 cautions ....................................................................................................................... ............558 chapter 15 can controller ......................................... ......................................................... ....559 15.1 overview.................................................................................................................. .................559 15.1.1 f eatur es................................................................................................................ ...................... 559 user?s manual u17830ee1v0um00 14 15.1.2 overview of func tions................................................................................................... ..............560 15.1.3 confi guratio n........................................................................................................... ....................561 15.2 can protocol .............................................................................................................. ............ 562 15.2.1 fram e fo rmat............................................................................................................ ...................562 15.2.2 fram e ty pes ............................................................................................................. ...................563 15.2.3 data frame and remote frame ............................................................................................. ........563 15.2.4 erro r frame ............................................................................................................. .....................571 15.2.5 overl oad fram e .......................................................................................................... .................572 15.3 functions................................................................................................................. ................ 573 15.3.1 determining bus prio rity ................................................................................................ ..............573 15.3.2 bit stuffi ng ............................................................................................................ .......................573 15.3.3 multi masters........................................................................................................... ....................572 15.3.4 mult i ca st .............................................................................................................. .......................573 15.3.5 can sleep mode/can stop mode f unction .................................................................................57 4 15.3.6 error cont rol func tion.................................................................................................. .................574 15.3.7 baud rate c ontrol f unction .............................................................................................. .............581 15.4 connection with target system.................................. .......................................................... 5 85 15.5 internal registers of can controller ...................... .............................................................. 58 6 15.5.1 can controlle r configur ation ............................................................................................ ...........586 15.5.2 register access type.................................................................................................... ...............588 15.5.3 register bi t configur ation.............................................................................................. ...............656 15.6 control registers......................................................................................................... ........... 660 15.7 bit set/clear function .................................................................................................... ........ 694 15.8 can controller initialization ............................................................................................. ..... 696 15.8.1 initializati on of can module ............................................................................................ ............696 15.8.2 initialization of message buffer........................................................................................ ............696 15.8.3 redefinition of message buffer.......................................................................................... ..........695 15.8.4 transition from initializ ation mode to oper ation m ode .................................................................69 7 15.8.5 resetting error counter cnerc of ca n modul e .........................................................................698 15.9 message reception ......................................................................................................... ....... 699 15.9.1 message recept ion....................................................................................................... ...............699 15.9.2 receive hist ory list f uncti on........................................................................................... ..............700 15.9.3 mask functi on ........................................................................................................... ...................702 15.9.4 multi buffer rece ive block functi on ..................................................................................... ..........704 15.9.5 remote fr ame rec eption.................................................................................................. ............705 15.10 message transmission ..................................................................................................... ..... 706 15.10.1 message transmi ssion ................................................................................................... .............706 15.10.2 transmit hist ory list f uncti on......................................................................................... ...............708 15.10.3 automatic blo ck transmissi on (abt) ..................................................................................... ......710 15.10.4 transmission abort proc ess ............................................................................................. ...........712 15.10.5 remote fr ame trans mission .............................................................................................. ..........712 15.11 power saving modes....................................................................................................... ....... 713 15.11.1 can sleep m ode ......................................................................................................... ................713 15.11.2 can stop m ode.......................................................................................................... .................714 15.11.3 example of usi ng power sa ving m odes .................................................................................... ...715 15.12 interrupt function....................................................................................................... ............ 716 15.13 diagnosis functions and special operational mod es........................................................ 717 15.13.1 receiv e-only mode ...................................................................................................... ...............717 user?s manual u17830ee1v0um00 15 15.13.2 single- shot mode ....................................................................................................... ................. 718 15.13.3 self-t est m ode......................................................................................................... .................... 719 15.14 time stamp function ...................................................................................................... ........720 15.14.1 time st amp func tion.................................................................................................... ................ 720 15.15 baud rate settings ....................................................................................................... ..........722 15.15.1 bit rate setting c onditi ons............................................................................................ ................ 722 15.15.2 representativ e examples of baud rate setti ngs .......................................................................... 726 15.16 operation of can controller ................................... ........................................................... ....730 chapter 16 dma controller (dmac) ......................... .............................................................755 16.1 features....................................................................................................................... .............755 16.2 configuration .................................................................................................................. .........756 16.3 registers ...................................................................................................................... ............757 16.4 dma bus states................................................................................................................. ......766 16.4.1 types of bus states............................................................................................................ ......... 766 16.4.2 dmac bus cycle st ate trans ition ................................................................................................ . 767 16.5 transfer targets ............................................................. .................................................. .......768 16.6 transfer modes................................................................................................................. .......768 16.7 transfer types................................................................................................................. ........769 16.8 dma channel priorities ......................................................................................................... .770 16.9 time related to dma transfer ...............................................................................................770 16.10 dma transfer start factors......... ...........................................................................................7 71 16.11 dma abort factors.............................................................................................................. ....772 16.12 end of dma transfer............................................................................................................ ...772 16.13 operation timing............................................................................................................... ......772 16.14 cautions ....................................................................................................................... ............777 chapter 17 interrupt/exception processing fu nction ...............................................782 17.1 features....................................................................................................................... .............782 17.2 non-maskable interrupts .................... .................................................................................... 787 17.2.1 non-maskable interr upt request signal ....................................................................................... 787 17.2.2 operat ion ...................................................................................................................... .............. 789 17.2.3 restore ........................................................................................................................ ............... 790 17.2.4 np fl ag ........................................................................................................................ ................ 792 17.2.5 eliminating noise on nmi pin................................................................................................... .... 792 17.2.6 function to detect edge of nm i pin ............................................................................................. 792 17.3 maskable interrupts ............................................................................................................ ....794 17.3.1 operat ion ...................................................................................................................... .............. 794 17.3.2 restore ........................................................................................................................ ............... 796 17.3.3 priorities of ma skable inte rrupts.............................................................................................. .... 797 17.3.4 interrupt control r egisters ( xxicn)............................................................................................ .... 801 17.3.5 interrupt mask registers 0 to 5 (imr0 to im r4, imr 5l) .............................................................. 804 17.3.6 in-service priority register (ispr) ............................................................................................ .... 806 17.3.7 id flag ........................................................................................................................ ................. 807 17.3.8 watchdog timer mode regi ster 2 (w dtm2) ................................................................................ 807 17.3.9 eliminating noise on in tp0 to intp 7 pins .................................................................................. 808 17.4 software exceptions ............................................................................................................ ...818 17.4.1 operat ion ...................................................................................................................... .............. 818 user?s manual u17830ee1v0um00 16 17.4.2 restore ........................................................................................................................ ...............819 17.4.3 ep fl ag ........................................................................................................................ ................820 17.5 exception trap................................................................................................................. ....... 821 17.5.1 illegal opcode definit ion...................................................................................................... .........821 17.5.2 debug tr ap ..................................................................................................................... .............823 17.6 interrupt acknowledgment time of cpu ..................... ........................................................ 825 17.7 periods in which interrupts are not acknowledge d by cpu ............................................ 826 chapter 18 key interrupt function ........................... .......................................................... 827 18.1 function....................................................................................................................... ............ 827 18.2 control register............................................................................................................... ....... 828 chapter 19 standby function ................................................................................................ .. 829 19.1 overview ....................................................................................................................... ........... 829 19.2 halt mode...................................................................................................................... ........ 834 19.2.1 setting and operat ion st atus................................................................................................... .....834 19.2.2 releasing ha lt m ode ............................................................................................................ ....834 19.3 idle1 mode ..................................................................................................................... ........ 836 19.3.1 setting and operat ion st atus................................................................................................... .....836 19.3.2 releasing id le1 m ode ........................................................................................................... ....836 19.4 idle2 mode ..................................................................................................................... ........ 838 19.4.1 setting and operat ion st atus................................................................................................... .....838 19.4.2 releasing id le2 m ode ........................................................................................................... ....838 19.4.3 securing setup time after release of id le2 m ode....................................................................... 840 19.5 software stop mode ............................................................................................................. 841 19.5.1 setting and operat ion st atus................................................................................................... .....841 19.5.2 releasing softwar e stop mode .................................................................................................84 2 19.5.3 securing setup time after rel ease of software stop m ode.........................................................844 19.6 subclock operation mode ..................................................................................................... 845 19.6.1 setting and operat ion st atus................................................................................................... .....845 19.6.2 releasing subclock operation mode............................................................................................84 5 19.7 sub-idle mode .................................................................................................................. ..... 847 19.7.1 setting and operat ion st atus................................................................................................... .....847 19.7.2 releasing sub- idle mode ........................................................................................................ ..847 19.8 control registers.............................................................................................................. ...... 849 chapter 20 reset function .................................................................................................. ..... 852 20.1 overview ....................................................................................................................... ........... 852 20.2 register to check reset source ................................... ........................................................ 853 20.3 operation ...................................................................................................................... ........... 854 20.3.1 reset operation by reset pin .................................................................................................. 854 20.3.2 reset operation by wdt2res signal .........................................................................................856 chapter 21 clock monitor ................................................................................................... ..... 859 21.1 function of clock monitor ..................................................................................................... 8 59 21.2 configuration of clock monitor..................................... ........................................................ 859 21.3 register controlling clock monitor .............................. ........................................................ 860 21.4 operation of clock monitor ................................................................................................... 86 1 user?s manual u17830ee1v0um00 17 chapter 22 power-on clear circ uit .....................................................................................864 22.1 functions of power-on clear circuit............................ .........................................................864 22.2 configuration of power-on clear circuit ................. .............................................................865 22.3 operation of power-on clear circuit ........................... ..........................................................865 chapter 23 low-voltage detector .............................. ..........................................................866 23.1 functions of low-voltage detector... ....................................................................................866 23.2 configuration of low-voltage det ector ................................................................................866 23.3 registers controlling low-voltage detector ............. ..........................................................867 23.4 operation of low-voltage detector... ....................................................................................870 23.4.1 to use for inter nal rese t signal............................................................................................... ..... 870 23.4.2 to use for interr upt........................................................................................................... ........... 871 23.5 ram retention voltage detection operation .......... .............................................................872 chapter 24 regulator ........................................................................................................ ..........873 24.1 overview....................................................................................................................... ............873 24.2 operation...................................................................................................................... ............873 chapter 25 flash memory.................................................................................................... .......875 25.1 features....................................................................................................................... .............875 25.1.1 erasure unit ................................................................................................................... ............. 876 25.1.2 functional outlin e............................................................................................................. ........... 877 25.2 writing with flash programmer .................................... .........................................................879 25.3 programming environment ....................................................................................................879 25.4 communication mode............................................................................................................. 880 25.5 pin connection ................................................................................................................. .......885 25.5.1 flmd0 pin ...................................................................................................................... ............ 885 25.5.2 flmd1 pin ...................................................................................................................... ............ 886 25.5.3 serial inte rface pins .......................................................................................................... .......... 886 25.5.4 reset pin ...................................................................................................................... ............ 888 25.5.5 port pins (i ncluding nmi)...................................................................................................... ....... 888 25.5.6 other signal pi ns .............................................................................................................. ........... 888 25.5.7 power s upply ................................................................................................................... ........... 888 25.6 programming method ............................................................................................................. 889 25.6.1 flash memory cont rol ........................................................................................................... ...... 889 25.6.2 selecting communi cation m ode .................................................................................................. 8 90 25.6.3 communicati on comm ands......................................................................................................... 891 25.7 rewriting by self-programming.................................... .........................................................892 25.7.1 overvi ew....................................................................................................................... .............. 892 25.7.2 featur es....................................................................................................................... ............... 893 25.7.3 standard self-pr ogramming flow ................................................................................................. 894 25.7.4 flash f uncti ons................................................................................................................ ............ 895 25.7.5 pin proc essi ng ................................................................................................................. ........... 895 25.7.6 internal res ources used ........................................................................................................ ...... 896 chapter 26 option function ...................................... ........................................................... .....897 26.1 mask options ................................................................................................................... ........897 user?s manual u17830ee1v0um00 18 chapter 27 on-chip debug function (on-chip debug unit)........................................ 899 27.1 functional outline ............................................................................................................. ..... 899 27.1.1 type of on-ch ip debug unit..................................................................................................... .....899 27.1.2 debug func tions ................................................................................................................ ..........899 27.2 connection circuit example.................................................................................................. 901 27.3 interface signals .............................................................................................................. ....... 901 27.4 register ....................................................................................................................... ............ 903 27.5 operation ...................................................................................................................... ........... 904 27.6 rom security function .......................................................................................................... 906 27.6.1 security id .................................................................................................................... ..............906 27.6.2 setti ng........................................................................................................................ .................907 27.7 connection to n-wire emulator ............................................................................................ 909 27.7.1 kel connec tor.................................................................................................................. ...........909 27.8 cautions ....................................................................................................................... ........... 913 appendix a register index .................................................................................................. ....... 914 appendix b instruction set list ........................................................................................... .. 927 b.1 conventions .................................................................................................................... ........ 927 b.2 instruction set (in alphabetical order) ........................ ........................................................ 930 b.3 description of operating precautions............................. ..................................................... 937 appendix c revision history ................................................................................................ ..... 942 user?s manual u17830ee1v0um00 19 chapter 1 introduction the v850es/fe2, v850es/ff2, v850es/ fg2, v850es/fj2 are products of nec electronics? v850 series of single-chip microcontrollers for real-time control. 1.1 general the v850es/fe2, v850es/ff2, v850es/fg 2, v850es/fj2 are 32-bit single-chip microcontroller that include the v850es cpu core and integrate peripheral functions such as timers/counters, serial interfaces, and an a/d converter. these microcontrollers also incorporate a can (c ontroller area network) as an automotive lan. in addition to highly real-time responsive, 1-clock-pitch basic instructions, this microcontroller have instructions ideal for digital servo applications, such as multiplicati on instructions using a hardware multiplier, sum-of-products operation instructions, and bit manipulation instructions. this microcontroller can also realize a real-time control system that is highly cost ef fective and can be used in autom otive instrumentation fields. v850es/fe2, v850es/ff2, v850es/fg2, are models of the v850es/fj2 with reduced i/o, timer/counter, and serial interface functions (see 1.2 product development of v850es/fe2, v850es/ff2, v850es/fg2, and v850es/fj2 and table 1-1. functional outline of v850es/fe 2, v850es/ff2, v850es/fg2, and v850es/fj2 ). chapter 1 introduction user?s manual u17830ee1v0um00 20 1.2 product development of v850es/fe2, v850es/ff2, v850es/fg2, and v850es/fj2 pd70f3239 pd70f3237 v850es/fj2 pd70f3233 pd703233 v850es/ff2 pd70f3231 pd703231 v850es/fe2 144-pin plastic lqfp (fine pitch) (20 x 20) flash memory: 512 kb, ram: 20 kb flash memory: 256 kb, ram: 12 kb flash memory: 256 kb, ram: 12 kb mask rom: 256 kb, ram: 12 kb flash memory: 128 kb, ram: 6 kb mask rom: 128 kb, ram: 6 kb 80-pin plastic tqfp (fine pitch) (12 x 12) 64-pin plastic lqfp (fine pitch) (10 x 10) pd703232 mask rom: 128 kb, ram: 6 kb pd703230 mask rom: 64 kb, ram: 4 kb pd70f3236 pd70f3235 pd703235 v850es/fg2 flash memory: 256 kb, ram: 12 kb mask rom: 256 kb, ram: 12 kb flash memory: 384 kb, ram: 16 kb 100-pin plastic lqfp (fine pitch) (14 x 14) pd703234 mask rom: 128 kb, ram: 6 kb pd70f3234 flash memory: 128 kb, ram: 6 kb pd70f3232 flash memory: 128 kb, ram: 12 kb pd70f3238 flash memory: 376 kb, ram: 20 kb chapter 1 introduction user?s manual u17830ee1v0um00 21 1.3 features number of instructions: 83 minimum instruction execution time: 50 ns (main clock (f xx ) = 20 mhz) general-purpose registers: 32 bits 32 power-on clear function low-voltage detection function ring-osc: 200 khz (typ.) internal memory ram: 4/6/8/12/16/20 kb (see table 1-1 ) flash memory: 64/128/256/376/384/512kb (see table 1-1 ) interrupts/exceptions non-maskable interrupts (see table 1-1 ) maskable interrupts (see table 1-1 ) software exceptions 2 sources exception trap 1 sources i/o lines i/o ports: 128 timer/counters 16-bit interval timer m (tmm): 1 ch 16-bit timer/event counter p (tmp): 4 ch 16-bit timer/event counter q (tmq): 1 to 3 ch (see table 1-1 ) watch timer: 1 ch watchdog timer 2: 1 ch serial interface (sio) asynchronous serial interface a (uart): 2 to 4 (see table 1-1 ) 3-wire variable-length serial interface b (csib): 2 to 3ch (see table 1-1 ) can controller: 1 to 4 ch (see table 1-1 ) a/d converter 10-bit resolution: 10 to 24 ch (see table 1-1 ) clock generator main clock/subclock operation cpu clock in seven steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable internal oscillator: 200 khz typ. power save function halt/idle1/idle 2/software stop/subclock/sub-idle modes package 64-pin plastic lqfp (fine pitch) (10 10) 80-pin plastic tqfp (fine pitch) (12 12) 100-pin plastic lqfp (fine pitch) (14 14) 144-pin plastic lqfp (fine pitch) (20 20) chapter 1 introduction user?s manual u17830ee1v0um00 22 table 1-1. functional outline of v850es/fe 2, v850es/ff2, v850es/fg2, and v850es/fj2 series name v850es/fe2 v850es/ff2 v850es/fg2 v850es/fj2 part number pd70(f)3230 pd70(f)3231 pd703232 pd70f3232 pd70(f)3233 pd70(f)3234 pd70(f)3235 pd70(f)3236 pd70f)237 pd70(3238 pd70f3239 flash (bytes) 64k 128 k 128 k 256 k 128k 256k 384k 256k 376k 512k mask rom (bytes) 64k 128k 128k 256k 128k 256k - - - - internal memory ram (bytes) 4k 6k 6k 12k 12k 6k 12k 16k 12k 20k 20k dma none none provided provided main (internal) 20 mhz max. 20 mhz max. 20 mhz max. 20 mhz max. ring-osc 200 khz typ. 200 khz typ. 200 khz typ. 200 khz typ. operating clock subclock rc or crystal rc or crys tal rc or crystal rc or crystal i/o ports 51 67 84 128 a/d converter 10 bits 10 ch 10 bits 12 ch 10 bits 16 ch 10 bits 24 ch timers tmq 1 ch 1 ch 2 ch 3 ch tmp 4 ch 4 ch 4 ch 4 ch tmm 1 ch 1 ch 1 ch 1 ch wdt2 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch csi 2 ch 2 ch 2 ch 3 ch uart 2 ch 2 ch 3 ch 3 ch 4 ch serial interfaces can 1 ch 1 ch 2 ch 2 ch 4 ch external 8 ch 8 ch 11 ch 15 ch internal 35 ch 35 ch 50 ch 57 ch 67 ch interrupts nmi 1 ch 1 ch 1 ch 1 ch key return input 8 ch 8 ch 8 ch 8 ch clock monitor function provided provided provided provided poc/lvi function provided provided provided provided clock output function provided provided provided provided pcl output function provided provided provided provided other functions on-chip debug function provided (note) provided (note) provided (note) provided (note) external memory interface none none none provided operating voltage 3.5 v to 5.5 v 3.5 v to 5.5 v 3.5 v to 5.5 v 3.5 v to 5.5 v package 64-pin lqfp 80-pin tqfp 100-pin lqfp 144-pin lqfp note on flash version only ( pd70f323x) chapter 1 introduction user?s manual u17830ee1v0um00 23 1.4 ordering information ? v850es/fj2 part number note package on-chip flash memory can buffer quality grade remark pd70f3237m1gj(a)-uen pd70f3237m1gj(a1)-uen pd70f3237m1gj(a2)-uen without power-on clear function pd70f3237m2gj(a)-uen pd70f3237m2gj(a1)-uen pd70f3237m2gj(a2)-uen 256 kb with power-on clear function pd70f3238m1gj(a)-uen pd70f3238m1gj(a1)-uen pd70f3238m1gj(a2)-uen without power-on clear function pd70f3238m2gj(a)-uen pd70f3238m2gj(a1)-uen pd70f3238m2gj(a2)-uen 376 kb with power-on clear function pd70f3239m1gj(a)-uen pd70f3239m1gj(a1)-uen pd70f3239m1gj(a2)-uen without power-on clear function pd70f3239m2gj(a)-uen pd70f3239m2gj(a1)-uen pd70f3239m2gj(a2)-uen 144-pin plastic lqfp (fine pitch) (20 20) 512 kb 32 buffer/ch special with power-on clear function note : the operating ambient temperature of each quality grades is as follows. (a) 40 to +85 (a1) 40 to +110 (a2) 40 to +125 please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. chapter 1 introduction user?s manual u17830ee1v0um00 24 ? v850es/fg2 part number package internal memory number of can buffers quality grade remark pd703234gc(a)-xxx-8ea 100-pin plastic lqfp 128 kb 32 buffers/ch special note ? pd703234gc(a1)-xxx-8ea (fine pitch) (14 14) (mask rom) pd703234gc(a2)-xxx-8ea pd703235gc(a)-xxx-8ea 256 kb pd703235gc(a1)-xxx-8ea (mask rom) pd703235gc(a2)-xxx-8ea pd70f3234m1gc(a)-8ea 128 kb without power-on clear function pd70f3234m1gc(a1)-8ea (flash memory) pd70f3234m1gc(a2)-8ea pd70f3234m2gc(a)-8ea with power-on clear function pd70f3234m2gc(a1)-8ea pd70f3234m2gc(a2)-8ea pd70f3235m1gc(a)-8ea 256 kb without power-on clear function pd70f3235m1gc(a1)-8ea (flash memory) pd70f3235m1gc(a2)-8ea pd70f3235m2gc(a)-8ea with power-on clear function pd70f3235m2gc(a1)-8ea pd70f3235m2gc(a2)-8ea pd70f3236m1gc(a)-8ea 384 kb without power-on clear function pd70f3236m1gc(a1)-8ea (flash memory) pd70f3236m1gc(a2)-8ea pd70f3236m2gc(a)-8ea with power-on clear function pd70f3236m2gc(a1)-8ea pd70f3236m2gc(a2)-8ea note: the operating ambient temperature of each quality grades is as follows. (a) 40 to +85 (a1) 40 to +110 (a2) 40 to +125 remark xxx is rom code number. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. chapter 1 introduction user?s manual u17830ee1v0um00 25 ? v850es/ff2 part number package internal memory number of can buffers quality grade remark pd703232gk(a)-xxx-9eu 80-pin plastic tqfp 128 kb 32 buffers/ch special note ? pd703232gk(a1)-xxx-9eu (fine pitch) (12 12) (mask rom) pd703232gk(a2)-xxx-9eu pd703233gk(a)-xxx-9eu 256 kb pd703233gk(a1)-xxx-9eu (mask rom) pd703233gk(a2)-xxx-9eu pd70f3232m1gk(a)-9eu 128 kb without power-on clear function pd70f3232m1gk(a1)-9eu (flash memory) pd70f3232m1gk(a2)-9eu pd70f3232m2gk(a)-9eu with power-on clear function pd70f3232m2gk(a1)-9eu pd70f3232m2gk(a2)-9eu pd70f3233m1gk(a)-9eu 256 kb without power-on clear function pd70f3233m1gk(a1)-9eu (flash memory) pd70f3233m1gk(a2)-9eu pd70f3233m2gk(a)-9eu with power-on clear function pd70f3233m2gk(a1)-9eu pd70f3233m2gk(a2)-9eu note : the operating ambient temperature of each quality grades is as follows. (a) 40 to +85 (a1) 40 to +110 (a2) 40 to +125 remark xxx is rom code number. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. chapter 1 introduction user?s manual u17830ee1v0um00 26 ? v850es/fe2 part number package internal memory number of can buffers quality grade remark pd703230gb(a)-xxx-8ea 64-pin plastic lqfp 64 kb 32 buffers/ch special note ? pd703230gb(a1)-xxx-8ea (fine pitch) (10 10) (mask rom) pd703230gb(a2)-xxx-8ea pd703231gb(a)-xxx-8ea 128 kb pd703231gb(a1)-xxx-8ea (mask rom) pd703231gb(a2)-xxx-8ea pd70f3231m1gb(a)-8ea 128 kb without power-on clear function pd70f3231m1gb(a1)-8ea (flash memory) pd70f3231m1gb(a2)-8ea pd70f3231m2gb(a)-8ea with power-on clear function pd70f3231m2gb(a1)-8ea pd70f3231m2gb(a2)-8ea note : the operating ambient temperature of each quality grades is as follows. (a) 40 to +85 (a1) 40 to +110 (a2) 40 to +125 remark xxx is rom code number. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. 1.5 applications automotive body electrical systems (can controller equipped general-purpose products) chapter 1 introduction user?s manual u17830ee1v0um00 27 1.6 pin configuration (top view) ? v850es/fj2 ( pd70f3237) 144-pin plastic lqfp (fine pitch) (20 20) av ref0 av ss p10/intp9 p11/intp10 ev dd p00/tip31/top31 p01/tip30/top30 flmd0 v dd regc v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst p06/intp3 p40/sib0 p41/sob0 p42/sckb0 p30/txda0 p31/rxda0/intp7 p32/ascka0/tip00/top00/top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 p36/ctxd1 p37/crxd1 ev ss ev dd p38/txda2 p39/rxda2/intp8 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0/cs0 pcd3 pcd2 pcd1 pcd0 p915/intp6 p914/intp5 p913/intp4/pcl p912/sckb2 p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms p60/intp11 p61/intp12 p62/intp13 p63 p64 p65 p66 p67 p68 p69 p610/tiq20/toq20 p611/tiq21/toq21 p612/tiq22/toq22 p613/tiq23/toq23 p614 p615 p80/intp14 p81 p90/kr6/txda1 p91/kr7/rxda1 p92/tiq11/toq11 p93/tiq12/toq12 p94/tiq13/toq13 p95/tiq10/toq10 p96/tip21/top21 p97/sib1/tip20/top20 p98/sob1 p99/sckb1 p910/sib2 p911/sob2 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p712/ani12 p713/ani13 p714/ani14 p715/ani15 p120/ani16 p121/ani17 p122/ani18 p123/ani19 p124/ani20 p125/ani21 p126/ani22 p127/ani23 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 notes 1 ic: connect to vss directly mask rom products only flmd0: connect to vss in the normal operation mode. flash memory versions only flmd1: flash memory versions only notes 2 regc can be connect to vss via capacitor of 4.7uf chapter 1 introduction user?s manual u17830ee1v0um00 28 ? v850es/fj2 ( pd70f3238, pd70f3239) 144-pin plastic lqfp (fine pitch) (20 20) av ref0 av ss p10/intp9 p11/intp10 ev dd p00/tip31/top31 p01/tip30/top30 flmd0 v dd regc v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst p06/intp3 p40/sib0 p41/sob0 p42/sckb0 p30/txda0 p31/rxda0/intp7 p32/ascka0/tip00/top00/top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 p36/ctxd1 p37/crxd1 ev ss ev dd p38/txda2 p39/rxda2/intp8 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0/cs0 pcd3 pcd2 pcd1 pcd0 p915/intp6 p914/intp5 p913/intp4/pcl p912/sckb2 p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms p60/intp11 p61/intp12 p62/intp13 p63 p64 p65/ctxd2 p66/crxd2 p67/ctxd3 p68/crxd3 p69 p610/tiq20/toq20 p611/tiq21/toq21 p612/tiq22/toq22 p613/tiq23/toq23 p614 p615 p80/rxda3/intp14 p81/txda3 p90/kr6/txda1 p91/kr7/rxda1 p92/tiq11/toq11 p93/tiq12/toq12 p94/tiq13/toq13 p95/tiq10/toq10 p96/tip21/top21 p97/sib1/tip20/top20 p98/sob1 p99/sckb1 p910/sib2 p911/sob2 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p712/ani12 p713/ani13 p714/ani14 p715/ani15 p120/ani16 p121/ani17 p122/ani18 p123/ani19 p124/ani20 p125/ani21 p126/ani22 p127/ani23 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 notes 1 ic: connect to vss directly flmd0: connect to vss in the normal operation mode. flash memory versions only flmd1: flash memory versions only notes 2 regc can be connect to vss via capacitor of 4.7uf chapter 1 introduction user?s manual u17830ee1v0um00 29 ? v850es/fg2 ( pd70f3234, pd70f3235, pd70f3236) 100-pin plastic lqfp (fine pitch) (14 14) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 av r ef 0 av ss p 10 /i n tp 9 p 11 /i n tp 10 ev dd p 00 /tip 31 /top 31 p 01 /tip 30 /top 30 i c /[f l m d 0 ] v dd r eg c v ss x 1 x 2 r eset xt 1 xt 2 p 02 / n m i p 03 /i n tp 0 /a d t r g p 04 /i n tp 1 p 05 /i n tp 2 /[ dr st] p 06 /i n tp 3 p 40 /sib 0 p 41 /sob 0 p 42 /s c kb 0 p 30 /tx d a 0 41 p 31 / r x d a 0 /i n tp 7 p 32 /as c ka 0 /top 01 /tip 00 /top 00 p 33 /tip 01 /top 01 / c tx d0 p 34 /tip 10 /top 10 / cr x d0 p 35 /tip 11 /top 11 p 36 / c tx d p 37 / cr x d ev ss ev dd p 38 /tx d a 2 p 39 / r x d a 2 /i n tp 8 p 50 /k r0 /tiq 01 /toq 01 p 51 /k r1 /tiq 02 /toq 02 p 52 /k r2 /tiq 03 /toq 03 /[ dd i] p 53 /k r3 /tiq 00 /toq 00 /[ dd o] p 54 /k r4 /[ dc k] p 55 /k r5 /[ d m s] p 90 /k r6 /tx d a 1 p 91 /k r7 / r x d a 1 p 92 /tiq 11 /toq 11 p 93 /tiq 12 /toq 12 p 94 /tiq 13 /toq 13 p 95 /tiq 10 /toq 10 p 96 /tip 21 /top 21 p 97 /sib 1 /tip 20 /top 20 p d l4 p d l3 p d l2 p d l1 p d l0 bv dd bv ss p c t 6 p c t 4 p c t 1 p c t 0 p c m 3 p c m 2 p c m 1 / c l ko u t p c m 0 p c s 1 p c s 0 p 915 /i n tp 6 p 914 /i n tp 5 p 913 /i n tp 4 /p c l p 912 p 911 p 910 p 99 /s c kb 1 p 98 /sob 1 p 70 /a n i 0 p 71 /a n i 1 p 72 /a n i 2 p 73 /a n i 3 p 74 /a n i 4 p 75 /a n i 5 p 76 /a n i 6 p 77 /a n i 7 p 78 /a n i 8 p 79 /a n i 9 p 710 /a n i 10 p 711 /a n i 11 p 712 /a n i 12 p 713 /a n i 13 p 714 /a n i 14 p 715 /a n i 15 p dl13 p dl12 p dl11 p dl10 p dl9 p dl8 p dl7 p dl6 p dl5 /[f l m d1 ] 43 44 42 45 84 82 83 81 49 46 48 47 50 77 80 78 79 76 n o t e 1 n o t e 2 n o t e 1 notes 1 ic: connect to vss directly flmd0: connect to vss in the normal operation mode. flash memory versions only flmd1: flash memory versions only notes 2 regc can be connect to vss via capacitor of 4.7uf remark pins in brackets are valid only in pd70f3234, 70f3235, 70f3236 chapter 1 introduction user?s manual u17830ee1v0um00 30 ? v850es/ff2 ( pd70f3232, pd70f3233) 80-pin plastic tqfp (fine pitch) (12 12) avref0 av ss p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 ic/[flmd0] v dd regc v ss x1 x2 reset xt1 xt2 p05/intp2/[drst] p06/intp3 p40/sib0 p41/sob0 pdl3 pdl2 pdl1 pdl0 pct6 pct4 pct1 pct0 pcm3 pcm2 pcm1/clkout pcm0 pcs1 pcs0 p915/intp6 p914/intp5 p913/intp4/pcl p99/sckb1 p98/sob1 p97/sib1/tip20/top20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p42/sckb0 p30/txda0 p31/rxda0/intp7 p32/ascka0/tip00/top00/top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 p38 p39 ev ss ev dd p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/[ddi] p53/kr3/tiq00/toq00/[ddo] p54/kr4/[dck] p55/kr5/[dms] p90/kr6/txda1 p91/kr7/rxda1 p96/tip21/top21 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdl11 pdl10 pdl9 pdl8 pdl7 pdl6 pdl5/[flmd1] pdl4 note1 note1 note2 notes 1 ic: connect to vss directly flmd0: connect to vss in the normal operation mode. flash memory versions only flmd1: flash memory versions only notes 2 regc can be connect to vss via capacitor of 4.7uf remark pins in brackets are only valid for pd70f3232, 70f3233 chapter 1 introduction user?s manual u17830ee1v0um00 31 ? v850es/fe2 ( pd703230, pd70f3231) 64-pin plastic lqfp (fine pitch) (10 10) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 avref0 av ss ic/[flmd0] v dd regc v ss x1 x2 reset xt1 xt2 p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 32 p05/intp2/[drst] p06/intp3 p40/sib0 p41/sob0 p42/sckb0 p30/txda0 p31/rxda0/intp7 p32/ascka0/tip00/top00/top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/[ddi] p53/kr3/tiq00/toq00/[ddo] ev ss pdl1 pdl0 pcm1/clkout pcm0 p915/intp6 p914/intp5 p913/intp4/pcl p99/sckb1 p98/sob1 p97/sib1/tip20/top20 p96/tip21/top21 p91/kr7/rxda1 p90/kr6/txda1 p55/kr5/[dms] p54/kr4/[dck] ev dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 pdl7 pdl6 pdl5/[flmd1] pdl4 pdl3 pdl2 note1 note1 note2 note 1 ic: connect to vss directly flmd0: connect to vss in the normal operation mode. flash memory versions only flmd1: flash memory versions only note 2 regc can be connect to vss via capacitor of 4.7uf remark pins in brackets are only valid for pd70f3231 chapter 1 introduction user?s manual u17830ee1v0um00 32 pin identification ad0 to ad15: adtrg: ani0 to ani23: ascka0: astb: av ref0 : av ss : bv dd : bv ss : clkout: crxd0 to crxd3: cs0 to cs3: ctxd0 to ctxd3: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: intp0 to intp14: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p60 to p615: p70 to p715: p80, p81: p90 to p915: address/data bus a/d trigger input analog input asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output can receive data chip select can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request interrupt request from peripherals key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 8 port 9 p120 to p127: pcd0 to pcd3: pcl: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdl0 to pdl15: rd: regc: reset: rxda0 to rxda3: sckb0 to sckb2: sib0 to sib2: sob0 to sob2: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tiq00 to tiq03, tiq10 to tiq13, tiq20 to tiq23: top00, top01, top10, top11, top20, top21, top30, top31, toq01 to toq03, toq11 to toq13, toq20 to toq23: txda0 to txda3: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port 12 port cd programmable clock output port cm port cs port ct port dl read strobe regulator control reset receive data serial clock serial input serial output timer input timer input timer input timer input timer input timer input timer input timer output timer output timer output timer output timer output timer output timer output transmit data power supply ground wait write strobe low level data write strobe high level data crystal for main clock crystal for subclock chapter 1 introduction user?s manual u17830ee1v0um00 33 1.7 function block configuration 1.7.1 internal block diagram ? v850es/fj2 ( pd70f3237) nmi sob0 to sob2 sib0 to sib2 sckb0 to sckb2 intp0 to intp14 intc 16-bit timer/ counter q: 3 ch tip00 to tip30 tip01 to tip31 top00 to top30 top01 to top31 16-bit timer/ counter p: 4 ch dmac 256 kb ram flash memory 12 kb pc general- purpose registers 32 bits ? 32 multiplier 16 ? 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 ad0 to ad1 5 ports pcs0 to pcs7 pcm0 to pcm5 pct0 to pct7 pdl0 to pdl15 pcd0 to pcd3 p120 to p127 p90 to p915 p80, p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 16-bit interval timer m: 1 ch csib: 3 ch watch timer tiq00 to tiq20 tiq01 to tiq21 tiq02 to tiq22 tiq03 to tiq23 toq00 to toq20 toq01 to toq21 toq02 to toq22 toq03 to toq23 txda0 to txda2 rxda0 to rxda2 ascka0 uarta: 3 ch ctxd0, ctxd1 crxd0, crxd1 can: 2 ch instruction queue bcu memc watchdog timer 2 key return function kr0 to kr7 ani0 to ani23 av ss av ref0 adtrg a/d converter flmd0 flmd1 cg rg regulator clm poc pll v dd v ss regc bv dd bv ss ev dd ev ss pcl clkout xt1 xt2 x1 x2 reset on chip debug drst dms ddo dck ddi rcu rsu romc lvi note note: only poc version chapter 1 introduction user?s manual u17830ee1v0um00 34 ? v850es/fj2 ( pd70f3238 pd70f3239) nmi sob0 to sob2 sib0 to sib2 sckb0 to sckb2 intp0 to intp14 intc 16-bit timer/ counter q: 3 ch tip00 to tip30 tip01 to tip31 top00 to top30 top01 to top31 16-bit timer/ counter p: 4 ch dmac note 1 ram flash memory 20 kb pc general- purpose registers 32 bits ? 32 multiplier 16 ? 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 ad0 to ad15 flmd0 flmd1 ports cg rg regulator clm pll flmd0 pcs0 to pcs7 pcm0 to pcm5 pct0 to pct7 pdl0 to pdl15 pcd0 to pcd3 p120 to p127 p90 to p915 p80, p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 v dd v ss regc bv dd bv ss ev dd ev ss 16-bit interval timer m: 1 ch csib: 3 ch watch timer tiq00 to tiq20 tiq01 to tiq21 tiq02 to tiq22 tiq03 to tiq23 toq00 to toq20 toq01 to toq21 toq02 to toq22 toq03 to toq23 txda0 to txda3 rxda0 to rxda3 ascka0 uarta: 4 ch ctxd0 to ctxd3 crxd0 to crxd3 can: 4 ch instruction queue bcu memc watchdog timer 2 key return function kr0 to kr7 ani0 to ani23 av ss av ref0 adtrg a/d converter pcl clkout xt1 xt2 x1 x2 reset on chip debug drst dms ddo dck ddi rcu rsu romc poc lvi note 2 notes: 1 376 kb/512 kb (flash memory see table1-1) 2. poc version chapter 1 introduction user?s manual u17830ee1v0um00 35 ? v850es/fg2 ( pd70f3234, pd70f3235, pd70f3236) nmi sob0, sob1 sib0, sib1 sckb0, sckb1 intp0 to intp10 intc 16-bit timer/ counter q: 2 ch tip00 to tip30 tip01 to tip31 top00 to top30 top01 to top31 16-bit timer/ counter p: 4 ch dmac pc general- purpose register 32 bits ? 32 alu system registers 32-bit barrel shifter cpu ports pcs0, pcs1 pcm0 to pcm3 pct0, pct1, pct4, pct6 pdl0 to pdl13 p90 to p915 p70 to p715 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 16-bit interval timer m: 1 ch csib: 2ch watch timer tiq00 to tiq10 tiq01 to tiq11 tiq02 to tiq12 tiq03 to tiq13 toq00 to toq10 toq01 to toq11 toq02 to toq12 toq03 to toq13 txda0 to txda2 rxda0 to rxda2 ascka0 uarta: 3ch ctxd0, ctxd1 crxd0, crxd1 can: 2ch instruction queue bcu watchdog timer 2 key return function kr0 to kr7 ani0 to ani15 av ss av ref0 adtrg a/d converter flmd0 flmd1 cg rg regulator clm poc pll flmd0 v dd v ss regc bv dd bv ss ev dd ev ss pcl clkout xt1 xt2 x1 x2 reset on chip debug drst dms ddo dck ddi rcu rsu romc lvi note 1 ram rom note 2 multiplier 16 16 32 note 3 notes: 1 128/256/384kb (flash memory see table1-1) 128/256kb (mask rom see table1-1) 2 6/12/16kb (see table1-1) 3 poc version only chapter 1 introduction user?s manual u17830ee1v0um00 36 ? v850es/ff2 ( pd70f3232, pd70f3233) nmi sob0, sob1 sib0, sib1 sckb0, sckb1 intp0 to intp7 intc 16-bit timer/ counter q: 1 ch tip00 to tip30 tip01 to tip31 top00 to top30 top01 to top31 16-bit timer/ counter p: 4 ch pc general- purpose registers 32 bits ? 32 alu system registers 32-bit barrel shifter cpu ports pcs0,pcs1 pcm0 to pcm3 pct0,pct1,pct4,pct6 pdl0 to pdl11 p90,p91,p96 to p99,p913 to p915 p70 to p711 p50 to p55 p40 to p42 p30 to p35,p38, p39 p00 to p06 16-bit interval timer m: 1 ch csib: 2ch watch timer tiq00 tiq01 tiq02 tiq03 toq00 toq01 toq02 toq03 txda0, txda1 rxda0, rxda1 ascka0 uarta: 2ch ctxd0 crxd0 can: 1ch instruction queue bcu watchdog timer 2 key return function kr0 to kr7 ani0 to ani11 av ss av ref0 adtrg a/d converter flmd0 flmd1 cg rg regulator clm pll flmd0 v dd v ss regc ev dd ev ss pcl clkout xt1 xt2 x1 x2 reset on chip debug drst dms ddo dck ddi rcu rsu romc note 1 ram rom note 2 poc lvi multiplier 16 16 32 note 3 notes: 1 128/256 (flash memory see table1-1) 128/256kb (mask rom see table1-1) 2 6/12kb (see table1-1) 3 poc version only chapter 1 introduction user?s manual u17830ee1v0um00 37 ? v850es/fe2 ( pd703230, pd70f3231) nmi sob0, sob1 sib0, sib1 sckb0, sckb1 intp0 to intp7 intc 16-bit timer/ counter q: 1 ch tip00 to tip30 tip01 to tip31 top00 to top30 top01 to top31 16-bit timer/ counter p: 4 ch pc general- purpose register 32 bits ? 32 alu system registers 32-bit barrel shifter cpu ports on chip debug pcm0,pcm1 pdl0 to pdl7 p90,p91,p96 to p99,p913 to p915 p70 to p79 p50 to p55 p40 to p42 p30 to p35 p00 to p06 16-bit interval timer m: 1 ch csib: 2ch drst dms ddo dck ddi watch timer tiq00 tiq01 tiq02 tiq03 toq00 toq01 toq02 toq03 txda0, txda1 rxda0, rxda1 ascka0 uarta: 2ch ctxd0 crxd0 can: 1ch instruction queue bcu watchdog timer 2 key return function kr0 to kr7 ani0 to ani9 av ss av ref0 adtrg a/d converter rcu rsu romc flmd0 flmd1 cg rg regulator clm pll flmd0 v dd v ss regc ev dd ev ss pcl clkout xt1 xt2 x1 x2 reset note 1 ram rom note 2 poc lvi multiplier 16 16 32 note 3 notes: 1 128kb (flash memory see table1-1) 64/128kb (mask rom see table1-1) 2 4/6kb (see table1-1) 3 poc version only chapter 1 introduction user?s manual u17830ee1v0um00 38 1.7.2 internal units (1) cpu the cpu can execute almost all instruction processing, such as address calculati on, arithmetic and logic operations, and data transfer, in one clock under control of a five-stage pipeline. dedicated hardware units such as a multiplier (16 bits 16 bits ? 32 bits) and a barrel shifter (32 bits) are provided to speed up complicated instruction processing. (2) external memory control unit (memc) this unit starts necessary external bus cycles based on the physical addresses obtained by the cpu. if the cpu does not request the start of a bus cycle when it fetches an instructi on from an external memory area, this unit generates a prefetch address and prefetches an instruction code. the prefetched instruction code is sent to an internal instruction queue. (3) rom this is a flash memory of 512/384/376/ 256/128/64 kb mapped to addresses 0000000h- 007ffffh/0000000h-005ffffh /0000000h-005dfffh/00000 00h-003ffffh/0000000h- 001ffffh/0000000h-000ffffh. the cpu can access this memory in one clock when it fetches an instruction. (4) ram this is a ram of 20/16/12/6/4 kb m apped to addresses 3ffa 000h-3ffefffh/3ffb000h- 3ffefffh/3ffc000h-3ffefffh/3ffd 8000h-3ffefffh/3ffe000h-3ffefffh. the cpu can access this ram in one clock when it accesses data. (5) interrupt controller (intc) the interrupt controller processes interrupt requests (nmi and intp0 up to intp14 refer to table 1-1 ) from the on-chip peripheral hardware and external sources. eight levels of priorities can be specified for these interrupt requests, and multiple servicing control can be performed on interrupt sources. (6) clock generator (cg) two types of oscillators, a main clock (f xx ) and a subclock (f xt ), are provided. the cl ock generator generates seven types of clocks (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt ), of which one is supplied as the operating clock of the cpu (f cpu ). (7) ring-osc a ring-osc oscillator is provided. the oscillation freq uency is 200 khz (typ.). this ring-osc oscillator supplies a clock to watchdog timer 2 and timer m. (8) timers/counters 16-bit timer/event counter p (tmp), 16-bit timer/event counter q (tmq), and 16-bit interval timer m (tmm) are provided (refer to table 1-1 ). (9) watch timer this timer counts the reference time for watch counting from the subclock or f brg from prescaler 3. at the same time, it can also be used as an interv al timer that operates on the main clock. chapter 1 introduction user?s manual u17830ee1v0um00 39 (10) watchdog timer 2 this watchdog timer is used to detect a program loop and system errors. as the source clock of this timer, ring-osc, or main clock can be selected. when this watchdog timer overflows, it generates a non-maskable interrupt request signal (intwdt2) or system reset signal (wdt2res). (11) serial interface (sio) the v850es /fe2, v850es/ff2, v850es/fg2, v850es/fj2 have asynchronous serial interface a (uarta) and 3-wire variable-length serial interface b (csib) as serial interfaces, and up to seven channels can be used at the same time. uarta transfers data by using the txdan and rxdan pins (n = 0 up to 3 refer to table 1-1 ). csib transfers data by using the sobm, sibm, and sckbm pins (m = 0 up to 2 refer to table 1-1 ). uarta has a dedicated baud rate generator. (12) can controller the can controller is a small-scale digital data transmission system that transfers data between units. (13) a/d converter this is a high-speed, high-resolution 10-bit a/d converter with up to 24 analog input pins (refer to table 1-1) . this converter is a successive approximation type. (14) dma controller the v850es/fg2, v850es/fj2 has a f our-channel dma controller that tr ansfers data between the internal ram, on-chip peripheral i/o, and external memory, in response to interrupt requests from the on-chip peripheral i/o. (15) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to key input pins of eight channels. (16) on-chip debug function (flash memory product only) an on-chip debug function (flash memory product only) t hat uses the communication specifications of jtag (joint test action group) and that is used via an n-wire in-circuit emul ator is provided. the normal port function and on-chip debug function are selected by us ing the input level of a control pin and on-chip debug mode setting register (ocdm). (17) ports general-purpose port functions and control pin functions are available. for details, refer to chapter 4 port functions . user?s manual u17830ee1v0um00 40 chapter 2 pin functions this section explains the names and functions of the pins of the v850es/fe2, v850es/ff2, v850es/fg2, v850es/fj2. 2.1 pin function list 2.1.1 v850es/fe2 two i/o buffer power supplies, av ref0 and ev dd , are available.the relationship between the power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies (v850es/fe2) power supply corresponding pin av ref0 port 7 ev dd port 0, port 3, port 4, port 5, port 6, port 8, port 9, port cm, port dl, reset chapter 2 pin functions user?s manual u17830ee1v0um00 41 (1) port pins table 2-2. pin list (port pins v850es/fe2) pin name i/o function alternate function p00 tip31/top31 p01 tip30/top30 p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst p06 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. intp3 p30 txda0 p31 rxda0/intp7 p32 ascka0/tip00/top00/top01 p33 tip01/top01/ctxd0 p34 tip10/top10/crxd0 p35 i/o port 3 6-bit i/o port input/output can be specified in 1-bit units. tip11/top11 p40 sib0 p41 sob0 p42 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. sckb0 p50 kr0/tiq01/toq01 p51 kr1/tiq02/toq02 p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. kr5/dms p70 to p79 i/o port 7 10-bit i/o port input/output can be specified in 1-bit units. ani0 to ani9 p90 kr6/txda1 p91 kr7/rxda1 p96 tip21/top21 p97 sib1/tip20/top20 p98 sob1 p99 sckb1 p913 intp4/pcl p914 intp5 p915 i/o port 9 9-bit i/o port input/output can be specified in 1-bit units. intp6 pcm0 - pcm1 i/o port cm 2-bit i/o port input/output can be specified in 1-bit units. clkout pdl0 to pdl4 - pdl5 flmd1 pdl6, pdl7 i/o port dl 8-bit i/o port input/output can be specified in 1-bit units. - chapter 2 pin functions user?s manual u17830ee1v0um00 42 (2) non-port pins table 2-3. pin list (non-port pins v850es/fe2) (1/3) pin name i/o function alternate function nmi input external interrupt input (non-maskable, with analog noise eliminated) p02 note intp0 p03/adtrg intp1 p04 intp2 p05/drst intp3 p06 intp4 p913/pcl intp5 p914 intp6 p915 intp7 input external interrupt request input (maskable, with analog noise eliminated) p31/rxda0 tip00 external event/clock input (tmp00) p32/ascka0/top00/top01 tip01 external event input (tmp01) p33/top01/ctxd0 tip10 external event/clock input (tmp10) p34/top10/crxd0 tip11 external event input (tmp11) p35/top11 tip20 external event/clock input (tmp20) p97/sib1/top20 tip21 external event input (tmp21) p96/top21 tip30 external event/clock input (tmp30) p01/top30 tip31 input external event input (tmp31) p00/top31 top00 timer output (tmp00) p32/ascka0/tip00/top01 p32/ascka0/tip00/top00 top01 timer output (tmp01) p33/tip01/ctxd0 top10 timer output (tmp10) p34/tip10/crxd0 top11 timer output (tmp11) p35/tip11 top20 timer output (tmp20) p97/sib1/tip20 top21 timer output (tmp21) p96/tip21 top30 timer output (tmp30) p01/tip30 top31 output timer output (tmp31) p00/tip31 note: the nmi pin and p02 pin are an alternate-function pi n. this pin functions as the p02 pin after if has been reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1.the initial setting of the nmi pin is "no edge detected". select the nmi pin valid edge using intf0 and intr0 registers. chapter 2 pin functions user?s manual u17830ee1v0um00 43 table 2-3. pin list (non-port pins v850es/fe2) (2/3) pin name i/o function alternate function tiq00 external event/clock input (tmq00) p53/kr3/toq00/ddo tiq01 external event input (tmq01) p50/kr0/toq01 tiq02 external event input (tmq02) p51/kr1/toq02 tiq03 input external event input (tmq03) p52/kr2/toq03/ddi toq00 timer output (tmq00) p53/kr3/tiq00/ddo toq01 timer output (tmq01) p50/kr0/tiq01 toq02 timer output (tmq02) p51/kr1/tiq02 toq03 output timer output (tmq03) p52/kr2/tiq03/ddi sib0 serial receive data input (csib0) p40 sib1 input serial receive data input (csib1) p97/tip20/top20 sob0 serial transmit data output (csib0) p41 sob1 output serial transmit data output (csib1) p98 sckb0 serial clock i/o (csib0) p42 sckb1 i/o serial clock i/o (csib1) p99 rxda0 serial receive data input (uarta0) p31/intp7 rxda1 input serial receive data input (uarta1) p91/kr7 txda0 serial transmit data output (uarta0) p30 txda1 output serial transmit data output (uarta1) p90/kr6 ascka0 input baud rate clock input to uarta0 p32/tip00/top00/top01 crxd0 input can receive data input (can0) p34/tip10/top10 ctxd0 output can transmit data output (can0) p33/tip01/top01 ani0 to ani9 input analog voltage input to a/d converter p70 to p79 av ref0 input reference voltage input to a/d converter, and positive power supply pin for port 7 ? av ss ? ground potential for a/d converter (same potential as v ss ) ? adtrg input a/d converter external trigger input p03/intp0 kr0 p50/tiq01/toq01 kr1 p51/tiq02/toq02 kr2 p52/tiq03/toq03/ddi kr3 p53/tiq00/toq00/ddo kr4 p54/dck kr5 p55/dms kr6 p90/txda1 kr7 input key interrupt input p91/rxda1 chapter 2 pin functions user?s manual u17830ee1v0um00 44 table 2-3. pin list (non-port pins v850es/fe2) (2/3) pin name i/o function alternate function dms input debug mode select p55/kr5 ddi input debug data input p52/kr2/tiq03/toq03 ddo output debug data output p53/kr3/tiq00/toq00 dck input debug clock input p54/kr4 drst input debug reset input p05/intp2 cs0 to cs3 output chip select signal output pcs0 to pcs3 flmd0 ? flmd1 input flash programming mode setting pins pdl5 clkout output internal system clock output pcm1 pcl output clock output (timing output of x1 input clock and subclock) p913/intp4 regc ? regulator output stabilizing capacitor connection ? reset input system reset input ? x1 input ? x2 ? main clock resonator connection ? xt1 input ? xt2 ? subclock resonator connection ? v dd ? positive power supply pi n for internal circuitry ? v ss ? ground potential for internal circuitry ? ev dd ? positive power supply pin for extern al circuitry (same potential as v dd ) ? ev ss ? ground potential for external circuitry (same potential as v ss ) ? chapter 2 pin functions user?s manual u17830ee1v0um00 45 2.1.2 v850es/ff2 two i/o buffer power supplies, av ref0 and ev dd , are available. the relationship between the power supplies and the pins is shown below. table 2-4. pin i/o buffer power supplies (v850es/ff2) power supply corresponding pin av ref0 port 7 ev dd port 0, port 3, port 4, port 5, port 6, port 8, port 9, port cm, port cs, port ct, port dl, reset (1) port pins table 2-5. pin list (port pins v850es/ff2) (1/2) pin name i/o function alternate function p00 tip31/top31 p01 tip30/top30 p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst p06 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. intp3 p30 txda0 p31 rxda0/intp7 p32 ascka0/tip00/top00/top01 p33 tip01/top01/ctxd0 p34 tip10/top10/crxd0 p35 tip11/top11 p38 - p39 i/o port 3 8-bit i/o port input/output can be specified in 1-bit units. - p40 sib0 p41 sob0 p42 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. sckb0 p50 kr0/tiq01/toq01 p51 kr1/tiq02/toq02 p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. kr5/dms chapter 2 pin functions user?s manual u17830ee1v0um00 46 table 2-5. pin list (port pins v850es/ff2) (2/2) pin name i/o function alternate function p70 to p711 i/o port 7 12-bit i/o port input/output can be specified in 1-bit units. ani0 to ani11 p90 kr6/txda1 p91 kr7/rxda1 p96 tip21/top21 p97 sib1/tip20/top20 p98 sob1 p99 sckb1 p913 intp4/pcl p914 intp5 p915 i/o port 9 9-bit i/o port input/output can be specified in 1-bit units. intp6 pcm0 - pcm1 clkout pcm2, pcm3 i/o port cm 4-bit i/o port input/output can be specified in 1-bit units. - pcs0, pcs1 i/o port cs 2-bit i/o port input/output can be specified in 1-bit units. - pct0, pct1, pct4, pct6 i/o port ct 4-bit i/o port input/output can be specified in 1-bit units. - pdl0 to pdl4 - pdl5 flmd1 pdl6 to pdl11 i/o port dl 8-bit i/o port input/output can be specified in 1-bit units. - chapter 2 pin functions user?s manual u17830ee1v0um00 47 (2) non-port pins table 2-6. pin list (non-port pins v850es/ff2) (1/3) pin name i/o function alternate function nmi input external interrupt input (non-maskable, with analog noise eliminated) p02 note intp0 p03/adtrg intp1 p04 intp2 p05/drst intp3 p06 intp4 p913/pcl intp5 p914 intp6 p915 intp7 input external interrupt request input (maskable, with analog noise eliminated) p31/rxda0 tip00 external event/clock input (tmp00) p32/ascka0/top00/top01 tip01 external event input (tmp01) p33/top01/ctxd0 tip10 external event/clock input (tmp10) p34/top10/crxd0 tip11 external event input (tmp11) p35/top11 tip20 external event/clock input (tmp20) p97/sib1/top20 tip21 external event input (tmp21) p96/top21 tip30 external event/clock input (tmp30) p01/top30 tip31 input external event input (tmp31) p00/top31 top00 timer output (tmp00) p32/ascka0/tip00/top01 p32/ascka0/tip00/top00 top01 timer output (tmp01) p33/tip01/ctxd0 top10 timer output (tmp10) p34/tip10/crxd0 top11 timer output (tmp11) p35/tip11 top20 timer output (tmp20) p97/sib1/tip20 top21 timer output (tmp21) p96/tip21 top30 timer output (tmp30) p01/tip30 top31 output timer output (tmp31) p00/tip31 note: the nmi pin and p02 pin are an alternate-function pi n. this pin functions as the p02 pin after if has been reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1.the initial setting of the nmi pin is "no edge detected". select the nmi pin valid edge using intf0 and intr0 registers. chapter 2 pin functions user?s manual u17830ee1v0um00 48 table 2-6. pin list (non-port pins v850es/ff2) (2/3) pin name i/o function alternate function tiq00 external event/clock input (tmq00) p53/kr3/toq00/ddo tiq01 external event input (tmq01) p50/kr0/toq01 tiq02 external event input (tmq02) p51/kr1/toq02 tiq03 input external event input (tmq03) p52/kr2/toq03/ddi toq00 timer output (tmq00) p53/kr3/tiq00/ddo toq01 timer output (tmq01) p50/kr0/tiq01 toq02 timer output (tmq02) p51/kr1/tiq02 toq03 output timer output (tmq03) p52/kr2/tiq03/ddi sib0 serial receive data input (csib0) p40 sib1 input serial receive data input (csib1) p97/tip20/top20 sob0 serial transmit data output (csib0) p41 sob1 output serial transmit data output (csib1) p98 sckb0 serial clock i/o (csib0) p42 sckb1 i/o serial clock i/o (csib1) p99 rxda0 serial receive data input (uarta0) p31/intp7 rxda1 input serial receive data input (uarta1) p91/kr7 txda0 serial transmit data output (uarta0) p30 txda1 output serial transmit data output (uarta1) p90/kr6 ascka0 input baud rate clock input to uarta0 p32/tip00/top00/top01 crxd0 input can receive data input (can0) p34/tip10/top10 ctxd0 output can transmit data output (can0) p33/tip01/top01 ani0 to ani11 input analog voltage input to a/d converter p70 to p711 av ref0 input reference voltage input to a/d converter , and positive power supply pin for port 7 ? av ss ? ground potential for a/d converter (same potential as v ss ) ? adtrg input a/d converter external trigger input p03/intp0 kr0 p50/tiq01/toq01 kr1 p51/tiq02/toq02 kr2 p52/tiq03/toq03/ddi kr3 p53/tiq00/toq00/ddo kr4 p54/dck kr5 p55/dms kr6 p90/txda1 kr7 input key interrupt input p91/rxda1 chapter 2 pin functions user?s manual u17830ee1v0um00 49 table 2-6. pin list (non-port pins v850es/ff2) (2/3) pin name i/o function alternate function dms input debug mode select p55/kr5 ddi input debug data input p52/kr2/tiq03/toq03 ddo output debug data output p53/kr3/tiq00/toq00 dck input debug clock input p54/kr4 drst input debug reset input p05/intp2 flmd0 ? flmd1 input flash programming mode setting pins pdl5 clkout output internal system clock output pcm1 pcl output clock output (timing output of x1 input clock and subclock) p913/intp4 regc ? regulator output stabilizing capacitor connection ? reset input system reset input ? x1 input ? x2 ? main clock resonator connection ? xt1 input ? xt2 ? subclock resonator connection ? v dd ? positive power supply pi n for internal circuitry ? v ss ? ground potential for internal circuitry ? ev dd ? positive power supply pin for extern al circuitry (same potential as v dd ) ? ev ss ? ground potential for external circuitry (same potential as v ss ) ? chapter 2 pin functions user?s manual u17830ee1v0um00 50 2.1.3 v850es/fg2 three i/o buffer power supplies, av ref0, bv dd and ev dd , are available. the relationship between the power supplies and the pins is shown below. table 2-7. pin i/o buffer power supplies (v850es/fg2) power supply corresponding pin av ref0 port 7 ev dd port 0, port 1, port 3, port 4, port 5, port 9, reset bv dd port cm, port cs, port ct, port dl (1) port pins table 2-8. pin list (port pins v850es/fg2) (1/2) pin name i/o function alternate function p00 tip31/top31 p01 tip30/top30 p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst p06 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. intp3 p10 intp9 p11 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. intp10 p30 txda0 p31 rxda0/intp7 p32 ascka0/tip00/top00/top01 p33 tip01/top01/ctxd0 p34 tip10/top10/crxd0 p35 tip11/top11 p36 ctxd1 p37 crxd1 p38 txda2 p39 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. rxda2/intp8 p40 sib0 p41 sob0 p42 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. sckb0 chapter 2 pin functions user?s manual u17830ee1v0um00 51 table 2-8. pin list (port pins v850es/fg2) (2/2) pin name i/o function alternate function p50 kr0/tiq01/toq01 p51 kr1/tiq02/toq02 p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. kr5/dms p70 to p715 i/o port 7 16-bit i/o port input/output can be specified in 1-bit units. ani0 to ani15 p90 kr6/txda1 p91 kr7/rxda1 p92 tiq11/toq11 p93 tiq12/toq12 p94 tiq13/toq13 p95 tiq10/toq10 p96 tip21/top21 p97 sib1/tip20/top20 p98 sob1 p99 sckb1 p910 ? p911 ? p912 ? p913 intp4/pcl p914 intp5 p915 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. intp6 pcm0 ? pcm1 clkout pcm2, pcm3 i/o port cm 4-bit i/o port input/output can be specified in 1-bit units. ? pcs0, pcs1 i/o port cs 2-bit i/o port input/output can be specified in 1-bit units. ? ? pct0, pct1, pct4, pct6 i/o port ct 4-bit i/o port input/output can be specified in 1-bit units. ? pdl0 to pdl4 ? pdl5 flmd1 pdl6 to pdl13 i/o port dl 14-bit i/o port input/output can be specified in 1-bit units. ? chapter 2 pin functions user?s manual u17830ee1v0um00 52 (2) non-port pins table 2-9. pin list (non-port pins v850es/fg2) (1/3) pin name i/o function alternate function nmi input external interrupt input (non-maskable, with analog noise eliminated) p02 note intp0 p03/adtrg intp1 p04 intp2 p05/drst intp3 p06 intp4 p913/pcl intp5 p914 intp6 p915 intp7 p31/rxda0 intp8 p39/rxda2 intp9 p10 intp10 input external interrupt request input (maskable, with analog noise eliminated) p11 tip00 external event/clock input (tmp00) p32/ascka0/top00/top01 tip01 external event/clock input (tmp01) p33/top01/ctxd0 tip10 external event/clock input (tmp10) p34/top10/crxd0 tip11 external event/clock input (tmp11) p35/top11 tip20 external event/clock input (tmp20) p97/sib1/top20 tip21 external event/clock input (tmp21) p96/top21 tip30 external event/clock input (tmp30) p01/top30 tip31 input external event/clock input (tmp31) p00/top31 top00 timer output (tmp00) p32/ascka0/tip00/top01 p32/ascka0/tip00/top00 top01 timer output (tmp01) p33/tip01/ctxd0 top10 timer output (tmp10) p34/tip10/crxd0 top11 timer output (tmp11) p35/tip11 top20 timer output (tmp20) p97/sib1/tip20 top21 timer output (tmp21) p96/tip21 top30 timer output (tmp30) p01/tip30 top31 output timer output (tmp31) p00/tip31 tiq00 external event/clock input (tmq00) p53/kr3/toq00/ddo tiq01 external event input (tmq01) p50/kr0/toq01 tiq02 external event input (tmq02) p51/kr1/toq02 tiq03 input external event input (tmq03) p52/kr2/toq03/ddi note: the nmi pin and p02 pin are an alternate-function pi n. this pin functions as the p02 pin after if has been reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1.the initial setting of the nmi pin is "no edge detected". select the nmi pin valid edge using intf0 and intr0 registers. chapter 2 pin functions user?s manual u17830ee1v0um00 53 table 2-9. pin list (non-port pins v850es/fg2) (2/3) pin name i/o function alternate function tiq10 external event input (tmq10) p95/toq10 tiq11 external event input (tmq11) p92/toq11 tiq12 external event input (tmq12) p93/toq12 tiq13 input external event input (tmq13) p94/toq13 toq00 timer output (tmq00) p53/kr3/tiq00/ddo toq01 timer output (tmq01) p50/kr0/tiq01 toq02 timer output (tmq02) p51/kr1/tiq02 toq03 timer output (tmq03) p52/kr2/tiq03/ddi toq10 timer output (tmq10) p95/tiq10 toq11 timer output (tmq11) p92/tiq11 toq12 timer output (tmq12) p93/tiq12 toq13 output timer output (tmq13) p94/tiq13 sib0 serial receive data input (csib0) p40 sib1 input serial receive data input (csib1) p97/tip20/top20 sob0 serial transmit data output (csib0) p41 sob1 output serial transmit data output (csib1) p98 sckb0 serial clock i/o (csib0) p42 sckb1 i/o serial clock i/o (csib1) p99 rxda0 serial receive data input (uarta0) p31/intp7 rxda1 serial receive data input (uarta1) p91/kr7 rxda2 input serial receive data input (uarta2) p39/intp8 txda0 serial transmit data output (uarta0) p30 txda1 serial transmit data output (uarta1) p90/kr6 txda2 output serial transmit data output (uarta2) p38 ascka0 input baud rate clock input to uarta0 p32/tip00/top00/top01 crxd0 can receive data input (can0) p34/tip10/top10 crxd1 input can receive data input (can1) p37 ctxd0 can transmit data output (can0) p33/tip01/top01 ctxd1 output can transmit data output (can1) p36 ani0 to ani15 input analog voltage input to a/d converter p70 to p715 av ref0 input reference voltage input to a/d converter , and positive power supply pin for port 7 ? av ss ? ground potential for a/d converter (same potential as v ss ) ? adtrg input a/d converter external trigger input p03/intp0 kr0 p50/tiq01/toq01 kr1 p51/tiq02/toq02 kr2 p52/tiq03/toq03/ddi kr3 p53/tiq00/toq00/ddo kr4 p54/dck kr5 p55/dms kr6 input key interrupt input p90/txda1 chapter 2 pin functions user?s manual u17830ee1v0um00 54 kr7 p91/rxda1 table 2-9. pin list (non-port pins v850es/fg2) (3/3) pin name i/o function alternate function dms input debug mode select p55/kr5 ddi input debug data input p52/kr2/tiq03/toq03 ddo output debug data output p53/kr3/tiq00/toq00 dck input debug clock input p54/kr4 drst input debug reset input p05/intp2 flmd0 ? flmd1 input flash programming mode setting pins pdl5 clkout output internal system clock output pcm1 pcl output clock output (timing output of x1 input clock and subclock) p913/intp4 regc ? regulator output stabilizing capacitor connection ? reset input system reset input ? x1 input ? x2 ? main clock resonator connection ? xt1 input ? xt2 ? subclock resonator connection ? v dd ? positive power supply pi n for internal circuitry ? v ss ? ground potential for internal circuitry ? ev dd ? positive power supply pin for exte rnal circuitry (same potential as v dd ) ? ev ss ? ground potential for external circuitry (same potential as v ss ) ? bv dd ? positive power supply pin for exte rnal circuitry (same potential as v dd ) ? bv ss ? ground potential for external circuitry (same potential as v ss ) ? chapter 2 pin functions user?s manual u17830ee1v0um00 55 2.1.4 v850es/fj2 three i/o buffer power supplies, av ref0 , bv dd , and ev dd , are available. the relationship between the power supplies and the pins is shown below. table 2-10. pin i/o buffer power supplies (v850es/fj2) power supply corresponding pin av ref0 port 7, port 12 bv dd port cd, port cm port cs, port ct, port dl ev dd port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, reset chapter 2 pin functions user?s manual u17830ee1v0um00 56 (1) port pins table 2-11. pin list (port pins) (1/3) pin name i/o function alternate function p00 tip31/top31 p01 tip30/top30 p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst p06 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. intp3 p10 i/o intp9 p11 port 1 2-bit i/o port input/output can be specified in 1-bit units. intp10 p30 txda0 p31 rxda0/intp7 p32 ascka0/tip00/top00/top01 p33 tip01/top01/ctxd0 p34 tip10/top10/crxd0 p35 tip11/top11 p36 ctxd1 p37 crxd1 p38 txda2 p39 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. rxda2/intp8 p40 sib0 p41 sob0 p42 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. sckb0 p50 kr0/tiq01/toq01 p51 kr1/tiq02/toq02 p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. kr5/dms chapter 2 pin functions user?s manual u17830ee1v0um00 57 table 2-11. pin list (port pins) (2/3) pin name i/o function alternate function p60 intp11 p61 intp12 p62 intp13 p63 ? p64 ? p65 ctxd2 note 1 p66 crxd2 note 1 p67 ctxd3 note 1 p68 crxd3 note 1 p69 ? p610 tiq20/toq20 p611 tiq21/toq21 p612 tiq22/toq22 p613 tiq23/toq23 p614 ? p615 i/o port 6 16-bit i/o port input/output can be specified in 1-bit units. ? p70 to p715 i/o port 7 16-bit i/o port input/output can be specified in 1-bit units. ani0 to ani15 p80 rxda3/intp14 note 2 p81 i/o port 8 2-bit i/o port input/output can be specified in 1-bit units. txda3 note 2 p90 kr6/txda1 p91 kr7/rxda1 p92 tiq11/toq11 p93 tiq12/toq12 p94 tiq13/toq13 p95 tiq10/toq10 p96 tip21/top21 p97 sib1/tip20/top20 p98 sob1 p99 sckb1 p910 sib2 p911 sob2 p912 sckb2 p913 intp4/pcl p914 intp5 p915 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. intp6 notes 1. in the pd70f3237, alternate functions of the p65 to p68 pins (ctxd2, crxd2, ctxd3, and crxd3) are not available. 2. in the pd70f3237, the alternate functi ons of the p80 and p81 pins (rxda3 and txda3) are not available. the alternate f unction of the p80 pin in the pd70f3237 is intp14 only. chapter 2 pin functions user?s manual u17830ee1v0um00 58 table 2-11. pin list (port pins) (3/3) pin name i/o function alternate function p120 to p127 i/o port 12 8-bit i/o port input/output can be specified in 1-bit units. ani16 to ani23 pcd0 to pcd3 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. ? pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq pcm4 ? pcm5 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. ? pcs0 to pcs3 cs0 to cs3 pcs4 to pcs7 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. ? pct0 wr0 pct1 wr1 pct2 ? pct3 ? pct4 rd pct5 ? pct6 astb pct7 i/o port ct 8-bit i/o port input/output can be specified in 1-bit units. ? pdl0 to pdl4 ad0 to ad4 pdl5 ad5/flmd1 pdl6 to pdl15 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad6 to ad15 chapter 2 pin functions user?s manual u17830ee1v0um00 59 (2) non-port pins table 2-12. pin list (non-port pins) (1/4) pin name i/o function alternate function nmi note 1 input external interrupt input (non-maskable, with analog noise eliminated) p02 note 1 intp0 p03/adtrg intp1 p04 intp2 p05/drst intp3 p06 intp4 p913/pcl intp5 p914 intp6 p915 intp7 p31/rxda0 intp8 p39/rxda2 intp9 p10 intp10 p11 intp11 p60 intp12 p61 intp13 p62 intp14 input external interrupt request input (maskable, with analog noise eliminated) p80/rxda3 note 2 tip00 external event/clock input (tmp00) p32/ascka0/top00/top01 tip01 external event input (tmp01) p33/top01/ctxd0 tip10 external event/clock input (tmp10) p34/top10/crxd0 tip11 external event input (tmp11) p35/top11 tip20 external event/clock input (tmp20) p97/sib1/top20 tip21 external event input (tmp21) p96/top21 tip30 external event/clock input (tmp30) p01/top30 tip31 input external event input (tmp31) p00/top31 top00 timer output (tmp00) p32/ascka0/tip00/top01 p32/ascka0/tip00/top00 top01 timer output (tmp01) p33/tip01/ctxd0 top10 timer output (tmp10) p34/tip10/crxd0 top11 timer output (tmp11) p35/tip11 top20 timer output (tmp20) p97/sib1/tip20 top21 timer output (tmp21) p96/tip21 top30 timer output (tmp30) p01/tip30 top31 output timer output (tmp31) p00/tip31 notes 1. the nmi pin and p02 pin are an alternate-function pin. this pin functions as the p02 pin after if has been reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1.the initial setting of the nmi pin is "no edge detected". select the nmi pin valid edge using intf0 and intr0 registers. 2. in the pd70f3237, the alter nate functions of the p80 and p81 pi ns (rxda3 and txda3) are not available. the alternate f unction of the p80 pin in t he pd70f3237 is only intp14. chapter 2 pin functions user?s manual u17830ee1v0um00 60 table 2-12. pin list (non-port pins) (2/4) pin name i/o function alternate function tiq00 external event/clock input (tmq00) p53/kr3/toq00/ddo tiq01 external event input (tmq01) p50/kr0/toq01 tiq02 external event input (tmq02) p51/kr1/toq02 tiq03 external event input (tmq03) p52/kr2/toq03/ddi tiq10 external event input (tmq10) p95/toq10 tiq11 external event input (tmq11) p92/toq11 tiq12 external event input (tmq12) p93/toq12 tiq13 external event input (tmq13) p94/toq13 tiq20 external event/clock input (tmq20) p610/toq20 tiq21 external event input (tmq21) p611/toq21 tiq22 external event input (tmq22) p612/toq22 tiq23 input external event input (tmq23) p613/toq23 toq00 timer output (tmq00) p53/kr3/tiq00/ddo toq01 timer output (tmq01) p50/kr0/tiq01 toq02 timer output (tmq02) p51/kr1/tiq02 toq03 timer output (tmq03) p52/kr2/tiq03/ddi toq10 timer output (tmq10) p95/tiq10 toq11 timer output (tmq11) p92/tiq11 toq12 timer output (tmq12) p93/tiq12 toq13 timer output (tmq13) p94/tiq13 toq20 timer output (tmq20) p610/tiq20 toq21 timer output (tmq21) p611/tiq21 toq22 timer output (tmq22) p612/tiq22 toq23 output timer output (tmq23) p613/tiq23 sib0 serial receive data input (csib0) p40 sib1 serial receive data input (csib1) p97/tip20/top20 sib2 input serial receive data input (csib2) p910 sob0 serial transmit data output (csib0) p41 sob1 serial transmit data output (csib1) p98 sob2 output serial transmit data output (csib2) p911 sckb0 serial clock i/o (csib0) p42 sckb1 serial clock i/o (csib1) p99 sckb2 i/o serial clock i/o (csib2) p912 rxda0 serial receive data input (uarta0) p31/intp7 rxda1 serial receive data input (uarta1) p91/kr7 rxda2 serial receive data input (uarta2) p39/intp8 rxda3 note input serial receive data input (uarta3) p80/intp14 txda0 serial transmit data output (uarta0) p30 txda1 serial transmit data output (uarta1) p90/kr6 txda2 serial transmit data output (uarta2) p38 txda3 note output serial transmit data output (uarta3) p81 note in the pd70f3237, the alternate functions of the p80 and p81 pins (rxda3 and txda3) are not available. chapter 2 pin functions user?s manual u17830ee1v0um00 61 table 2-12. pin list (non-port pins) (3/4) pin name i/o function alternate function ascka0 input baud rate clock input to uarta0 p32/tip00/top00/top01 crxd0 can receive data input (can0) p34/tip10/top10 crxd1 can receive data input (can1) p37 crxd2 note can receive data input (can2) p66 crxd3 note input can receive data input (can3) p68 ctxd0 can transmit data output (can0) p33/tip01/top01 ctxd1 can transmit data output (can1) p36 ctxd2 note can transmit data output (can2) p65 ctxd3 note output can transmit data output (can3) p67 ani0 to ani15 p70 to p715 ani16 to ani23 input analog voltage input to a/d converter p120 to p127 av ref0 input reference voltage input to a/d converter, and positive power supply pin for port 7 ? av ss ? ground potential for a/d converter same potential as vss ? adtrg input a/d converter external trigger input p03/intp0 kr0 p50/tiq01/toq01 kr1 p51/tiq02/toq02 kr2 p52/tiq03/toq03/ddi kr3 p53/tiq00/toq00/ddo kr4 p54/dck kr5 p55/dms kr6 p90/txda1 kr7 input key interrupt input p91/rxda1 dms input debug mode select p55/kr5 ddi input debug data input p52/kr2/tiq03/toq03 ddo output debug data output p53/kr3/tiq00/toq00 dck input debug clock input p54/kr4 drst input debug reset input p05/intp2 cs0 to cs3 output chip select signal output pcs0 to pcs3 ad0 to ad4 pdl0 to pdl4 ad5 pdl5/flmd1 ad6 to ad15 i/o address/data bus for external memory pdl6 to pdl15 astb output address strobe signal output to external memory pct6 hldrq input bus hold request input pcm3 hldak output bus hold acknowledge output pcm2 rd output read strobe signal output to external memory pct4 wait input external wait input pcm0 wr0 write strobe to external memory (lower 8 bits) pct0 wr1 output write strobe to external memory (higher 8 bits) pct1 note in the pd70f3237, the alternate functi ons of the p65 to p68 pins (ctxd2, crxd2, ctxd3, and crxd3) are not available. chapter 2 pin functions user?s manual u17830ee1v0um00 62 table 2-12. pin list (non-port pins) (4/4) pin name i/o function alternate function flmd0 ? flmd1 input flash programming mode setting pins pdl5/ad5 clkout output internal system clock output pcm1 pcl output clock output (timing output of x1 input clock and subclock) p913/intp4 regc ? regulator output stabilizing capacitor connection ? reset input system reset input ? x1 input ? x2 ? main clock resonator connection ? xt1 input ? xt2 ? subclock resonator connection ? v dd ? positive power supply pi n for internal circuitry ? v ss ? ground potential for internal circuitry ? bv dd ? positive power supply for bus interface and port ? bv ss ? ground potential for bus interface and port ? ev dd ? positive power supply pin for extern al circuitry (same potential as v dd ) ? ev ss ? ground potential for external circuitry (same potential as v ss ) ? chapter 2 pin functions user?s manual u17830ee1v0um00 63 2.2 pin status (v850es/fj2) the v850es/fj2 has an external bus interface function t hat enables connection of external memories, such as rom and ram, and i/o. table 2-4 shows the operating stat us of each external bus interf ace pin in each operation mode. table 2-13. pin operating status in each operation mode bus control pin reset halt mode and dma transfer idle1, idle2, and software stop modes idle state note 2 bus hold ad0 to ad15 hi-z cs0 to cs3 h held hi-z wait ? ? ? clkout l operating operating wr0, wr1 rd astb hi-z hldak h h l hldrq hi-z note operating ? ? operating notes 1. the bus control pins function alternately as port pi ns and are initialized to the input mode (port mode). 2. pin status in the idle state that is inserted after the t3 state. remark hi-z: high impedance held: the state during the immediatel y preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged) chapter 2 pin functions user?s manual u17830ee1v0um00 64 2.3 description of pin functions 2.3.1 v850es/fe2 (1) p00 to p06 (port 0) ? 3-state i/o p00 to p06 function as a 7-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as nmi input, external interrupt request signal input, timer/counter i/o, external trigger of t he a/d converter, an d debug reset input. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by the intr0 and intf0 registers. an on-chip pull-up resistor can be connected to p00 to p06 by using pull-up resistor option register 0 (pu0). (a) port mode p00 to p06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable inte rrupt request) ? input this pin inputs a non-maskable interrupt request signal. (ii) intp0 to intp3 (interrupt request from peripherals) ? input these pins input external interrupt request signals. (iii) tip30, tip31 (timer input) ? input these pins input to timers p3 (tmp3). (iv) top30, top31 (timer output) ? output these pins output from timers p3 (tmp3). (v) adtrg (a/d trigger input) ? input this pin inputs an external trigger to the a/d conver ter. it is controlled by using a/d converter mode register 0 (ada0m0). (vi) drst (debug reset) ? input this pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip debug circuit. to deassert this signal, reset or in validate the on-chip debug circuit. deassert this signal when the debug function is not used. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . chapter 2 pin functions user?s manual u17830ee1v0um00 65 (2) p30 to p35 (port 3) ? 3-state output p30 to p35 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input, serial interface i/o, timer/counter i/o, and can data i/o. this port can be set in the port mode or control mode in 1-bit units. the valid edge of each pin is specified by using intr3 and intf3 registers. an on-chip pull-up resistor can be connected to p30 to p35 by using pull-up resistor option register 3 (pu3). (a) port mode p30 to p35 can be set in the input or output mode in 1-bit units, by using port mode register 3 (pm3). (b) control mode (i) rxda0 (receive data) ? input these pins input the serial receive data of uarta0. (ii) txda0 (transmit data) ? output these pins output the serial transmit data of uarta0. (iii) ascka0 (asynchronous serial clock) ? input this pin inputs uarta0. (iv) intp7 (interrupt request from peripherals) ? input these pins input an external interrupt request signal. (v) tip00, tip01, tip10, tip11 (timer input) ? input these pins input to timers p0 and p1 (tmp0, tmp1). (vi) top00, top01, top10, top11 (timer output) ? output these pins output from timers p0 and p1 (tmp0, tmp1). (vii) crxd0 (can receive data) ? input these pins input the receive data of can0. (viii) ctxd0 (can transmit data) ? output these pins output the transmit data of can0. chapter 2 pin functions user?s manual u17830ee1v0um00 66 (3) p40 to p42 (port 4) ? 3-state i/o p40 to p42 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o. this port can be set in the port mode or control mode in 1-bit units. an on-chip pull-up resistor can be connected to p40 to p42 by using pull-up resistor option register 4 (pu4). (a) port mode p40 to p42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (pm4). (b) control mode (i) sib0 (serial input) ? input this pin inputs the serial receive data of csib0. (ii) sob0 (serial output) ? output this pin outputs the serial transmit data of csib0. (iii) sckb0 (serial clock) ? 3-state i/o this pin inputs/outputs the serial clock of csib0. chapter 2 pin functions user?s manual u17830ee1v0um00 67 (4) p50 to p55 (port 5) ? 3-state i/o p50 to p55 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins oper ate as an i/o port, but also as timer/counter i/o, debug function i/o, and key interrupt input. this port can be set in the port mode or contro l mode in 1-bit units. an on-chip pull-up resistor can be connected to p50 to p55 by using pull-up resistor option register 5 (pu5). (a) port mode p50 to p55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (pm5). (b) control mode (i) kr0 to kr5 (key return) ? input these pins input a key interrupt. their operation is specified by using the key return mode register (krm) in the input port mode. (ii) tiq00, tiq01, tiq02, tiq03 (timer input) ? input these pins input to timers q0 (tmq0). (iii) toq00, toq01, toq02, toq03 (timer output) ? output these pins output from timers q0 (tmq0). (iv) ddi (debug data input) ? input this pin inputs debug data to the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (v) ddo (debug data output) ? output this pin outputs debug data from the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (iv) dck (debug clock input) ? input this pin inputs a debug clock to the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (vii) dms (debug mode select) ? input this pin selects the debug mode of the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (5) p70 to p79 (port 7) ? 3-state i/o p70 to p79 function as a 10-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as the analog input pins of the a/d converter in the control mode. when using this port as analog input pins, ho wever, set the port in the input mode. at this time, do not read the port. (a) port mode p70 to p79 can be set in the input or output mode in 1- bit units, by using port mode register 7l, h (pm7l, pm7h) chapter 2 pin functions user?s manual u17830ee1v0um00 68 (b) control mode p70 to p79 function alternately as the ani0 to ani9 pins. (i) ani0 to ani9 (analog input 0 to 9) ? input these pins input an analog signal to the a/d converter. (6) p90, p91, p96 to p99, p913 to p915 (port 9) ? 3-state i/o p90, p91, p96 to p99, p913 to p915 function as a 9-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o, ti mer/counter i/o, clock output, external interrupt request signal input, and key interrupt input. this port can be set in the port mode or control mode in 1-bit units. the valid edge of p913 to p915 is specified by using intf9h register. an on-chip pull-up resistor can be connected to p90, p91, p96 to p99, p913 to p915 by using pull-up resistor option register 9 (pu9). (a) port mode p90, p91, p96 to p99, p913 to p915 can be set in t he input or output mode in 1-bit units, by using port 9 mode register (pm9). (b) control mode (i) sib1 (serial input) ? input these pins input the serial receive data of csib1. (ii) sob1 (serial output) ? output these pins output the serial receive data of csib1. (iii) sckb1 (serial clock) ? 3-state i/o these pins input/output the serial clock of csib1. (iv) rxda1 (receive data) ? input this pin inputs the serial receive data of uarta1. (v) txda1 (transmit data) ? output this pin outputs the serial transmit data of uarta1. (vi) tip20, tip21 (timer input) ? input these pins input to timers p2 (tmp2). (vii) top20, top21 (timer output) ? output these pins output from timers p2 (tmp2). (viii) pcl (clock output) ? output this pin outputs a clock. (ix) intp4 to intp6 (interrupt request from peripherals) ? input these pins input an external interrupt request signal. chapter 2 pin functions user?s manual u17830ee1v0um00 69 (x) kr6, kr7 (key return) ? input these pins input a key interrupt. their operation is specified by the key return mode register (krm) in the input port mode. (7) pcm0, pcm1 (port cm) ? 3-state i/o pcm0, pcm1 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, and bus clock output. (a) port mode pcm0, pcm1 can be set in the input or output mode in 1-bit units, by using port mode register cm (pmcm). (b) control mode (i) clkout (clock output) ? output this pin outputs an internally generated bus clock. (8) pdl0 to pdl7 (port dl) ? 3-state i/o pdl0 to pdl7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. pdl5 also functions as the flmd1 pin when the flash memory is programmed (when a high level is input to fld0). at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl7 can be set in the input or output mode in 1-bit units, by using port mode register dl (pmdl). (9) reset (reset) ? input reset input is asynchronous input. when a signal wi th a fixed low level width is input to the reset pin regardless of the operating clock, the system is reset, taking precedenc e over all the other operations. this pin is used to release the standby mode (halt, idle , or stop), as well as for normal initialization/start. (10) x1, x2 (crystal for main clock) these pins are used to connect the res onator that generates the system clock. (11) xt1, xt2 (crystal for subclock) these pins are used to connect the re sonator that generates the subclock. (12) av ss (ground for analog) this is a ground pin for the a/d conv erter, and alternate-function ports. (13) av ref0 (analog reference voltage) ? input this pin supplies positive analog power to th e a/d converter and alternate-function ports. it also supplies a reference voltage to the a/d converter. (14) ev dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. chapter 2 pin functions user?s manual u17830ee1v0um00 70 (15) ev ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (16) v dd (power supply) this pin supplies positive power. connect all the v dd pins to a positive power supply. (17) v ss (ground) this is a ground pin. connect all the v ss pins to ground. (18) flmd0 (flash programming mode) input this is a signal input pin for flash memory programming mode. connect this pin to vss in the normal operation mode. (19) regc (regulator control) ? input this pin connects a capacitor for the regulator. chapter 2 pin functions user?s manual u17830ee1v0um00 71 2.3.2 v850es/ff2 (1) p00 to p06 (port 0) ? 3-state i/o p00 to p06 function as a 7-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as nmi input, external interrupt request signal input, timer/counter i/o, external trigger of t he a/d converter, an d debug reset input. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by the intr0 and intf0 registers. an on-chip pull-up resistor can be connected to p00 to p06 by using pull-up resistor option register 0 (pu0). (a) port mode p00 to p06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable inte rrupt request) ? input this pin inputs a non-maskable interrupt request signal. (ii) intp0 to intp3 (interrupt request from peripherals) ? input these pins input external interrupt request signals. (iii) tip30, tip31 (timer input) ? input these pins input to timers p3 (tmp3). (iv) top30, top31 (timer output) ? output these pins output from timers p3 (tmp3). (v) adtrg (a/d trigger input) ? input this pin inputs an external trigger to the a/d conver ter. it is controlled by using a/d converter mode register 0 (ada0m0). (vi) drst (debug reset) ? input this pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip debug circuit. to deassert this signal, reset or in validate the on-chip debug circuit. deassert this signal when the debug function is not used. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . chapter 2 pin functions user?s manual u17830ee1v0um00 72 (2) p30 to p35, p38, p39 (port 3) ? 3-state output p30 to p35, p38, p39 function as an 8-bit i/o port t hat can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input, serial interface i/o, timer/counter i/o, and can data i/o. this port can be set in the port mode or control mode in 1-bit units. the valid edge of each pin is specified by using intr3 and intf3 registers. an on-chip pull-up resistor can be connected to p30 to p3 5, p38, p39 by using pull- up resistor option register 3 (pu3). (a) port mode p30 to p35, p38, p39 can be set in the input or out put mode in 1-bit units, by using port mode register 3 (pm3). (b) control mode (i) rxda0 (receive data) ? input these pins input the serial receive data of uarta0. (ii) txda0 (transmit data) ? output these pins output the serial transmit data of uarta0. (iii) ascka0 (asynchronous serial clock) ? input this pin inputs of uarta0. (iv) intp7 (interrupt request from peripherals) ? input these pins input an external interrupt request signal. (v) tip00, tip01, tip10, tip11 (timer input) ? input these pins input to timers p0, p1 (tmp0, tmp1). (vi) top00, top01, top10, top11 (timer output) ? output these pins output from timers p0, p1 (tmp0, tmp1). (vii) crxd0 (can receive data) ? input these pins input the receive data of can0. (viii) ctxd0 (can transmit data) ? output these pins output the transmit data of can0. chapter 2 pin functions user?s manual u17830ee1v0um00 73 (3) p40 to p42 (port 4) ? 3-state i/o p40 to p42 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o. this port can be set in the port mode or control mode in 1-bit units. an on-chip pull-up resistor can be connected to p40 to p42 by using pull-up resistor option register 4 (pu4). (a) port mode p40 to p42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (pm4). (b) control mode (i) sib0 (serial input) ? input this pin inputs the serial receive data of csib0. (ii) sob0 (serial output) ? output this pin outputs the serial transmit data of csib0. (iii) sckb0 (serial clock) ? 3-state i/o this pin inputs/outputs the serial clock of csib0. chapter 2 pin functions user?s manual u17830ee1v0um00 74 (4) p50 to p55 (port 5) ? 3-state i/o p50 to p55 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins oper ate as an i/o port, but also as timer/counter i/o, debug function i/o, and key interrupt input. this port can be set in the port mode or contro l mode in 1-bit units. an on-chip pull-up resistor can be connected to p50 to p55 by using pull-up resistor option register 5 (pu5). (a) port mode p50 to p55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (pm5). (b) control mode (i) kr0 to kr5 (key return) ? input these pins input a key interrupt. their operation is specified by using the key return mode register (krm) in the input port mode. (ii) tiq00, tiq01, tiq02, tiq03 (timer input) ? input these pins input to timers q0 (tmq0). (iii) toq00, toq01, toq02, toq03 (timer output) ? output these pins output from timers q0 (tmq0). (iv) ddi (debug data input) ? input this pin inputs debug data to the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (v) ddo (debug data output) ? output this pin outputs debug data from the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (iv) dck (debug clock input) ? input this pin inputs a debug clock to the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (vii) dms (debug mode select) ? input this pin selects the debug mode of the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (5) p70 to p711 (port 7) ? 3-state i/o p70 to p711 function as a 12-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as the analog input pins of the a/d converter in the control mode. when using this port as analog input pins, ho wever, set the port in the input mode. at this time, do not read the port. (a) port mode p70 to p711 can be set in the input or output mode in 1-bit units, by using port mode register 7l, h (pm7l, pm7h). chapter 2 pin functions user?s manual u17830ee1v0um00 75 (b) control mode p70 to p711 function alternately as the ani0 to ani11 pins. (i) ani0 to ani11 (analog input 0 to 11) ? input these pins input an analog signal to the a/d converter. (6) p90, p91, p96 to p99, p913 to p915 (port 9) ? 3-state i/o p90, p91, p96 to p99, p913 to p915 function as a 9-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o, ti mer/counter i/o, clock output, external interrupt request signal input, and key interrupt input. this port can be set in the port mode or control mode in 1-bit units. the valid edge of p913 to p915 is specified by using intf9h register. an on-chip pull-up resistor can be connected to p90, p91, p96 to p99, p913 to p915 by using pull-up resistor option register 9 (pu9). (a) port mode p90, p91, p96 to p99, p913 to p915 can be set in t he input or output mode in 1-bit units, by using port 9 mode register (pm9). (b) control mode (i) sib1 (serial input) ? input these pins input the serial receive data of csib1. (ii) sob1 (serial output) ? output these pins output the serial receive data of csib1. (iii) sckb1 (serial clock) ? 3-state i/o these pins input/output the serial clock of csib1. (iv) rxda1 (receive data) ? input this pin inputs the serial receive data of uarta1. (v) txda1 (transmit data) ? output this pin outputs the serial transmit data of uarta1. (vi) tip20, tip21 (timer input) ? input these pins input to timers p2 (tmp2). (vii) top20, top21 (timer output) ? output these pins output from timers p2 (tmp2). (viii) pcl (clock output) ? output this pin outputs a clock. (ix) intp4 to intp6 (interrupt request from peripherals) ? input these pins input an external interrupt request signal. chapter 2 pin functions user?s manual u17830ee1v0um00 76 (x) kr6, kr7 (key return) ? input these pins input a key interrupt. their operation is specified by the key return mode register (krm) in the input port mode. (7) pcm0 to pcm3 (port cm) ? 3-state i/o pcm0 to pcm3 function as a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, and bus clock output. (a) port mode pcm0 to pcm3 can be set in the input or output mo de in 1-bit units, by using port mode register cm (pmcm). (b) control mode (i) clkout (clock output) ? output this pin outputs an internally generated bus clock. (13) pcs0, pcs1 (port cs) ? 3-state i/o pcs0, pcs1 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port. (a) port mode pcs0, pcs1 can be set in the input or output mode in 1-bit units, by using port mode register cs (pmcs). (14) pct0, pct1, pct4, pc t6 (port ct) ? 3-state i/o pct0, pct1, pct4, pct6 function as an 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port. (a) port mode pct0, pct1, pct4, pct6 can be se t in the input or out put mode in 1-bit units, by using port mode register ct (pmct). (8) pdl0 to pdl11 (port dl) ? 3-state i/o pdl0 to pdl11 function as a 12-bit i/o port that c an be set to input or output in 1-bit units. pdl5 also functions as the flmd1 pin when the flash memory is programmed (when a high level is input to fld0). at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl11 can be set in the input or output mo de in 1-bit units, by using port mode register dl (pmdl). (9) reset (reset) ? input reset input is asynchronous input. when a signal wi th a fixed low level width is input to the reset pin regardless of the operating clock, the system is reset, taking precedenc e over all the other operations. this pin is used to release the standby mode (halt, idle , or stop), as well as for normal initialization/start. (10) x1, x2 (crystal for main clock) these pins are used to connect the res onator that generates the system clock. chapter 2 pin functions user?s manual u17830ee1v0um00 77 (11) xt1, xt2 (crystal for subclock) these pins are used to connect the re sonator that generates the subclock. (12) av ss (ground for analog) this is a ground pin for the a/d conv erter, and alternate-function ports. (13) av ref0 (analog reference voltage) ? input this pin supplies positive analog power to th e a/d converter and alternate-function ports. it also supplies a reference voltage to the a/d converter. (14) ev dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. (15) ev ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (16) v dd (power supply) this pin supplies positive power. connect all the v dd pins to a positive power supply. (17) v ss (ground) this is a ground pin. connect all the v ss pins to ground. (18) flmd0 (flash programming mode) input this is a signal input pin for flash memory programming mode. connect this pin to vss in the normal operation mode. (19) regc (regulator control) ? input this pin connects a capacitor for the regulator. chapter 2 pin functions user?s manual u17830ee1v0um00 78 2.3.3 v850es/fg2 (1) p00 to p06 (port 0) ? 3-state i/o p00 to p06 function as a 7-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as nmi input, external interrupt request signal input, timer/counter i/o, external trigger of t he a/d converter, an d debug reset input. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by the intr0 and intf0 registers. an on-chip pull-up resistor can be connected to p00 to p06 by using pull-up resistor option register 0 (pu0). (a) port mode p00 to p06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable inte rrupt request) ? input this pin inputs a non-maskable interrupt request signal. (ii) intp0 to intp3 (interrupt request from peripherals) ? input these pins input external interrupt request signals. (iii) tip30, tip31 (timer input) ? input these pins input an external count clock to timer p3 (tmp3). (iv) top30, top31 (timer output) ? output these pins output a pulse signal from timer p3 (tmp3). (v) adtrg (a/d trigger input) ? input this pin inputs an external trigger to the a/d conver ter. it is controlled by using a/d converter mode register 0 (ada0m0). (vi) drst (debug reset) ? input this pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip debug circuit. to deassert this signal, reset or in validate the on-chip debug circuit. deassert this signal when the debug function is not used. for details, refer to chapter 26 on-chip debug function (on-chip debug unit) . (2) p10, p11 (port 1) ? 3-state i/o p10 and p11 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input in the control mode. this port can be set in the port mode or cont rol mode in 1-bit units. the valid edge of each pin is specified by intr1 and intf1 registers. an on-chip pull-up resistor can be connected to p10 and p11 by using pull-up resistor option register 1 (pu1). (a) port mode p10 and p11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (pm1). chapter 2 pin functions user?s manual u17830ee1v0um00 79 (b) control mode (i) intp9, intp10 (interrupt re quest from peripherals) ? input these pins input an external interrupt request signal. (3) p30 to p39 (port 3) ? 3-state i/o p30 to p39 function as a 10-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input, serial interface i/o, timer/counter i/o, and can data i/o. this port can be set in the port mode or control mode in 1-bit units. the valid edge of each pin is specified by using intr3 and intf3 registers. an on-chip pull-up resistor can be connected to p30 to p39 by using pull-up resistor option register 3 (pu3). (a) port mode p30 to p39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (pm3). (b) control mode (i) rxda0, rxda2 (receive data) ? input this pin inputs the serial receive data of uarta0. (ii) txda0, txda2 (transmit data) ? output this pin outputs the serial transmit data of uarta0. (iii) ascka0 (asynchronous serial clock) ? input this pin inputs of uarta0. (iv) intp7, intp8 (interrupt re quest from peripherals) ? input this pin inputs an external interrupt request signal. (v) tip00, tip01, tip10, tip11 (timer input) ? input these pins input an external count clo ck to timers p0, p1 (tmp0, tmp1). (vi) top00, top01, top10, top11 (timer output) ? output these pins output a pulse signal from timers p0, p1 (tmp0, tmp1). (vii) crxd0, crxd1 (can receive data) ? input these pins input the receive data of can0 and can1. (viii) ctxd0, ctxd1 (can transmit data) ? output these pins output the trans mit data of can0 and can1. (4) p40 to p42 (port 4) ? 3-state i/o p40 to p42 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o. this port can be set in the port mode or control mode in 1-bit units. an on-chip pull-up resistor can be connected to p40 to p42 by using pull-up resistor option register 4 (pu4). chapter 2 pin functions user?s manual u17830ee1v0um00 80 (a) port mode p40 to p42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (pm4). (b) control mode (i) sib0 (serial input) ? input this pin inputs the serial receive data of csib0. (ii) sob0 (serial output) ? output this pin outputs the serial transmit data of csib0. (iii) sckb0 (serial clock) ? 3-state i/o this pin inputs/outputs the serial clock of csib0. (5) p50 to p55 (port 5) ? 3-state i/o p50 to p55 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins oper ate as an i/o port, but also as timer/counter i/o, debug function i/o, and key interrupt input. this port can be set in the port mode or contro l mode in 1-bit units. an on-chip pull-up resistor can be connected to p50 to p55 by using pull-up resistor option register 5 (pu5). (a) port mode p50 to p55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (pm5). (b) control mode (i) kr0 to kr5 (key return) ? input these pins input a key interrupt. their operation is specified by using the key return mode register (krm) in the input port mode. (ii) tiq00, tiq01, tiq02, tiq03 (timer input) ? input these pins input an external c ount clock to timer q0 (tmq0). (iii) toq00, toq01, toq02, toq03 (timer output) ? output these pins output a pulse signal from timer q0 (tmq0). (iv) ddi (debug data input) ? input this pin inputs debug data to the on-chip debug circuit. for details, refer to chapter 26 on-chip debug function (on-chip debug unit) . (v) ddo (debug data output) ? output this pin outputs debug data from the on-chip debug circuit. for details, refer to chapter 26 on-chip debug function (on-chip debug unit) . (iv) dck (debug clock input) ? input this pin inputs a debug clock to the on-chip debug circuit. for details, refer to chapter 26 on-chip debug function (on-chip debug unit) . chapter 2 pin functions user?s manual u17830ee1v0um00 81 (vii) dms (debug mode select) ? input this pin selects the debug mode of the on-chip debug circuit. for details, refer to chapter 26 on-chip debug function (on-chip debug unit) . (6) p70 to p715 (port 7) ? 3-state i/o p70 to p715 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as the analog input pins of the a/d converter in the control mode. when using this port as analog input pins, ho wever, set the port in the input mode. at this time, do not read the port. (a) port mode p70 to p715 can be set in the input or output mode in 1-bit units, by using port mode register 7l, h (pm7l, pm7h). (b) control mode p70 to p715 function alternately as the ani0 to ani15 pins. (i) ani0 to ani15 (analog input 0 to 15) ? input these pins input an analog signal to the a/d converter. (7) p90 to p915 (port 9) ? 3-state i/o p90 to p915 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o, ti mer/counter i/o, clock output, external interrupt request signal input, and key interrupt input. this port can be set in the port mode or control mode in 1-bit units. the valid edge of p913 to p915 is specified by using intr9h and intf9h registers. an on-chip pull-up resistor can be connected to p90 to p915 by using pull-up resistor option register 9 (pu9). (a) port mode p90 to p915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (pm9). (b) control mode (i) sib1 (serial input) ? input this pin inputs the serial receive data of csib1. (ii) sob1 (serial output) ? output this pin outputs the serial receive data of csib1. (iii) sckb1 (serial clock) ? 3-state i/o this pin inputs/outputs the serial clock of csib1. (iv) rxda1 (receive data) ? input this pin inputs the serial receive data of uarta1. (v) txda1 (transmit data) ? output this pin outputs the serial transmit data of uarta1. chapter 2 pin functions user?s manual u17830ee1v0um00 82 (vi) tip20, tip21 (timer input) ? input these pins input timers p2 (tmp2). (vii) top20, top21 (timer output) ? output these pins output a pulse signal from timers p2 (tmp2). (viii) tiq10, tiq11, tiq12, tiq13 (timer input) ? input these pins input to timers q1 (tmq1), respectively. (ix) toq10, toq11, toq12, toq13 (timer output) ? output these pins output a pulse signal from timers q1 (tmq1), respectively. (x) pcl (clock output) ? output this pin outputs a clock. (xi) intp4 to intp6 (interrupt request from peripherals) ? input these pins input an external interrupt request signal. (xii) kr6, kr7 (key return) ? input these pins input a key interrupt. their operation is specified by key return mode register (krm) in the input port mode. (8) pcm0 to pcm3 (port cm) ? 3-state i/o pcm0 to pcm3 function as a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, thes e pins operate as bus clock output. (a) port mode pcm0 to pcm3 can be set in the input or output mo de in 1-bit units, by using port mode register cm (pmcm). (b) control mode (i) clkout (clock output) ? output this pin outputs an internally generated bus clock. (9) pcs0, pcs1 (port cs) ? 3-state i/o pcs0 and pcs1 function as a 2-bit i/o port that can be set to input or output in 1-bit units. (a) port mode pcs0 and pcs1 can be set in the input or output mode in 1-bit units, by using port mode register cs (pmcs). (10) pct0, pct1, pct4, pc t6 (port ct) ? 3-state i/o pct0, pct1, pct4, and pct6 function as a 4-bit i/o port that can be set to input or output in 1-bit units. (a) port mode pct0, pct1, pct4, and pct6 can be set in the input or output mode in 1-bit units, by using port mode register ct (pmct). chapter 2 pin functions user?s manual u17830ee1v0um00 83 (11) pdl0 to pdl13 (port dl) ? 3-state i/o pdl0 to pdl13 function as a 14-bit i/o port that c an be set to input or output in 1-bit units. pdl5 also functions as the flmd1 pin when the flash memory is programmed (when a high level is input to flmd0). at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl13 can be set in the input or output mo de in 1-bit units, by using port mode register dl (pmdl). (12) reset (reset) ? input reset input is asynchronous input. when a signal wi th a fixed low level width is input to the reset pin regardless of the operating clock, the system is reset, taking precedenc e over all the other operations. this pin is used to release the standby mode (halt, idle , or stop), as well as for normal initialization/start. (13) x1, x2 (crystal for main clock) these pins are used to connect the res onator that generates the system clock. (14) xt1, xt2 (crystal for subclock) these pins are used to connect the re sonator that generates the subclock. (15) av ss (ground for analog) this is a ground pin for the a/d conv erter, and alternate-function ports. (16) av ref0 (analog reference voltage) ? input this pin supplies positive analog power to th e a/d converter and alternate-function ports. it also supplies a reference voltage to the a/d converter. (17) ev dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. (18) ev ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (19) v dd (power supply) this pin supplies positive power. connect all the v dd pins to a positive power supply. (20) v ss (ground) this is a ground pin. connect all the v ss pins to ground. (21) flmd0 (flash programming mode) input this is a signal input pin for flash memory programming mode. connect this pin to vss in the normal operation mode. (22) bv dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. (23) bv ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (24) regc (regulator control) ? input this pin connects a capacitor for the regulator. chapter 2 pin functions user?s manual u17830ee1v0um00 84 2.3.4 v850es/fj2 (1) p00 to p06 (port 0) ? 3-state i/o p00 to p06 function as a 7-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as nmi input, external interrupt request signal input, timer/counter i/o, external trigger of t he a/d converter, an d debug reset input. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by the intr0 and intf0 registers. an on-chip pull-up resistor can be connected to p00 to p06 by using pull-up resistor option register 0 (pu0). (a) port mode p00 to p06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable inte rrupt request) ? input this pin inputs a non-maskable interrupt request signal. (ii) intp0 to intp3 (interrupt request from peripherals) ? input these pins input external interrupt request signals. (iii) tip30, tip31 (timer input) ? input these pins input to timers p3 (tmp3). (iv) top30, top31 (timer output) ? output these pins output from timers p3 (tmp3). (v) adtrg (a/d trigger input) ? input this pin inputs an external trigger to the a/d conver ter. it is controlled by using a/d converter mode register 0 (ada0m0). (vi) drst (debug reset) ? input this pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip debug circuit. to deassert this signal, reset or in validate the on-chip debug circuit. deassert this signal when the debug function is not used. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . chapter 2 pin functions user?s manual u17830ee1v0um00 85 (2) p10, p11 (port 1) ? 3-state i/o p10 and p11 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request i nput in the control mode. this port can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by intr1 and intf1 registers. an on-chip pull-up resistor can be connected to p10 and p11 by using pull-up resistor option register 1 (pu1). (a) port mode p10 and p11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (pm1). (b) control mode (i) intp9, intp10 (interrupt re quest from peripherals) ? input these pins input an external interrupt request signal. (3) p30 to p39 (port 3) ? 3-state output p30 to p39 function as a 10-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input, serial interface i/o, timer/counter i/o, and can data i/o. this port can be set in the port mode or control mode in 1-bit units. the valid edge of each pin is specified by using intr3 and intf3 registers. an on-chip pull-up resistor can be connected to p30 to p39 by using pull-up resistor option register 3 (pu3). (a) port mode p30 to p39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (pm3). (b) control mode (i) rxda0, rxda2 (receive data) ? input these pins input the serial receive data of uarta0 and uarta2. (ii) txda0, txda2 (transmit data) ? output these pins output the serial trans mit data of uarta0 and uarta2. (iii) ascka0 (asynchronous serial clock) ? input this pin inputs of uarta0. (iv) intp7, intp8 (interrupt re quest from peripherals) ? input these pins input an external interrupt request signal. (v) tip00, tip01, tip10, tip11 (timer input) ? input these pins input to timers p0 and p1 (tmp0, tmp1). (vi) top00, top01, top10, top11 (timer output) ? output these pins output from timers p0 and p1 (tmp0, tmp1). (vii) crxd0, crxd1 (can receive data) ? input these pins input the receive data of can0 and can1. chapter 2 pin functions user?s manual u17830ee1v0um00 86 (viii) ctxd0, ctxd1 (can transmit data) ? output these pins output the trans mit data of can0 and can1. (4) p40 to p42 (port 4) ? 3-state i/o p40 to p42 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o. this port can be set in the port mode or control mode in 1-bit units. an on-chip pull-up resistor can be connected to p40 to p42 by using pull-up resistor option register 4 (pu4). (a) port mode p40 to p42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (pm4). (b) control mode (i) sib0 (serial input) ? input this pin inputs the serial receive data of csib0. (ii) sob0 (serial output) ? output this pin outputs the serial transmit data of csib0. (iii) sckb0 (serial clock) ? 3-state i/o this pin inputs/outputs the serial clock of csib0. (5) p50 to p55 (port 5) ? 3-state i/o p50 to p55 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, these pins oper ate as an i/o port, but also as timer/counter i/o, debug function i/o, and key interrupt input. this port can be set in the port mode or contro l mode in 1-bit units. an on-chip pull-up resistor can be connected to p50 to p55 by using pull-up resistor option register 5 (pu5). (a) port mode p50 to p55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (pm5). (b) control mode (i) kr0 to kr5 (key return) ? input these pins input a key interrupt. their operation is specified by using the key return mode register (krm) in the input port mode. (ii) tiq00, tiq01, tiq02, tiq03 (timer input) ? input these pins input to timers q0 (tmq0). (iii) toq00, toq01, toq02, toq03 (timer output) ? output these pins output from timers q0 (tmq0). (iv) ddi (debug data input) ? input this pin inputs debug data to the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . chapter 2 pin functions user?s manual u17830ee1v0um00 87 (v) ddo (debug data output) ? output this pin outputs debug data from the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (iv) dck (debug clock input) ? input this pin inputs a debug clock to the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (vii) dms (debug mode select) ? input this pin selects the debug mode of the on-chip debug circuit. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . (6) p60 to p615 ? 3-state i/o p60 to p615 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as external interrupt request signal input, timer/counter i/o, and can data i/o. p60 to p62 can be set in the port mode or control mode in 1- bit units. the valid edge of each pin is specified by intr6l and intf6l registers. (a) port mode p60 to p65 can be set in the input or output mode in 1-bit units, by using port mode register 6 (pm6). (b) control mode (i) intp11 to intp13 (interrupt re quest from peripherals) ? input these pins input an external interrupt request signal. (ii) tiq20, tiq21, tiq22, tiq23 (timer input) ? input these pins input to timers q2 (tmq2). (iii) toq20, toq21, toq22, toq23 (timer output) ? input these pins output from timers q2 (tmq2). (iv) crxd2, crxd3 (can receive data) note ? input these pins input the receive data of can2 and can3. (v) ctxd2, ctxd3 (can transmit data) note ? output these pins output the trans mit data of can2 and can3. note in the pd70f3237, the alternate func tions of the p65 to p68 pins (ctxd2, crxd2, ctxd3, and crxd3) are not available. (7) p70 to p715 (port 7) ? 3-state i/o p70 to p715 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as the analog input pins of the a/d converter in the control mode. when using this port as analog input pins, ho wever, set the port in the input mode. at this time, do not read the port. (a) port mode p70 to p715 can be set in the input or output mode in 1-bit units, by using port mode register 7l, h (pm7l, pm7h). chapter 2 pin functions user?s manual u17830ee1v0um00 88 (b) control mode p70 to p715 function alternately as the ani0 to ani15 pins. (i) ani0 to ani15 (analog input 0 to 15) ? input these pins input an analog signal to the a/d converter. (8) p80 and p81 (port 8) ? 3-state i/o p80 and p81 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operat e as external interrupt request signal input, and serial interface i/o. p80 and p81 can be set in the port mode or control mode in 1-bit units. the valid edge of each pin is specified by intr8 and intf8 registers. an on-chip pull-up resistor can be connected to p80 and p81 by using pull-up resistor option register 8 (pu8). (a) port mode p80 and p81 can be set in the input or output mode in 1-bit units, by using port mode register 8 (pm8). (b) control mode (i) intp14 (interrupt request from peripherals) ? input this pin inputs an external interrupt request signal. (ii) rxda3 (receive data) note ? input this pin inputs the serial receive data of uarta3. (iii) txda3 (transmit data) note ? output this pin outputs the serial transmit data of uarta3. note in the pd70f3237, the alternate func tions of the p80 and p81 pins (rxda3 and txda3) are not available. the alternate f unction of the p80 pin in the pd70f3237 is intp14 only. (9) p90 to p915 (port 9) ? 3-state i/o p90 to p915 function as a 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as serial interface i/o, ti mer/counter i/o, clock output, external interrupt request signal input, and key interrupt input. this port can be set in the port mode or control mode in 1-bit units. the valid edge of p913 to p915 is specified by using intf9h register. an on-chip pull-up resistor can be connected to p90 to p915 by using pull-up resistor option register 9 (pu9). (a) port mode p90 to p915 can be set in the input or output mode in 1-bit units, by using port 9 mode register (pm9). (b) control mode (i) sib1, sib2 (serial input) ? input these pins input the serial receive data of csib1 and csib2. (ii) sob1, sob2 (serial output) ? output these pins output the serial re ceive data of csib1 and csib2. chapter 2 pin functions user?s manual u17830ee1v0um00 89 (iii) sckb1, sckb2 (serial clock) ? 3-state i/o these pins input/output the seri al clock of csib1 and csib2. (iv) rxda1 (receive data) ? input this pin inputs the serial receive data of uarta1. (v) txda1 (transmit data) ? output this pin outputs the serial transmit data of uarta1. (vi) tip20, tip21 (timer input) ? input these pins input timers p2 (tmp2). (vii) top20, top21 (timer output) ? output these pins output from timers p2 (tmp2). (viii) tiq10, tiq11, tiq12, tiq13 (timer input) ? input these pins input an external count clock to timers q1. (ix) toq10, toq11, toq12, toq13 (timer output) ? output these pins output a pulse signal from timers q1. (x) pcl (clock output) ? output this pin outputs a clock. (xi) intp4 to intp6 (interrupt request from peripherals) ? input these pins input an external interrupt request signal. (xii) kr6, kr7 (key return) ? input these pins input a key interrupt. their operation is specified by the key return mode register (krm) in the input port mode. (10) p120 to p127 (port 12) ? 3-state i/o p120 to p127 function as an 8-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as the analog input pins of the a/d converter in the control mode. when using this port as analog input pins, ho wever, set the port in the input mode. at this time, do not read the port. (a) port mode p120 to p127 can be set in the input or output mode in 1-bit units, by using port mode register 12 (pm12). (b) control mode p120 to p127 function alternately as the ani16 to ani23 pins. (i) ani16 to ani23 (analog input 16 to 23) ? input these pins input an analog signal to the a/d converter. chapter 2 pin functions user?s manual u17830ee1v0um00 90 (11) pcd0 to pcd3 (port cd) ? 3-state i/o pcd0 to pcd3 function as a 4-bit i/o port that can be set to input or output in 1-bit units. (a) port mode pcd0 to pcd3 can be set in the input or output mo de in 1-bit units, by using port mode register cd (pmcd). (12) pcm0 to pcm5 (port cm) ? 3-state i/o pcm0 to pcm5 function as a 6-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as bus hold control signal i/o, bus clock output, and a control signal that in serts a wait cycle in the bus cycle (wait), in the control mode. (a) port mode pcm0 to pcm5 can be set in the input or output mo de in 1-bit units, by using port mode register cm (pmcm). (b) control mode (i) hldak (hold acknowledge) ? output this pin outputs an acknowledge signal that indica tes that the v850es/fj2 has placed the address bus, data bus, and control bus in a high-impedance state in response to a bus hold request. while this signal is active, the address bus, data bus , and control bus go into a high-impedance state. (ii) hldrq (hold request) ? input an external device uses this input pin to request the v850es/fj2 to release the address bus, data bus, and control bus. a signal can be input to this pin asynchronously to clkout. when this pin is asserted, the v850es/fj2 places the address bus, data bus, and control bus in a high-impedance state after completion of a bus cycle under execution, if any, or immediately if no such bus cycle is under execution. the v850e s/fj2 then asserts the hldak signal and releases the buses. (iii) clkout (clock output) ? output this pin outputs an internally generated bus clock. (iv) wait (wait) ? input this is a control signal input pin that inserts a data wait state in the bus cycle. a signal can be input to this pin asynchronously to the clkout signal. the signal input to this pin is sampled at the falling edge of the clkout signal in the t2 and tw states of the bus cycle in the multiplexed mode. no wait state may be inserted if the se tup/hold time of the sampling timing is not satisfied. the wait function is set to on or off by port mode control register cm (pmccm). (13) pcs0 to pcs7 (port cs) ? 3-state i/o pcs0 to pcs7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as chip select signal out put in the control mode. chapter 2 pin functions user?s manual u17830ee1v0um00 91 (a) port mode pcs0 to pcs7 can be set in the input or output mode in 1-bit units, by using port mode register cs (pmcs). (b) control mode (i) cs0 to cs3 (chip select input) ? output these pins output a chip select signal to external memory and external peripheral i/o. the csn signal is assigned to memory block n (n = 0 to 3). this signal is asserted while a bus cycle for accessing the corresponding memory block is being executed. this signal is deasserted in the idle state (ti). (14) pct0 to pct7 (port ct) ? 3-state i/o pct0 to pct7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as control signal output in the control mode when memory is externally expanded. (a) port mode pct0 to pct7 can be set in the input or output mo de in 1-bit units, by using port mode register ct (pmct). (b) control mode (i) wr0 (lower byte write strobe) ? output this pin outputs the write strobe signal of th e lower data of the external 16-bit data bus. (ii) wr1 (upper byte write strobe) ? output this pin outputs the write strobe signal of th e higher data of the external 16-bit data bus. (iii) rd (read strobe) ? output this pin outputs the read strobe signal of the external 16-bit data bus. (iv) astb (address strobe) ? output this pin outputs the latch strobe signal of the extern al address bus. the signal output from this pin goes low at the falling edge of the t1 state of the bus cycle, and goes high at the falling edge of the t3 state. it goes high while the bus cycle is not active. (15) pdl0 to pdl15 (port dl) ? 3-state i/o pdl0 to pdl15 function as a 16-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, these pins operate as a time-division address/data bus (ad0 to ad15) when the memory is externally expanded. pdl5/ad5 also functions as the flmd1 pin when the flas h memory is programmed (when a high level is input to fld0). at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl15 can be set in the input or output mo de in 1-bit units, by using port mode register dl (pmdl). chapter 2 pin functions user?s manual u17830ee1v0um00 92 (b) control mode (i) ad0 to ad15 (address/data bus 0 to 15) ? 3-state i/o this is a multiplexed address/data bus for external access. (16) reset (reset) ? input reset input is asynchronous input. when a signal wi th a fixed low level width is input to the reset pin regardless of the operating clock, the system is reset, taking precedenc e over all the other operations. this pin is used to release the standby mode (halt, idle , or stop), as well as for normal initialization/start. (17) x1, x2 (crystal for main clock) these pins are used to connect the res onator that generates the system clock. (18) xt1, xt2 (crystal for subclock) these pins are used to connect the re sonator that generates the subclock. (19) av ss (ground for analog) this is a ground pin for the a/d conv erter, and alternate-function ports. (20) av ref0 (analog reference voltage) ? input this pin supplies positive analog power to th e a/d converter and alternate-function ports. it also supplies a reference voltage to the a/d converter. (21) ev dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. (22) ev ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (23) v dd (power supply) this pin supplies positive power. connect all the v dd pins to a positive power supply. (24) v ss (ground) this is a ground pin. connect all the v ss pins to ground. (25) flmd0 (flash programming mode) input this is a signal input pin for flash memory programming mode. connect this pin to vss in the normal operation mode. (26) bv dd (power supply for port) this pin supplies positive power to t he i/o ports and alternate-function pins. chapter 2 pin functions user?s manual u17830ee1v0um00 93 (27) bv ss (ground for port) this is a ground pin for the i/o ports and alternate-function pins. (28) regc (regulator control) ? input this pin connects a capacitor for the regulator. chapter 2 pin functions user?s manual u17830ee1v0um00 94 2.4 pin i/o circuit types and recommended connection of unused pins 2.4.1 v850es/fe2 (1/2) pin i/o circuit type recommended connection p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p05/intp2/drst 5-af input: independently connect to ev ss output: leave open p06/intp3 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p30/txda0 5-a p31/rxda0/intp7 p32/ascka0/tip00/top00/ top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p40/sib0 5-w p41/sob0 5-a p42/sckb0 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open chapter 2 pin functions user?s manual u17830ee1v0um00 95 (2/2) pin i/o circuit type recommended connection p70/ani0 to p79/ani9 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open p90/kr6/txda1 p91/kr7/rxda1 p96/tip21/top21 p97/sib1/tip20/top20 5-w p98/sob1 5-a p99/sckb1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p913/intp4/pcl p914/intp5 p915/intp6 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open pcm0 pcm1/clkout 5 input: independently connect to ev dd or ev ss via a resistor output: leave open pdl0 to pdl4 pdl5/flmd1 pdl6, pdl7 5 input: independently connect to ev dd or ev ss via a resistor output: leave open av ref0 ? directly connect to v dd av ss ? ? flmd0 note ? directly connect to v ss regc ? ? reset 2 ? x1 ? ? x2 ? ? xt1 16 connect to v ss via a resistor xt2 16 leave open v dd ? ? v ss ? ? ev dd ? ? ev ss ? ? note if noise that exceeds the noise elimination width is input to the reset pin during self programming, the flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is connected to the flmd0 pin. therefore, do not connect a capacitor to the flmd0 pin. chapter 2 pin functions user?s manual u17830ee1v0um00 96 2.4.2 v850es/ff2 (1/2) pin i/o circuit type recommended connection p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p05/intp2/drst 5-af input: independently connect to ev ss output: leave open p06/intp3 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p30/txda0 5-a p31/rxda0/intp7 p32/ascka0/tip00/top00/ top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 5-w p38 5-a p39 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p40/sib0 5-w p41/sob0 5-a p42/sckb0 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open chapter 2 pin functions user?s manual u17830ee1v0um00 97 (2/2) pin i/o circuit type recommended connection p70/ani0 to p711/ani11 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open p90/kr6/txda1 p91/kr7/rxda1 p96/tip21/top21 p97/sib1/tip20/top20 5-w p98/sob1 5-a p99/sckb1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p913/intp4/pcl p914/intp5 p915/intp6 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open pcm0 pcm1/clkout pcm2, pcm3 5 input: independently connect to ev dd or ev ss via a resistor output: leave open pcs0, pcs1 5 input: independently connect to ev dd or ev ss via a resistor output: leave open pct0. pct1, pct4, pct6 5 input: independently connect to ev dd or ev ss via a resistor output: leave open pdl0 to pdl4 pdl5/flmd1 pdl6 to pdl11 5 input: independently connect to ev dd or ev ss via a resistor output: leave open av ref0 ? directly connect to v dd av ss ? ? flmd0 note ? directly connect to v ss regc ? ? reset 2 ? x1 ? ? x2 ? ? xt1 16 connect to v ss via a resistor xt2 16 leave open v dd ? ? v ss ? ? ev dd ? ? ev ss ? ? note if noise that exceeds the noise elimination width is input to the reset pin during self programming, the flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is connected to the flmd0 pin. therefore, do not connect a capacitor to the flmd0 pin. chapter 2 pin functions user?s manual u17830ee1v0um00 98 2.4.3 v850es/fg2 (1/2) pin i/o circuit type recommended connection p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p05/intp2/drst 5-af input: independently connect to ev ss via a resistor output: leave open p06/intp3 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p10/intp9 p11/intp10 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p30/txda0 5-a p31/rxda0/intp7 p32/ascka0/tip00/top00/top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 5-w p36/ctxd1 5-a p37/crxd1 5-w p38/txda2 5-a p39/rxda2/intp8 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p40/sib0 5-w p41/sob0 5-a p42/sckb0 input: independently connect to ev dd or ev ss via a resistor output: leave open p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p70/ani0 to p711/ani11 p712/ani12 to p715/ani15 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open p90/kr6/txda1 p91/kr7/rxda1 p92/tiq11/toq11 p93/tiq12/toq12 p94/tiq13/toq13 p95/tiq10/toq10 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open chapter 2 pin functions user?s manual u17830ee1v0um00 99 (2/2) pin i/o circuit type recommended connection p96/tip21/top21 p97/sib1/tip20/top20 5-w p98/sob1 5-a p99/sckb1 5-w p910 p911 p912 5-a p913/intp4/pcl p914/intp5 p915/intp6 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open pcm0 pcm1/clkout pcm2, pcm3 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pcs0, pcs1 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pct0, pct1, pct4, pct6 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pdl0 to pdl4 pdl5/ flmd1 pdl6 to ad13 5 input: independently connect to bv dd or bv ss via a resistor output: leave open av ref0 ? directly connect to v dd av ss ? ? flmd0 note ? directly connect to v ss regc ? ? reset 2 ? x1 ? ? x2 ? ? xt1 16 connect to v ss via a resistor xt2 16 leave open v dd ? ? v ss ? ? bv dd ? ? bv ss ? ? ev dd ? ? ev ss ? ? note if noise that exceeds the noise elimination width is input to the reset pin during self programming, the flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is connected to the flmd0 pin. therefore, do not connect a capacitor to the flmd0 pin. chapter 2 pin functions user?s manual u17830ee1v0um00 100 2.4.4 v850es/fj2 (1/4) pin i/o circuit type recommended connection p00/tip31/top31 p01/tip30/top30 p02/nmi p03/intp0/adtrg p04/intp1 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p05/intp2/drst 5-af input: independently connect to ev ss output: leave open p06/intp3 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p10/intp9 p11/intp10 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p30/txda0 5-a p31/rxda0/intp7 p32/ascka0/tip00/top00/ top01 p33/tip01/top01/ctxd0 p34/tip10/top10/crxd0 p35/tip11/top11 5-w p36/ctxd1 5-a p37/crxd1 5-w p38/txda2 note 5-a p39/rxda2/intp8 note 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p40/sib0 5-w p41/sob0 5-a p42/sckb0 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p50/kr0/tiq01/toq01 p51/kr1/tiq02/toq02 p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open chapter 2 pin functions user?s manual u17830ee1v0um00 101 (2/4) pin i/o circuit type recommended connection p60/intp11 p61/intp12 p62/intp13 5-w p63 p64 p65/ctxd2 note1 5-a p66/crxd2 note1 5-w p67/ctxd3 note1 5-a p68/crxd3 note1 5-w p69 5-a p610/tiq20/toq20 p611/tiq21/toq21 p612/tiq22/toq22 p613/tiq23/toq23 5-w p614 p615 5-a input: independently connect to ev dd or ev ss via a resistor output: leave open p70/ani0 to p79/ani9 p710/ani10, p11/ani11 p712/ani12 to p715/ani15 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open p80/rxda3/intp14 note2 5-w p81/txda3 note2 5-a input: independently connect to ev dd or ev ss via a resistor output: leave open p90/kr6/txda1 p91/kr7/rxda1 p92/tiq11/toq11 p93/tiq12/toq12 p94/tiq13/toq13 p95/tiq10/toq10 p96/tip21/top21 p97/sib1/tip20/top20 5-w p98/sob1 5-a p99/sckb1 p910/sib2 5-w p911/sob2 5-a p912/sckb2 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open notes 1. in the pd70f3237, the alternate func tions of the p65 to p68 pins (ctxd2, crxd2, ctxd3, and crxd3) are not available. 2. in the pd70f3237, the alternate functi ons of the p80 and p81 pins (rxda3 and txda3) are not available. the alternate function of the p80 pin in the pd70f3237 is only intp14. chapter 2 pin functions user?s manual u17830ee1v0um00 102 (3/4) pin i/o circuit type recommended connection p913/intp4/pcl p914/intp5 p915/intp6 5-w input: independently connect to ev dd or ev ss via a resistor output: leave open p120/ani16 to p127/ani23 11-g input: independently connect to av ref0 or av ss via a resistor output: leave open pcd0 to pcd3 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pcm0/wait pcm1/clkout pcm2/hldak pcm3/hldrq pcm4 pcm5 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pcs0/cs0, pcs3/cs1 pcs0/cs2, pcs3/cs3, pcs4 to pcs7 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pct0/wr0 pct1/wr1 pct2 pct3 pct4/rd pct5 pct6/astb pct7 5 input: independently connect to bv dd or bv ss via a resistor output: leave open pdl0/ad0 to pdl4/ad4 pdl5/ad5/flmd1 pdl6/ad6, pdl7/ad7 pdl8/ad8 to pdl11/ad11 pdl12/ad12, pdl13/ad13 pdl14/ad14, pdl15/ad15 5 input: independently connect to bv dd or bv ss via a resistor output: leave open chapter 2 pin functions user?s manual u17830ee1v0um00 103 (4/4) pin i/o circuit type recommended connection av ref0 ? directly connect to v dd av ss ? ? flmd0 note ? directly connect to v ss regc ? ? reset 2 ? x1 ? ? x2 ? ? xt1 16 connect to v ss via a resistor xt2 16 leave open v dd ? ? v ss ? ? bv dd ? ? bv ss ? ? ev dd ? ? ev ss ? ? note if noise that exceeds the noise elimination width is input to the reset pin during self programming, the flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is connected to the flmd0 pin. therefore, do not connect a capacitor to the flmd0 pin. chapter 2 pin functions user?s manual u17830ee1v0um00 104 2.5 pin i/o circuits figure 2-1. pin i/o circuit types (1/2) in data output disable p-ch in/out v dd n-ch input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch v ref (threshold voltage) comparator schmitt-triggered input with hysteresis characteristics input enable + _ av ss av ss pullup enable pulldown enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch n -ch type 2 type 5-af type 5 type 11-g chapter 2 pin functions user?s manual u17830ee1v0um00 105 figure 2-1. pin i/o circuit types (2/2) data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch p-ch feedback cut-off xt1 xt2 type 5-a type 5-w type 16 user?s manual u17830ee1v0um00 106 chapter 3 cpu functions based on the risc architecture, the cpu of the v 850es/fe2, v850es/ff2, v850es/ fg2, v850es/fj2 executes most of the instructions in one clock under control of a five-stage pipeline. 3.1 features { minimum instruction execution time: 50 ns (at 20 mhz operation) { memory space program space: 64 mb, linear data space: 4 gb, linear { general-purpose registers: 32 bits 32 { internal 32-bit architecture { five-stage pipeline control { multiplication/division instructions { saturation operation instructions { 32-bit shift instructions: 1 clock { load/store instructions with long/short format { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu functions user?s manual u17830ee1v0um00 107 3.2 cpu register set the registers of the v850e s/fe2, v850es/ff2, v850es/fg2, v850es/ fj2 can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to v850es architecture user?s manual . r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 pc psw ecr fepc fepsw eipc eipsw 31 0 31 0 31 0 ctbp dbpc dbpsw ctpc ctpsw (status saving register on interrupt) (status saving register on interrupt) (status saving register on nmi) (status saving register on nmi) (interrupt source register) (program status word) (status saving register on callt execution) (status saving register on callt execution) (status saving register on exception/debug trap) (status saving register on exception/debug trap) (callt base pointer) (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) (program counter) (1) program register set (2) system register set chapter 3 cpu functions user?s manual u17830ee1v0um00 108 3.2.1 program register set the program registers include general-pur pose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used for a data variable or address variable. however, r0 and r30 are implicitly us ed by instructions, and care must be ex ercised when using these registers. register r0 always holds 0, and is used for an operation us ing 0 or addressing with offset 0. register r30 is used as a base pointer when the sld or sst instruction is used to access t he memory. registers r1, r3 to r5, and r31 are implicitly used by the assembler and c comp iler. when using these regi sters, therefore, their contents must be saved so that they are not lost, and later restored to the registers. register r2 may be used by a real-time os. if the real-time os used does no t use r2, r2 can be used as a register for variables. table 3-1. program register list name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as a wo rking register for creating 32-bit immediate r2 register for address/data variable (if the real-time os used does not use r2) r3 stack pointer used to generate a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as a register that points to the beginning of a text area (area where program codes are located) r6 to r29 registers for address/data variable r30 element pointer used as a base pointer when memory is accessed r31 link pointer used when t he compiler calls a function pc program counter holds an instruction address during program execution remark for further details on the r1, r3 to r5, and r31that are used in the assembler and c compiler, refer to the ca850 (c compiler package) assembly language of the user?s manual. (2) program counter (pc) the program counter holds an instruct ion address during program execution. the lower 26 bits of this counter are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to bit 26 is ignored. bit 0 is always fixed to 0, and execution cannot branch to an odd address. 31 26 25 1 0 pc 0 default value 00000000h instruction address during program execution fixed to 0 chapter 3 cpu functions user?s manual u17830ee1v0um00 109 3.2.2 system register set the system registers are used to control the status of the cpu or to hold interrupt information. data can be read from or written to system registers by setting one of the system r egister numbers listed below using a system register load or st ore (ldsr or stsr) instruction. table 3-2. system register numbers operand specification register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) 3 nmi status saving register (fepsw) 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion. (operation is not guaranteed if these registers are accessed.) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 19 exception/debug trap status saving register (dbpsw) note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion. (operation is not guaranteed if these registers are accessed.) notes 1. because only one pair of these registers is provided, the contents of these registers must be saved by program when multiple interrupt servicing is enabled. 2. these registers can be accessed only between dbtr ap or the illegal instruction execution and dbret instruction execution. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution returns from interrupt ser vicing to the main routine by the reti instruction (this is because bit 0 of the pc is fixed to 0). when setting a value to eipc, fepc, or ctpc, set an even value (bit = 0). remark : accessible : access prohibited chapter 3 cpu functions user?s manual u17830ee1v0um00 110 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are interrupt status saving registers. if a software exception or a maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program status word (psw) are saved to eipsw. (the content s of the pc and psw are saved to fepc and fepsw (nmi status saving registers) if a n on-maskable interrupt (nmi) occurs.) the address of the instruction next to the one under execution, except some instructions (see 17.7 periods in which interrupts are not acknowledged by cpu), is sa ved to eipc when a software exception or a maskable interrupt occurs. the current contents of t he psw are saved to eipsw. because only one pair of interrupt stat us saving registers is available, th e contents of these registers must be saved by program if multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved for future function expansion (these bits are fixed to 0). the values of eipc restore the pc, and the values of eipsw do to the psw by the reti instruction. 31 0 eipc 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (contents of psw) (contents of pc) chapter 3 cpu functions user?s manual u17830ee1v0um00 111 (2) nmi status saving re gisters (fepc and fepsw) fepc and fepsw are nmi st atus saving registers. if a non-maskable interrupt (nmi) occurs, the contents of the program counter (pc) are saved to fepc, and the contents of the progr am status word (psw) are saved to fepsw. the address of the instruction next to the one under execution, except some instructions, is saved to fepc. the current contents of t he psw are saved to fepsw. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are reserved for future function expansion (these bits are fixed to 0). 31 0 fepc 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (contents of psw) (contents of pc) (3) interrupt source register (ecr) the interrupt source register ecr hol ds the source of an exception or an interrupt that has occurred. the value ecr is to hold is an exception code for each interru pt source. this register is a read-only register. no data can be written to this register by using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 3 cpu functions user?s manual u17830ee1v0um00 112 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate t he status of the program (result of instruction execution) or the cpu. if the contents of any bit of this r egister are changed by using the ldsr instruction, the new contents become valid immediately after execution of the ldsr inst ruction. when the id flag is set to 1, however, acknowledgment of an interrupt request is disabled from when the ldsr instruction is still under execution. bits 31 to 8 are reserved for future function expansion (these bits are fixed to 0). 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. always fixed to 0 7 np indicates that a non-maskable interrupt (nmi) is bei ng serviced. this flag is set to 1, disabling multiple interrupt servicing, when an nmi request is acknowledged. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that exception processing is in progre ss. this flag is set to 1 when an exception is generated. interrupt requests are ac knowledged even if this bit is set. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt request can be acknowledged. 0: interrupts enabled 1: interrupts disabled 4 sat note indicates that the result of an operation of a saturation operation instruction overflows and that the operation result is saturated. because this is a cumulative flag, it is set to 1 if the operation result of a saturation operation instruction is saturated, and is not cleared to 0 even if the operation result of the subsequent instructions is not saturated. this flag is cleared to 0 by the ldsr instruction. when an arithmetic operation in struction is executed, this flag is neither set to 1 nor cleared to 0. 0: not saturated 1: saturated 3 cy indicates whether a carry or a borrow occurred as a result of an operation. 0: carry or borrow did not occur. 1: carry or borrow occurred. 2 ov note indicates whether an overflow occurred during an operation. 0: overflow did not occur. 1: overflow occurred. 1 s note indicates whether the result of an operation is negative or not. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether the result of an operation is 0 or not. 0: result of operation is not 0. 1: result of operation is 0. remark refer to the next page for the explanation of note . chapter 3 cpu functions user?s manual u17830ee1v0um00 113 (2/2) note the result of an operation of saturation processing is determined by the contents of the ov and s flags when a saturation operation is performed. the sat flag is set to 1 only when the ov flag is set to 1 as a result of a saturation operation. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded. 1 1 0 7fffffffh maximum negative value is exceeded. 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation. 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and the contents of the progr am status word (psw) are saved to ctpsw. the contents saved to ctpc are t he address of the instruction ne xt to the callt instruction. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (these bits are fixed to 0). 31 0 ctpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (contents of psw) chapter 3 cpu functions user?s manual u17830ee1v0um00 114 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status saving registers. if an exception trap or a debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and the contents of the progr am status word (psw) are saved to dbpsw. the contents saved to dbpc are t he address of the instruction next to the one under execution when an exception trap or a debug trap has occurred. the current contents of t he psw are saved to dbpsw. these registers can be accessed only between dbtrap or the illegal instruction execution and dbret instruction execution. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (these bits are fixed to 0). the values of dbpc restore pc, and the values of dbpsw do to psw by dbret instruction. 31 0 dbpc 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (contents of pc) (contents of psw) (7) callt base pointer (ctbp) the callt base pointer (ctbp) is us ed to specify a table address or to generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for futu re function expansion (these bits are fixed to 0). 31 0 ctbp 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 (base address) chapter 3 cpu functions user?s manual u17830ee1v0um00 115 3.3 operation modes the v850es/fx2 have the fo llowing operation modes. flmd0 flmd1 operation mode 0 x normal operation mode 1 0 flash memory programming mode 1 1 setting prohibited remark x: don't care (1) normal operation mode after system reset is released, each pin related to the bus interface is set in the port mode, execution branches to the reset entry address of the internal rom, and instruction processing is started. when the pmcdl, pmccm, pmccs, and pmcct registers are set in the cont rol mode by software, an external device can be connected to the external memory area. (2) flash memory programming mode when this mode is specified, the internal flash me mory can be programmed by using a flash programmer. (3) on-chip debug mode the v850es/fj2 is provided with an on- chip debug function that employ t he jtag (joint test action group) communication specifications and that is executed via an n-wire emulat or. for details, see chapter 27 on- chip debug function." 3.3.1 specifying operation mode specify the operation mode by usi ng the flmd0 and flmd1 pins. in the normal mode, make sure that the flmd0/ic pin goes low when reset is released. in the flash memory programming mode, a high level is input to the flmd0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. chapter 3 cpu functions user?s manual u17830ee1v0um00 116 3.4 address space 3.4.1 cpu address space the cpu of the v850es/fx2 has 32-bit ar chitecture, and supports a linear address space (data space) of up to 4 gb for operand addressing (data access). it also supports a linear address space (program space) of up to 64 mb for addressing instruction addresses. however, both the pr ogram and data spaces have ar eas prohibited from being used. for details, refer to figure 3-2 . figure 3-1 illustrates the cpu address space. figure 3-1. cpu address space data area (4 gb, linear) program area (64 mb, linear) cpu address space ffffffffh 04000000h 03ffffffh 00000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 117 3.4.2 image up to 16 mb of external memory area, internal rom ar ea, and internal ram area of up to 16 mb of linear address space (program space) are supported fo r addressing of instruction addresses. up to 4 gb of linear address space (data space) are supported for operand addressing (data a ccess). note, however, that there seems to be sixty-four 64 mb physical address spaces on the 4 gb address space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-2. image on address space peripheral i/o area data space internal rom area (external memory area) external memory area use-prohibited area internal ram area internal rom area (external memory area) external memory area use-prohibited area internal ram area use-prohibited area program space 4 gb 64 mb . . . 16 mb image 63 image 1 image 0 64 mb chapter 3 cpu functions user?s manual u17830ee1v0um00 118 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and the lowest address, 00000000h, are contiguous addresses. that the highest address and th e lowest address of the program space are contiguous in this way is called wraparound. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fe tched from this area. therefo re, do not execute an operation in which the result of a branch a ddress calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and t he lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh chapter 3 cpu functions user?s manual u17830ee1v0um00 119 3.4.4 memory map the v850es/fx2 reserves the areas shown in figure 3-3 . figure 3-3. data memory map (physical addresses) 3ffffffh 3fec000h 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 3febfffh 3ffffffh 3fff000h 3ffefffh 3ff0000h 3feffffh 3fef000h 3feefffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h (80 kb) programmable peripheral i/o area use prohibited note 2 internal ram area (60 kb) note 1 internal rom area note 3 (1 mb) on-chip peripheral i/o area (4 kb) external memory area (8 mb) external memory area (4 mb) external memory area (2 mb) external memory area (1 mb) (2 mb) use prohibited notes 1. v850es/fe2: pd703230: 4k, p d70f3231: 6k are provided. v850es/ff2: pd703232: 6k , pd70f32 32: 12k , pd703232: 12k are provided v850es/fg2: pd70f3234: 6k , pd70f3 235: 12k , pd70f3236: 16k are provided v850es/fj2: pd70f3237: 12kb, pd70f3 238: 20kb, pd703239: 20kb are provided. 2. use of addresses 3fef000h to 3feffffh is prohibi ted because these addresses are in the same area as the on-chip peripheral i/o area. 3. a fetch access and a read access to addresses 000 0000h to 00fffffh is made to the internal rom area, but these addresses are used as an exte rnal memory area when a data write access is made. chapter 3 cpu functions user?s manual u17830ee1v0um00 120 figure 3-4. program memory map internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (14 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h remark instructions can be executed in the external me mory area without a branch from the internal rom area to the external memory area. for deta ils, refer to 3.4.5 (2) internal ram area chapter 3 cpu functions user?s manual u17830ee1v0um00 121 3.4.5 areas (1) internal flash memory area up to 1 mb is reserved as an internal flash memory area. (a) internal mask rom memory area (64 kb) 64 kb, addresses 0000000h to 000ffffh, are provided in the following products as an internal flash memory area. accessing addresses 0001000h to 00fffffh is prohibited. ? v850es/fe2: pd703230 figure 3-5. internal fl ash memory area (64 kb) access-prohibited area internal flash memory 00fffffh 0010000h 0000ffffh 0000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 122 (b) internal flash me mory area (128 kb) 128 kb, addresses 0000000h to 001ffffh, are provided in the following products as an internal flash memory area. accessing addresses 0020000h to 00fffffh is prohibited. ? v850es/fe2: pd70f3231 ? v850es/ff2: pd70f3232 ? v850es/fg2: pd70f3234 figure 3-6. internal fl ash memory area (128 kb) access-prohibited area internal flash memory 00fffffh 0020000h 001ffffh 0000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 123 (c) internal flash me mory area (256 kb) 256 kb, addresses 0000000h to 003ffffh, are provided in the following products as an internal flash memory area. accessing addresses 0040000h to 00fffffh is prohibited. ? v850es/ff2: pd70f3233 ? v850es/fg2: pd70f3235 ? v850es/fj2: pd70f3237 figure 3-7. internal fl ash memory area (256 kb) access-prohibited area internal flash memory 00fffffh 0040000h 003ffffh 0000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 124 (d) internal flash memory area (376 kb) the following products have a 376 kb area of 00000000h to 0005dfffh. use of addresses 005e000h to 00fffffh is prohibited. ? v850es/fj2: pd70f3238 figure 3-8. internal fl ash memory area (376 kb) access-prohibited area internal flash memory 00fffffh 005e000h 005dfffh 0000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 125 (e) internal flash memory area (384 kb) the following products have a 384 kb area of 00000000h to 0005ffffh. use of addresses 0060000h to 00fffffh is prohibited. ? v850es/fg2: pd70f3236 figure 3-9. internal fl ash memory area (384 kb) access-prohibited area internal flash memory 00fffffh 0060000h 0005ffffh 0000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 126 (f) internal flash memory area (512 kb) 512 kb, addresses 0000000h to 007ffffh, are provided in the followi ng product as an internal flash memory area. accessing addresses 0080000h to 00fffffh is prohibited. ? v850es/fj2: pd70f3239 figure 3-10. internal fl ash memory area (512 kb) access-prohibited area internal flash memory 00fffffh 0080000h 007ffffh 0000000h chapter 3 cpu functions user?s manual u17830ee1v0um00 127 (2) internal ram area up to 60 kb are reserved as an internal ram area. (a) internal ram (4 kb) the following product has a 4 kb area from addresses 3ffe000h to 3ffefffh. use of addresses 3ff0000h to 3ffdfffh is prohibited. ? v850es/fe2: pd703230 figure 3-11. internal ram area (4 kb) a cc e ss - p r oh i b i t ed a r ea i n t e r na l r a m 3 ffefff h 3 ffe 000 h 3 ff d fff h 3 ff 0000 h chapter 3 cpu functions user?s manual u17830ee1v0um00 128 (b) internal ram (6 kb) the following products have a 6 kb area from addr esses 3ffd800h to 3ffefffh. use of addresses 3ff0000h to 3ffd7ffh is prohibited. ? v850es/fe2: pd70f3231 ? v850es/ff2: pd703232 ? v850es/fg2: pd70f3234 figure 3-12. internal ram area (6 kb) access-prohibited area internal ram 3ffefffh 3ffd800h 3ffd7ffh 3ff0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 129 (c) internal ram (12 kb) the following products have a 12 kb area from addresses 3ffc000h to 3ffefffh. use of addresses 3ff0000h to 3ffbfffh is prohibited. ? v850es/ff2: pd70f3232, pd70f3233 ? v850es/fg2: pd70f3235 ? v850es/fj2: pd70f3237 figure 3-13. internal ram area (12 kb) access-prohibited area internal ram 3ffefffh 3ffc000h 3ffbfffh 3ff0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 130 (d) internal ram (16 kb) the following prod uct has a 16 kb area from addresses 3ffb000h to 3ffefffh. use of addresses 3ff0000h to 3ffafffh is prohibited. ? v850es/fg2: pd70f3236 figure 3-14. internal ram area (16 kb) access-prohibited area internal ram 3ffefffh 3ffb000h 3ffafffh 3ff0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 131 (e) internal ram (20 kb) the following products have a 20 kb area from addresses 3ffa000h to 3ffefffh. use of addresses 3ff0000h to 3ff9fffh is prohibited. ? v850es/fj2: pd70f3238, pd70f3239 figure 3-15. internal ram area (20 kb) access-prohibited area internal ram 3ffefffh 3ffa000h 3ff9fffh 3ff0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 132 (3) on-chip peripheral i/o area 4 kb, addresses 3fff000h to 3ffffffh, are re served as an on-chip peripheral i/o area. figure 3-16. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 3ffffffh 3fff000h peripheral i/o registers that are used to specify the operation mode of and to monitor the status of the on-chip peripheral i/o are mapped to the on-ch ip peripheral i/o area. program cannot be fetched from this area. cautions 1. if a register is access ed in word units, a word area wit h the lower 2 bits of an address ignored is accessed in halfword units in the order of the lower halfword and the higher halfword. 2. if a register that can be accessed in bytes is accessed in ha lfwords, the higher 8 bits are undefined when the register is read. data is written to the lower 8 bits when a write access is made to the register. 3. addresses not defined as those of registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. chapter 3 cpu functions user?s manual u17830ee1v0um00 133 (4) programmable peripheral i/o area 12 kb of addresses 03fec000h to 03feefffh are rese rved as the programmable peripheral i/o area. figure 3-17. programmable peripheral i/o area programmable peripheral i/o area (12 kb) 03feefffh 03fec000h caution the programmable peri pheral i/o area is seen as images of 256 mb each in the 4 gb address space. (5) external memory area an external memory area of 15 mb (0100000h to 0ffffffh) is available. for details, refer to chapter 5 bus control function . chapter 3 cpu functions user?s manual u17830ee1v0um00 134 3.4.6 recommended use of address space with the architecture of the v850es/ fx2, a register that serves as a pointer must be secured for address generation when operand data in the data space is to be accessed. the 32 kb of this pointer register can be directly accessed from an instruction for operand data. however, the number of general-purpose registers that can be used as a pointer is limited. the number of general-purpose registers that can be allocated for variables can be maximized and the program size can be reduced by suppressing a dr op in performance due to address calculation when a pointer value is to be changed. (1) program space of the 32 bits of the pc (program counter), only the lower 26 bits are valid and the higher 6 bits are fixed to 0. therefore, a contiguous 64 mb s pace, starting from address 00000000h, is mapped as a program space. when using the internal ram area as a progr am space, access the following addresses. caution the prefetch operation (inva lid fetch) across internal periphe ral i/o area is not generated if there is a branch instruction in the uppe r-limit addresses of the internal ram area. ram size addresses to be accessed 20 kb 3ffa000h to 3ffefffh 16 kb 3ffb000h to 3ffefffh 12 kb 3ffc000h to3ffefffh 6 kb 3ffd800h to3ffefffh 4 kb 3ffe000h to3ffefffh chapter 3 cpu functions user?s manual u17830ee1v0um00 135 (2) data space on the 4 gb cpu address space of the v850es/fx2, there seems to be sixty-four 64 mb physical address spaces. therefore, 26-bit addresses wit h the most significant bit (bit 25) sign-extended up to 32 bits in length are allocated. (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, the range of address 00000000h 32 kb can be addressed by sign-extended disp16. all the resources of the internal hardware can be addressed by using one pointer. the zero register (r0) is fixed to 0 by hardware and a register used for a pointer is basically unnecessary. example : pd70f3239 use prohibited internal rom area internal ram area on-chip peripheral i/o area 32 kb (r = ) 4 kb 20 kb 8 kb 00080000h 00007fffh 00000000h fffff000h ffffefffh ffffa000h ffff9fffh ffff8000h chapter 3 cpu functions user?s manual u17830ee1v0um00 136 figure 3-18. recommended memory map program space, 64 mb ffffffffh fffff000h ffffefffh ffffc000h ffffbfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh 03fec000h 03febfffh 01000000h 00ffffffh 00020000h 0001ffffh 00000000h xfffffffh xffff000h xfffefffh xfff7000h xfff6fffh xffec000h xffebfffh x0100000h x00fffffh x0000000h external memory external memory use prohibited use prohibited internal ram internal ram on-chip peripheral i/o internal ram internal rom internal rom internal rom on-chip peripheral i/o on-chip peripheral i/o note data space program space note accessing this area is prohibited. to access on-ch ip peripheral i/o in this area, specify addresses ffff000h to fffffffh. remarks 1. the upper and lower arrows indicate the area recommended to be used. 2. this figure is the recommended memory map of the upd70f3238 and upd79f0239. chapter 3 cpu functions user?s manual u17830ee1v0um00 137 3.4.7 peripheral i/o registers 3.4.7.1 v850es/fe2 (1/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl pdl undefined fffff004h port dll pdll undefined fffff005h port dlh pdlh undefined fffff00ch port cm pcm undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll ffh fffff025h port mode register dlh pmdlh ffh fffff02ch port mode register cm pmcm ffh fffff04ch port mode control register cm pmccm 00h fffff064h peripheral i/o area select control register bpc 0000h fffff06eh system wait control register vswc 77h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h r/w ffh chapter 3 cpu functions user?s manual u17830ee1v0um00 138 (2/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff10ah interrupt mask register 5l imr5l ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 r/w 47h chapter 3 cpu functions user?s manual u17830ee1v0um00 139 (3/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tm0eqic0 47h fffff146h interrupt control register cb0ric 47h fffff148h interrupt control register cb0tic 47h fffff14ah interrupt control register cb1ric 47h fffff14ch interrupt control register cb1tic 47h fffff14eh interrupt control register ua0ric 47h fffff150h interrupt control register ua0tic 47h fffff152h interrupt control register ua1ric 47h fffff154h interrupt control register ua1tic 47h fffff156h interrupt control register adic 47h fffff158h interrupt control register c0erric 47h fffff15ah interrupt control register c0wupic 47h fffff15ch interrupt control register c0recic 47h fffff15eh interrupt control register c0trxic 47h fffff160h interrupt control register kric 47h fffff162h interrupt control register wtiic 47h fffff164h interrupt control register wtic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register 0 ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail comparison mode register ada0pfm 00h fffff205h power-fail comparison threshold value register ada0pft r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 140 (4/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h r undefined fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff318h noise elimination control register nfc 00h fffff400h port 0 p0 undefined fffff406h port 3 p3 undefined fffff406h port 3l p3l undefined fffff408h port 4 p4 undefined fffff40ah port 5 p5 undefined fffff40eh port 7l p7l undefined fffff40fh port 7h p7h undefined fffff412h port 9 p9 undefined fffff412h port 9l p9l undefined fffff413h port 9h p9h r/w undefined chapter 3 cpu functions user?s manual u17830ee1v0um00 141 (5/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff420h port mode register 0 pm0 ffh fffff426h port mode register 3 pm3 ffffh fffff426h port mode register 3l pm3l ffh fffff428h port mode register 4 pm4 ffh fffff42ah port mode register 5 pm5 ffh fffff42eh port mode register 7 pm7 ffffh fffff42eh port mode register 7l pm7l ffh fffff42fh port mode register 7h pm7h ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l ffh fffff433h port mode register 9h pm9h ffh fffff440h port mode control register 0 pmc0 00h fffff446h port mode control register 3 pmc3 0000h fffff446h port mode control register 3l pmc3l 00h fffff447h port mode control register 3h pmc3h 00h fffff448h port mode control register 4 pmc4 00h fffff44ah port mode control register 5 pmc5 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l 00h fffff453h port mode control register 9h pmc9h 00h fffff460h port function control register 0 pfc0 00h fffff466h port function control register 3l pfc3l 00h fffff46ah port function control register 5 pfc5 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l 00h fffff473h port function control register 9h pfc9h 00h fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 142 (6/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 143 (7/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff610h tmq1 timer control register 0 tq1ctl0 r/w 00h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff706h port function control expansion register 3l pfce3l 00h fffff70ah port function control expansion register 5 pfce5 00h fffff712h port function control expansion register 9 pfce9 0000h fffff712h port function control expansion register 9l pfce9l 00h fffff713h port function control expansion register 9h pfce9h 00h fffff802h system status register sys 00h fffff80ch ring osc mode register rcm 00h fffff820h power save mode register psmr r/w 00h fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operating clock status register ccls r 00h fffff82fh programmable clock mode register pclm 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emulat ion register 1 pemu1 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 r/w ffh caution for ocdm details, refer to chapter 25 on-chip debug function (on-chip debug unit). chapter 3 cpu functions user?s manual u17830ee1v0um00 144 (8/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 receive data register ua1tx r/w ffh fffffb00h tip00 noise eliminator control register p00nfc 00h fffffb04h tip01 noise eliminator control register p01nfc 00h fffffb08h tip10 noise eliminator control register p10nfc 00h fffffb0ch tip11 noise eliminator control register p11nfc 00h fffffb10h tip20 noise eliminator control register p20nfc 00h fffffb14h tip21 noise eliminator control register p21nfc 00h fffffb18h tip30 noise eliminator control register p30nfc 00h fffffb1ch tip31 noise eliminator control register p31nfc 00h fffffb50h tiq00 noise eliminator control register q00nfc 00h fffffb54h tiq01 noise eliminator control register q01nfc 00h fffffb58h tiq02 noise eliminator control register q02nfc 00h fffffb5ch tiq03 noise eliminator control register q03nfc 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 0000h fffffc06h external interrupt falling edge specification register 3l intf3l 00h fffffc07h external interrupt falling edge specification register 3h intf3h 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 0000h fffffc26h external interrupt rising edge specification register 3l intr3l 00h fffffc27h external interrupt rising edge specification register 3h intr3h 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc40h pull-up resistor option register 0 pu0 00h fffffc46h pull-up resistor option register 3 pu3 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 145 (9/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc46h pull-up resistor option register 3l pu3l 00h fffffc47h pull-up resistor option register 3h pu3h 00h fffffc48h pull-up resistor option register 4 pu4 00h fffffc4ah pull-up resistor option register 5 pu5 00h fffffc52h pull-up resistor option register 9 pu9 0000h fffffc52h pull-up resistor option register 9l pu9l 00h fffffc53h pull-up resistor option register 9h pu9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 146 3.4.1.2 v850es/ff2 (1/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl pdl undefined fffff004h port dll pdll undefined fffff005h port dlh pdlh undefined fffff008h port cs pcs undefined fffff00ah port ct pct undefined fffff00ch port cm pcm undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll ffh fffff025h port mode register dlh pmdlh ffh fffff02ch port mode register cm pmcm ffh fffff04ch port mode control register cm pmccm 00h fffff064h peripheral i/o area select control register bpc 0000h fffff06eh system wait control register vswc 77h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h r/w ffh chapter 3 cpu functions user?s manual u17830ee1v0um00 147 (2/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff10ah interrupt mask register 5l imr5l ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 r/w 47h chapter 3 cpu functions user?s manual u17830ee1v0um00 148 (3/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tm0eqic0 47h fffff146h interrupt control register cb0ric 47h fffff148h interrupt control register cb0tic 47h fffff14ah interrupt control register cb1ric 47h fffff14ch interrupt control register cb1tic 47h fffff14eh interrupt control register ua0ric 47h fffff150h interrupt control register ua0tic 47h fffff152h interrupt control register ua1ric 47h fffff154h interrupt control register ua1tic 47h fffff156h interrupt control register adic 47h fffff158h interrupt control register c0erric 47h fffff15ah interrupt control register c0wupic 47h fffff15ch interrupt control register c0recic 47h fffff15eh interrupt control register c0trxic 47h fffff160h interrupt control register kric 47h fffff162h interrupt control register wtiic 47h fffff164h interrupt control register wtic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register 0 ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail comparison mode register ada0pfm 00h fffff205h power-fail comparison threshold value register ada0pft r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 149 (4/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff210h a/d conversion result register 0 ada0cr0 00h fffff211h a/d conversion result register 0h ada0cr0h 00h fffff212h a/d conversion result register 1 ada0cr1 00h fffff213h a/d conversion result register 1h ada0cr1h 00h fffff214h a/d conversion result register 2 ada0cr2 00h fffff215h a/d conversion result register 2h ada0cr2h 00h fffff216h a/d conversion result register 3 ada0cr3 00h fffff217h a/d conversion result register 3h ada0cr3h 00h fffff218h a/d conversion result register 4 ada0cr4 00h fffff219h a/d conversion result register 4h ada0cr4h 00h fffff21ah a/d conversion result register 5 ada0cr5 00h fffff21bh a/d conversion result register 5h ada0cr5h 00h fffff21ch a/d conversion result register 6 ada0cr6 00h fffff21dh a/d conversion result register 6h ada0cr6h 00h fffff21eh a/d conversion result register 7 ada0cr7 00h fffff21fh a/d conversion result register 7h ada0cr7h 00h fffff220h a/d conversion result register 8 ada0cr8 00h fffff221h a/d conversion result register 8h ada0cr8h 00h fffff222h a/d conversion result register 9 ada0cr9 00h fffff223h a/d conversion result register 9h ada0cr9h 00h fffff224h a/d conversion result register 10 ada0cr10 00h fffff225h a/d conversion result register 10h ada0cr10h 00h fffff226h a/d conversion result register 11 ada0cr11 00h fffff227h a/d conversion result register 11h ada0cr11h r 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff318h noise elimination control register nfc 00h fffff400h port 0 p0 undefined fffff406h port 3 p3 undefined fffff406h port 3l p3l undefined fffff407h port 3h p3h undefined fffff408h port 4 p4 undefined fffff40ah port 5 p5 undefined fffff40eh port 7l p7l undefined fffff40fh port 7h p7h undefined fffff412h port 9 p9 undefined fffff412h port 9l p9l undefined fffff413h port 9h p9h r/w undefined chapter 3 cpu functions user?s manual u17830ee1v0um00 150 (5/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff420h port mode register 0 pm0 ffh fffff426h port mode register 3 pm3 ffffh fffff426h port mode register 3l pm3l ffh fffff427h port mode register 3h pm3h ffh fffff428h port mode register 4 pm4 ffh fffff42ah port mode register 5 pm5 ffh fffff42eh port mode register 7 pm7 ffffh fffff42eh port mode register 7l pm7l ffh fffff42fh port mode register 7h pm7h ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l ffh fffff433h port mode register 9h pm9h ffh fffff440h port mode control register 0 pmc0 00h fffff446h port mode control register 3 pmc3 0000h fffff446h port mode control register 3l pmc3l 00h fffff447h port mode control register 3h pmc3h 00h fffff448h port mode control register 4 pmc4 00h fffff44ah port mode control register 5 pmc5 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l 00h fffff453h port mode control register 9h pmc9h 00h fffff460h port function control register 0 pfc0 00h fffff466h port function control register 3l pfc3l 00h fffff46ah port function control register 5 pfc5 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l 00h fffff473h port function control register 9h pfc9h 00h fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 151 (6/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 152 (7/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff706h port function control expansion register 3l pfce3l 00h fffff70ah port function control expansion register 5 pfce5 00h fffff712h port function control expansion register 9 pfce9 0000h fffff712h port function control expansion register 9l pfce9l 00h fffff713h port function control expansion register 9h pfce9h 00h fffff802h system status register sys 00h fffff80ch ring osc mode register rcm 00h fffff820h power save mode register psmr r/w 00h fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operating clock status register ccls r 00h fffff82fh programmable clock mode register pclm 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emulat ion register 1 pemu1 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 r/w ffh caution for ocdm details, refer to chapter 25 on-chip debug function (on-chip debug unit). chapter 3 cpu functions user?s manual u17830ee1v0um00 153 (8/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 receive data register ua1tx r/w ffh fffffb00h tip00 noise eliminator control register p00nfc 00h fffffb04h tip01 noise eliminator control register p01nfc 00h fffffb08h tip10 noise eliminator control register p10nfc 00h fffffb0ch tip11 noise eliminator control register p11nfc 00h fffffb10h tip20 noise eliminator control register p20nfc 00h fffffb14h tip21 noise eliminator control register p21nfc 00h fffffb18h tip30 noise eliminator control register p30nfc 00h fffffb1ch tip31 noise eliminator control register p31nfc 00h fffffb50h tiq00 noise eliminator control register q00nfc 00h fffffb54h tiq01 noise eliminator control register q01nfc 00h fffffb58h tiq02 noise eliminator control register q02nfc 00h fffffb5ch tiq03 noise eliminator control register q03nfc 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 0000h fffffc06h external interrupt falling edge specification register 3l intf3l 00h fffffc07h external interrupt falling edge specification register 3h intf3h 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 0000h fffffc26h external interrupt rising edge specification register 3l intr3l 00h fffffc27h external interrupt rising edge specification register 3h intr3h 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc40h pull-up resistor option register 0 pu0 00h fffffc46h pull-up resistor option register 3 pu3 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 154 (9/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc46h pull-up resistor option register 3l pu3l 00h fffffc47h pull-up resistor option register 3h pu3h 00h fffffc48h pull-up resistor option register 4 pu4 00h fffffc4ah pull-up resistor option register 5 pu5 00h fffffc52h pull-up resistor option register 9 pu9 0000h fffffc52h pull-up resistor option register 9l pu9l 00h fffffc53h pull-up resistor option register 9h pu9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 155 3.4.1.3 v850es/fg2 (1/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl pdl undefined fffff004h port dll pdll undefined fffff005h port dlh pdlh undefined fffff008h port cs pcs undefined fffff00ah port ct pct undefined fffff00ch port cm pcm undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll ffh fffff025h port mode register dlh pmdlh ffh fffff028h port mode register cs pmcs ffh fffff02ah port mode register ct pmct ffh fffff02ch port mode register cm pmcm ffh fffff04ch port mode control register cm pmccm 00h fffff064h peripheral i/o area select control register bpc 0000h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 156 (2/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 47h fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 r/w 47h chapter 3 cpu functions user?s manual u17830ee1v0um00 157 (3/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff144h interrupt control register tm0eqic0 47h fffff146h interrupt control register cb0ric 47h fffff148h interrupt control register cb0tic 47h fffff14ah interrupt control register cb1ric 47h fffff14ch interrupt control register cb1tic 47h fffff14eh interrupt control register ua0ric 47h fffff150h interrupt control register ua0tic 47h fffff152h interrupt control register ua1ric 47h fffff154h interrupt control register ua1tic 47h fffff156h interrupt control register adic 47h fffff158h interrupt control register c0erric 47h fffff15ah interrupt control register c0wupic 47h fffff15ch interrupt control register c0recic 47h fffff15eh interrupt control register c0trxic 47h fffff160h interrupt control register kric 47h fffff162h interrupt control register wtiic 47h fffff164h interrupt control register wtic 47h fffff166h interrupt control register pic8 47h fffff168h interrupt control register pic9 47h fffff16ah interrupt control register pic10 47h fffff16ch interrupt control register tq1ovic 47h fffff16eh interrupt control register tq1ccic0 47h fffff170h interrupt control register tq1ccic1 47h fffff172h interrupt control register tq1ccic2 47h fffff174h interrupt control register tq1ccic3 47h fffff176h interrupt control register ua2ric 47h fffff178h interrupt control register ua2tic 47h fffff17ah interrupt control register c1erric 47h fffff17ch interrupt control register c1wupic 47h fffff17eh interrupt control register c1recic 47h fffff180h interrupt control register c1trxic 47h fffff182h interrupt control register dmaic0 47h fffff184h interrupt control register dmaic1 47h fffff186h interrupt control register dmaic2 47h fffff188h interrupt control register dmaic3 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 158 (4/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register 0 ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail comparison mode register ada0pfm 00h fffff205h power-fail comparison threshold value register ada0pft r/w 00h fffff210h a/d conversion result register 0 ada0cr0 00h fffff211h a/d conversion result register 0h ada0cr0h 00h fffff212h a/d conversion result register 1 ada0cr1 00h fffff213h a/d conversion result register 1h ada0cr1h 00h fffff214h a/d conversion result register 2 ada0cr2 00h fffff215h a/d conversion result register 2h ada0cr2h 00h fffff216h a/d conversion result register 3 ada0cr3 00h fffff217h a/d conversion result register 3h ada0cr3h 00h fffff218h a/d conversion result register 4 ada0cr4 00h fffff219h a/d conversion result register 4h ada0cr4h 00h fffff21ah a/d conversion result register 5 ada0cr5 00h fffff21bh a/d conversion result register 5h ada0cr5h 00h fffff21ch a/d conversion result register 6 ada0cr6 00h fffff21dh a/d conversion result register 6h ada0cr6h 00h fffff21eh a/d conversion result register 7 ada0cr7 00h fffff21fh a/d conversion result register 7h ada0cr7h 00h fffff220h a/d conversion result register 8 ada0cr8 00h fffff221h a/d conversion result register 8h ada0cr8h 00h fffff222h a/d conversion result register 9 ada0cr9 00h fffff223h a/d conversion result register 9h ada0cr9h 00h fffff224h a/d conversion result register 10 ada0cr10 00h fffff225h a/d conversion result register 10h ada0cr10h 00h fffff226h a/d conversion result register 11 ada0cr11 00h fffff227h a/d conversion result register 11h ada0cr11h 00h fffff228h a/d conversion result register 12 ada0cr12 00h fffff229h a/d conversion result register 12h ada0cr12h 00h fffff22ah a/d conversion result register 13 ada0cr13 00h fffff22bh a/d conversion result register 13h ada0cr13h 00h fffff22ch a/d conversion result register 14 ada0cr14 00h fffff22dh a/d conversion result register 14h ada0cr14h 00h fffff22eh a/d conversion result register 15 ada0cr15 00h fffff22fh a/d conversion result register 15h ada0cr15h r 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff318h noise elimination control register nfc r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 159 (5/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff400h port 0 p0 undefined fffff402h port 1 p1 undefined fffff406h port 3 p3 undefined fffff406h port 3l p3l undefined fffff407h port 3h p3h undefined fffff408h port 4 p4 undefined fffff40ah port 5 p5 undefined fffff40eh port 7l p7l undefined fffff40fh port 7h p7h undefined fffff412h port 9 p9 undefined fffff412h port 9l p9l undefined fffff413h port 9h p9h undefined fffff420h port mode register 0 pm0 ffh fffff422h port mode register 1 pm1 ffh fffff426h port mode register 3 pm3 ffffh fffff426h port mode register 3l pm3l ffh fffff427h port mode register 3h pm3h ffh fffff428h port mode register 4 pm4 ffh fffff42ah port mode register 5 pm5 ffh fffff42eh port mode register 7l pm7l ffh fffff42fh port mode register 7h pm7h ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l ffh fffff433h port mode register 9h pm9h ffh fffff440h port mode control register 0 pmc0 00h fffff442h port mode control register 1 pmc1 00h fffff446h port mode control register 3 pmc3 0000h fffff446h port mode control register 3l pmc3l 00h fffff447h port mode control register 3h pmc3h 00h fffff448h port mode control register 4 pmc4 00h fffff44ah port mode control register 5 pmc5 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l 00h fffff453h port mode control register 9h pmc9h 00h fffff460h port function control register 0 pfc0 00h fffff466h port function control register 3l pfc3l 00h fffff46ah port function control register 5 pfc5 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l 00h fffff473h port function control register 9h pfc9h r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 160 (6/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 161 (7/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 0 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff610h tmq1 control register 0 tq1ctl0 00h fffff611h tmq1 control register 1 tq1ctl1 00h fffff612h tmq1 i/o control register 0 tq1ioc0 00h fffff613h tmq1 i/o control register 1 tq1ioc1 00h fffff614h tmq1 i/o control register 2 tq1ioc2 00h fffff615h tmq1 timer option register 0 tq1opt0 00h fffff616h tmq1 capture/compare register 0 tq1ccr0 0000h fffff618h tmq1 capture/compare register 1 tq1ccr1 0000h fffff61ah tmq1 capture/compare register 2 tq1ccr2 0000h fffff61ch tmq1 capture/compare register 3 tq1ccr3 r/w 0000h fffff61eh tmq1 counter read buffer register tq1cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff706h port function control expansion register 3l pfce3l 00h fffff70ah port function control expansion register 5 pfce5 00h fffff712h port function control expansion register 9 pfce9 0000h fffff712h port function control expansion register 9l pfce9l 00h fffff713h port function control expansion register 9h pfce9h 00h fffff802h system status register sys 00h fffff80ch ring osc mode register rcm 00h fffff810h dma trigger source register 0 dtfr0 00h fffff812h dma trigger source register 1 dtfr1 00h fffff814h dma trigger source register 2 dtfr2 00h fffff816h dma trigger source register 3 dtfr3 00h fffff820h power save mode register psmr r/w 00h fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operating clock status register ccls r 00h fffff82fh programmable clock mode register pclm 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 162 (8/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emulat ion register 1 pemu1 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 receive data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffb00h tip00 noise eliminator control register p00nfc 00h fffffb04h tip01 noise eliminator control register p01nfc 00h fffffb08h tip10 noise eliminator control register p10nfc 00h fffffb0ch tip11 noise eliminator control register p11nfc 00h fffffb10h tip20 noise eliminator control register p20nfc 00h fffffb14h tip21 noise eliminator control register p21nfc 00h fffffb18h tip30 noise eliminator control register p30nfc 00h fffffb1ch tip31 noise eliminator control register p31nfc 00h fffffb50h tiq00 noise eliminator control register q00nfc 00h fffffb54h tiq01 noise eliminator control register q01nfc 00h fffffb58h tiq02 noise eliminator control register q02nfc 00h fffffb5ch tiq03 noise eliminator control register q03nfc r/w 00h caution for ocdm details, refer to chapter 26 on-chip debug function (on-chip debug unit). chapter 3 cpu functions user?s manual u17830ee1v0um00 163 (9/9) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffb60h tiq10 noise eliminator control register q10nfc 00h fffffb64h tiq11 noise eliminator control register q11nfc 00h fffffb68h tiq12 noise eliminator control register q12nfc 00h fffffb6ch tiq13 noise eliminator control register q13nfc 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc02h external interrupt falling edge specification register 1 intf1 00h fffffc06h external interrupt falling edge specification register 3 intf3 0000h fffffc06h external interrupt falling edge specification register 3l intf3l 00h fffffc07h external interrupt falling edge specification register 3h intf3h 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc22h external interrupt rising edge specification register 1 intr1 00h fffffc26h external interrupt rising edge specification register 3 intr3 0000h fffffc26h external interrupt rising edge specification register 3l intr3l 00h fffffc27h external interrupt rising edge specification register 3h intr3h 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc40h pull-up resistor option register 0 pu0 00h fffffc42h pull-up resistor option register 1 pu1 00h fffffc46h pull-up resistor option register 3 pu3 0000h fffffc46h pull-up resistor option register 3l pu3l 00h fffffc47h pull-up resistor option register 3h pu3h 00h fffffc48h pull-up resistor option register 4 pu4 00h fffffc4ah pull-up resistor option register 5 pu5 00h fffffc52h pull-up resistor option register 9 pu9 0000h fffffc52h pull-up resistor option register 9l pu9l 00h fffffc53h pull-up resistor option register 9h pu9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 164 3.4.1.4 v850es/fj2 ) note the on-chip peripheral i/o differs for pd70f3237 and pd70f 3238/pd70f3239. (1/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl pdl undefined fffff004h port dll pdll undefined fffff005h port dlh pdlh undefined fffff008h port cs pcs undefined fffff00ah port ct pct undefined fffff00ch port cm pcm undefined fffff00eh port cd pcd undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll ffh fffff025h port mode register dlh pmdlh ffh fffff028h port mode register cs pmcs ffh fffff02ah port mode register ct pmct ffh fffff02ch port mode register cm pmcm ffh fffff02eh port mode register cd pmcd ffh fffff044h port mode control register dl pmcdl 0000h fffff044h port mode control register dll pmcdll 00h fffff045h port mode control register dlh pmcdlh 00h fffff048h port mode control register cs pmccs 00h fffff04ah port mode control register ct pmcct 00h fffff04ch port mode control register cm pmccm 00h fffff064h peripheral i/o area select control register bpc 0000h fffff066h bus size configuration register bus bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h r/w undefined chapter 3 cpu functions user?s manual u17830ee1v0um00 165 (2/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h ffh fffff10ah interrupt mask register 5l imr5l ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 r/w 47h chapter 3 cpu functions user?s manual u17830ee1v0um00 166 (3/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 47h fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tm0eqic0 47h fffff146h interrupt control register cb0ric 47h fffff148h interrupt control register cb0tic 47h fffff14ah interrupt control register cb1ric 47h fffff14ch interrupt control register cb1tic 47h fffff14eh interrupt control register ua0ric 47h fffff150h interrupt control register ua0tic 47h fffff152h interrupt control register ua1ric 47h fffff154h interrupt control register ua1tic 47h fffff156h interrupt control register adic 47h fffff158h interrupt control register c0erric 47h fffff15ah interrupt control register c0wupic 47h fffff15ch interrupt control register c0recic 47h fffff15eh interrupt control register c0trxic 47h fffff160h interrupt control register kric 47h fffff162h interrupt control register wtiic 47h fffff164h interrupt control register wtic 47h fffff166h interrupt control register pic8 47h fffff168h interrupt control register pic9 47h fffff16ah interrupt control register pic10 47h fffff16ch interrupt control register tq1ovic 47h fffff16eh interrupt control register tq1ccic0 47h fffff170h interrupt control register tq1ccic1 47h fffff172h interrupt control register tq1ccic2 47h fffff174h interrupt control register tq1ccic3 47h fffff176h interrupt control register ua2ric r/w 47h chapter 3 cpu functions user?s manual u17830ee1v0um00 167 (4/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff178h interrupt control register ua2tic 47h fffff17ah interrupt control register c1erric 47h fffff17ch interrupt control register c1wupic 47h fffff17eh interrupt control register c1recic 47h fffff180h interrupt control register c1trxic 47h fffff182h interrupt control register dmaic0 47h fffff184h interrupt control register dmaic1 47h fffff186h interrupt control register dmaic2 47h fffff188h interrupt control register dmaic3 47h fffff18ah interrupt control register pic11 47h fffff18ch interrupt control register pic12 47h fffff18eh interrupt control register pic13 47h fffff190h interrupt control register pic14 47h fffff192h interrupt control register tq2ovic 47h fffff194h interrupt control register tq2ccic0 47h fffff196h interrupt control register tq2ccic1 47h fffff198h interrupt control register tq2ccic2 47h fffff19ah interrupt control register tq2ccic3 47h fffff19ch interrupt control register cb2ric 47h fffff19eh interrupt control register cb2tic 47h fffff1a0h interrupt control register ua3ric 47h fffff1a2h interrupt control register ua3tic 47h fffff1a4h interrupt control register c2erric 47h fffff1a6h interrupt control register c2wupic 47h fffff1a8h interrupt control register c2recic 47h fffff1aah interrupt control register c2trxic 47h fffff1ach interrupt control register c3erric 47h fffff1aeh interrupt control register c3wupic 47h fffff1b0h interrupt control register c3recic 47h fffff1b2h interrupt control register c3trxic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register 0 ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail comparison mode register ada0pfm 00h fffff205h power-fail comparison threshold value register ada0pft r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 168 (5/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff210h a/d conversion result register 0 ada0cr0 00h fffff211h a/d conversion result register 0h ada0cr0h 00h fffff212h a/d conversion result register 1 ada0cr1 00h fffff213h a/d conversion result register 1h ada0cr1h 00h fffff214h a/d conversion result register 2 ada0cr2 00h fffff215h a/d conversion result register 2h ada0cr2h 00h fffff216h a/d conversion result register 3 ada0cr3 00h fffff217h a/d conversion result register 3h ada0cr3h 00h fffff218h a/d conversion result register 4 ada0cr4 00h fffff219h a/d conversion result register 4h ada0cr4h 00h fffff21ah a/d conversion result register 5 ada0cr5 00h fffff21bh a/d conversion result register 5h ada0cr5h 00h fffff21ch a/d conversion result register 6 ada0cr6 00h fffff21dh a/d conversion result register 6h ada0cr6h 00h fffff21eh a/d conversion result register 7 ada0cr7 00h fffff21fh a/d conversion result register 7h ada0cr7h 00h fffff220h a/d conversion result register 8 ada0cr8 00h fffff221h a/d conversion result register 8h ada0cr8h 00h fffff222h a/d conversion result register 9 ada0cr9 00h fffff223h a/d conversion result register 9h ada0cr9h 00h fffff224h a/d conversion result register 10 ada0cr10 00h fffff225h a/d conversion result register 10h ada0cr10h 00h fffff226h a/d conversion result register 11 ada0cr11 00h fffff227h a/d conversion result register 11h ada0cr11h 00h fffff228h a/d conversion result register 12 ada0cr12 00h fffff229h a/d conversion result register 12h ada0cr12h 00h fffff22ah a/d conversion result register 13 ada0cr13 00h fffff22bh a/d conversion result register 13h ada0cr13h 00h fffff22ch a/d conversion result register 14 ada0cr14 00h fffff22dh a/d conversion result register 14h ada0cr14h 00h fffff22eh a/d conversion result register 15 ada0cr15 00h fffff22fh a/d conversion result register 15h ada0cr15h 00h fffff230h a/d conversion result register 16 ada0cr16 00h fffff231h a/d conversion result register 16h ada0cr16h 00h fffff232h a/d conversion result register 17 ada0cr17 00h fffff233h a/d conversion result register 17h ada0cr17h 00h fffff234h a/d conversion result register 18 ada0cr18 00h fffff235h a/d conversion result register 18h ada0cr18h 00h fffff236h a/d conversion result register 19 ada0cr19 00h fffff237h a/d conversion result register 19h ada0cr19h r 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 169 (6/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff238h a/d conversion result register 20 ada0cr20 00h fffff239h a/d conversion result register 20h ada0cr20h 00h fffff23ah a/d conversion result register 21 ada0cr21 00h fffff23bh a/d conversion result register 21h ada0cr21h 00h fffff23ch a/d conversion result register 22 ada0cr22 00h fffff23dh a/d conversion result register 22h ada0cr22h 00h fffff23eh a/d conversion result register 23 ada0cr23 00h fffff23fh a/d conversion result register 23h ada0cr23h r 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff30ah selector operation control register 1 selcnt1 00h fffff318h noise elimination control register nfc 00h fffff400h port 0 p0 undefined fffff402h port 1 p1 undefined fffff406h port 3 p3 undefined fffff406h port 3l p3l undefined fffff407h port 3h p3h undefined fffff408h port 4 p4 undefined fffff40ah port 5 p5 undefined fffff40ch port 6 p6 undefined fffff40ch port 6l p6l undefined fffff40dh port 6h p6h undefined fffff40eh port 7l p7l undefined fffff40fh port 7h p7h undefined fffff410h port 8 p8 undefined fffff412h port 9 p9 undefined fffff412h port 9l p9l undefined fffff413h port 9h p9h undefined fffff418h port 12 p12 undefined fffff420h port mode register 0 pm0 ffh fffff422h port mode register 1 pm1 ffh fffff426h port mode register 3 pm3 ffffh fffff426h port mode register 3l pm3l ffh fffff427h port mode register 3h pm3h ffh fffff428h port mode register 4 pm4 ffh fffff42ah port mode register 5 pm5 ffh fffff42ch port mode register 6 pm6 r/w ffffh chapter 3 cpu functions user?s manual u17830ee1v0um00 170 (7/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff42ch port mode register 6l pm6l ffh fffff42dh port mode register 6h pm6h ffh fffff42eh port mode register 7l pm7l ffh fffff42fh port mode register 7h pm7h ffh fffff430h port mode register 8 pm8 ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l ffh fffff433h port mode register 9h pm9h ffh fffff438h port mode register 12 pm12 ffh fffff440h port mode control register 0 pmc0 00h fffff442h port mode control register 1 pmc1 00h fffff446h port mode control register 3 pmc3 0000h fffff446h port mode control register 3l pmc3l 00h fffff447h port mode control register 3h pmc3h 00h fffff448h port mode control register 4 pmc4 00h fffff44ah port mode control register 5 pmc5 00h fffff44ch port mode control register 6 pmc6 0000h fffff44ch port mode control register 6l pmc6l 00h fffff44dh port mode control register 6h pmc6h 00h fffff450h port mode control register 8 pmc8 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l 00h fffff453h port mode control register 9h pmc9h 00h fffff460h port function control register 0 pfc0 00h fffff466h port function control register 3l pfc3l 00h fffff46ah port function control register 5 pfc5 00h fffff46ch port function control register 6 pfc6 0000h fffff46ch port function control register 6l pfc6l 00h fffff46dh port function control register 6h pfc6h 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l 00h fffff473h port function control register 9h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 171 (8/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 172 (9/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff610h tmq1 timer control register 0 tq1ctl0 00h fffff611h tmq1 control register 1 tq1ctl1 00h fffff612h tmq1 i/o control register 0 tq1ioc0 00h fffff613h tmq1 i/o control register 1 tq1ioc1 00h fffff614h tmq1 i/o control register 2 tq1ioc2 00h fffff615h tmq1 timer option register tq1opt0 00h fffff616h tmq1 capture/compare register 0 tq1ccr0 0000h fffff618h tmq1 capture/compare register 1 tq1ccr1 0000h fffff61ah tmq1 capture/compare register 2 tq1ccr2 0000h fffff61ch tmq1 capture/compare register 3 tq1ccr3 r/w 0000h fffff61eh tmq1 counter read buffer register tq1cnt r 0000h fffff620h tmq2 control register 0 tq2ctl0 00h fffff621h tmq2 control register 1 tq2ctl1 00h fffff622h tmq2 i/o control register 0 tq2ioc0 00h fffff623h tmq2 i/o control register 1 tq2ioc1 00h fffff624h tmq2 i/o control register 2 tq2ioc2 00h fffff625h tmq2 option register tq2opt0 00h fffff626h tmq2 capture/compare register 0 tq2ccr0 0000h fffff628h tmq2 capture/compare register 1 tq2ccr1 0000h fffff62ah tmq2 capture/compare register 2 tq2ccr2 0000h fffff62ch tmq2 capture/compare register 3 tq2ccr3 r/w 0000h fffff62eh tmq2 counter read buffer register tq2cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff706h port function control expansion register 3l pfce3l 00h fffff70ah port function control expansion register 5 pfce5 00h fffff712h port function control expansion register 9 pfce9 0000h fffff712h port function control expansion register 9l pfce9l 00h fffff713h port function control expansion register 9h pfce9h 00h fffff802h system status register sys 00h fffff80ch ring osc mode register rcm 00h fffff810h dma trigger source register 0 dtfr0 00h fffff812h dma trigger source register 1 dtfr1 00h fffff814h dma trigger source register 2 dtfr2 00h fffff816h dma trigger source register 3 dtfr3 00h fffff820h power save mode register psmr r/w 00h fffff824h lock register lockr r 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 173 (10/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operating clock status register ccls r 00h fffff82fh programmable clock mode register pclm 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emulat ion register 1 pemu1 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 receive data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffa30h uarta3 control register 0 ua3ctl0 10h fffffa31h uarta3 control register 1 ua3ctl1 00h fffffa32h uarta3 control register 2 ua3ctl2 ffh fffffa33h uarta3 option control register 0 ua3opt0 14h fffffa34h uarta3 status register ua3str r/w 00h fffffa36h uarta3 receive data register ua3rx r ffh fffffa37h uarta3 transmit data register ua3tx r/w ffh caution for ocdm details, refer to chapter 27 on-chip debug function (on-chip debug unit). chapter 3 cpu functions user?s manual u17830ee1v0um00 174 (11/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffb00h tip00 noise eliminator control register p00nfc 00h fffffb04h tip01 noise eliminator control register p01nfc 00h fffffb08h tip10 noise eliminator control register p10nfc 00h fffffb0ch tip11 noise eliminator control register p11nfc 00h fffffb10h tip20 noise eliminator control register p20nfc 00h fffffb14h tip21 noise eliminator control register p21nfc 00h fffffb18h tip30 noise eliminator control register p30nfc 00h fffffb1ch tip31 noise eliminator control register p31nfc 00h fffffb50h tiq00 noise eliminator control register q00nfc 00h fffffb54h tiq01 noise eliminator control register q01nfc 00h fffffb58h tiq02 noise eliminator control register q02nfc 00h fffffb5ch tiq03 noise eliminator control register q03nfc 00h fffffb60h tiq10 noise eliminator control register q10nfc 00h fffffb64h tiq11 noise eliminator control register q11nfc 00h fffffb68h tiq12 noise eliminator control register q12nfc 00h fffffb6ch tiq13 noise eliminator control register q13nfc 00h fffffb70h tiq20 noise eliminator control register q20nfc 00h fffffb74h tiq21 noise eliminator control register q21nfc 00h fffffb78h tiq22 noise eliminator control register q22nfc 00h fffffb7ch tiq23 noise eliminator control register q23nfc 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc02h external interrupt falling edge specification register 1 intf1 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 0000h fffffc06h external interrupt falling edge specification register 3l intf3l 00h fffffc07h external interrupt falling edge specification register 3h intf3h 00h fffffc0ch external interrupt falling edge specification register 6l intf6l 00h fffffc10h external interrupt falling edge specification register 8 intf8 00h fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc22h external interrupt rising edge specification register 1 intr1 00h fffffc26h external interrupt rising edge specification register 3 intr3 0000h fffffc26h external interrupt rising edge specification register 3l intr3l 00h fffffc27h external interrupt rising edge specification register 3h intr3h 00h fffffc2ch external interrupt rising edge specification register 6l intr6l 00h fffffc30h external interrupt rising edge specification register 8 intr8 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc40h pull-up resistor option register 0 pu0 00h fffffc42h pull-up resistor option register 1 pu1 00h fffffc46h pull-up resistor option register 3 pu3 0000h chapter 3 cpu functions user?s manual u17830ee1v0um00 175 (12/12) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc46h pull-up resistor option register 3l pu3l 00h fffffc47h pull-up resistor option register 3h pu3h 00h fffffc48h pull-up resistor option register 4 pu4 00h fffffc4ah pull-up resistor option register 5 pu5 00h fffffc4ch pull-up resistor option register 6 pu6 0000h fffffc4ch pull-up resistor option register 6l pu6l 00h fffffc4dh pull-up resistor option register 6h pu6h 00h fffffc50h pull-up resistor option register 8 pu8 00h fffffc52h pull-up resistor option register 9 pu9 0000h fffffc52h pull-up resistor option register 9l pu9l 00h fffffc53h pull-up resistor option register 9h pu9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl r/w 00h chapter 3 cpu functions user?s manual u17830ee1v0um00 176 3.4.8 programmable peri pheral i/o register the peripheral i/o area select control regi ster (bpc) is used to select a programmable peripheral i/o register area. peripheral i/o registers for the can controller are allocated to addresses 03fec000h to 03fee6efh of the programmable per ipheral i/o register area. for details, see ch apter 15 can controller. (1) peripheral i/o select c ontrol register (bpc) this register can be read or written in 16-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: fffff064h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b p c pa 1 5 0 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pa15 enable or disable of use of programmable peripheral i/o area 0 disable use of programmable peripheral i/o area. 1 enable use of programmable peripheral i/o area. pa 1 3 t o pa 0 setting of resumption address of programmable peripheral i/o area (correspond to a27 to a14). caution be sure to set the bpc register to 8ffbh when the pa15 bit is set to 1. be sure to set the bpc register to 000 0h when the pa15 bit is cleared to 0. chapter 3 cpu functions user?s manual u17830ee1v0um00 177 3.4.9 special registers special registers are protect ed so that no illegal data is wr itten to them in case of a program loop. the v850es/fx2 have the following seven special registers. ? power save control register (psc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) a command register (prcmd) is provided as a register that protects the special registers from a write operation so that the application system does not stop inadvertently in case of a program loop. a write access to a special register is performed in a specific sequence, and an illegal store operation is reported to the system status register (sys) (if an operation to read option data (address: 007ah) is illegal due to noise or instantaneous voltage drop, it is also reported to the system status register (sys)). chapter 3 cpu functions user?s manual u17830ee1v0um00 178 (1) setting data to special register data is set to the special registers in the following sequence. <1> disable the dma operation. <2> prepare data to be set to a special register, in a general-purpose register. <3> write the data prepared in <2 > to the command register (prcmd). <4> write the data to the special regist er (by using the following instructions). ? store instruction (st/sst instruction). ? bit manipulation instruction (set1/clr1/not1 instruction). <5> to <9> insert nop instru ctions (five instructions). <10> enable dma operation if necessary. [example] to set data to the psc register (to set standby mode) st.b r11, psmr [r0] ; setting psmr register (setting idle1, idle2, or software stop mode). <1> clr1 0, dchcn [r0] ; disabling dma operation. n = 0 to 3 <2> mov 0x02, r10 <3> st.b r10, prcmd [r0] ; writing prcmd register. <4> st.b r10, psc [r0] ; setting psc register. <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction <9> nop ; dummy instruction <10> set1 0, dchcn [r0] ; enabling dma operation. n = 0 to 3 (next instruction) no specific sequence is necessary for reading a special register. cautions 1. the instruction that stores data in the command register does not acknowledge an interrupt. this is because it is assumed th at steps <3> and <4> above are executed by successive store instructions. if an other in struction is written be tween <3> and <4>, and if that instruction acknowledges an interrupt , the above sequence may not be established, causing malfunction. 2. dummy data is written to the prcmd regi ster. use the same general-purpose register as the one used to set th e special register (<4> in the a bove example) for writing the prcmd register (<3>). the same applies when usi ng a general-purpose register for addressing. 3. when shifting to idle1, id le2, software stop mode and sub-idle mode (stp bit of psc register = 1), five nop instructions or more must be inserted immediately after entering that mode. chapter 3 cpu functions user?s manual u17830ee1v0um00 179 (2) command register (prcmd) the command register (prcmd) is an 8-bi t register that is used to protect a register that may seriously affect the system from a write operation, so that the application system does no t stop inadvertently in case of a program loop. only the first writing of a special regi ster is valid after a write operation is performed on the prcmd register in advance. the value written to t he prcmd register can be rewr itten only in a specific sequence, so that an illegal wr ite operation cann ot be executed. the prcmd register is write-only; in 8-bit units (if this register is read, illegal data is read). this register becomes undefined at reset. 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu functions user?s manual u17830ee1v0um00 180 (3) system status register (sys) a status flag that indicates the ov erall operating status of the system is allocated to this register. this register can be read or written in 8-bit or 1-bit units. this register becomes 00h at reset. 0 prerr 0 1 sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h 7 6 54 3 2 1 <0> protection error did not occur. protection error occurred. detection of protection error the prerr flag operates under the following conditions. (a) setting condition (prerr flag = 1) (i) when a write operation is not performed on the p rcmd register and an operat ion to write a special register is performed (when <4> in the example in 3.4.9 (1) setting data to special register is executed without <3>) (ii) if a write operation (including a bit manipulation instruction) is performed on an on-chip peripheral i/o register other than a special regist er after a write operation to the prcmd register (when <4> in the example in 3.4.9 (1) setting data to special register is not for a special register) remark even if an on-chip peripheral i/o register is read (including a bit manipulation instruction) between writing the prcmd register and writing a special regi ster such as an access to the internal ram, the prerr flag is not set, and data can be written to the special register. (b) clearing condition (prerr flag = 0) (i) when 0 is written to the prerr flag of the sys register (ii) when system reset is executed cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write operation to the prcmd register, the prerr bit is cleared to 0 (write priority). 2. if a write operation is performed on the prcmd register, which is not a special register immediately after a write operation to the prcmd register, the prerr bit is set to 1. chapter 3 cpu functions user?s manual u17830ee1v0um00 181 3.4.10 cautions (1) registers to be set first be sure to set the following registers first when using the v850es/fx2. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register (wdtm2 after setting the ocdm register, set the vswc r egister, and set other registers as necessary. when using the external bus, place each pin in the cont rol mode by setting the port-re lated registers immediately after setting the above registers. (a) system wait control register (vswc) the vswc register is used to control the wait cycle of a bus access to an on-chip peripheral i/o register. three clocks are required to access an on-chip periph eral i/o register (when no wait cycle is used). the v850es/fx2 requires a wait cycle depending on the operat ing frequency used. set the following value to the vswc register. this register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of wait cycles 32 khz f clk < 16.6 mhz 00h 0 16.6 mhz f clk 20 mhz 01h 1 remark if an attempt to change the contents of one of t he following registers by hardware conflicts with a cpu access to the register, the register access is kept waiting. consequently, an access to an on- chip peripheral i/o register may take a longer time than usual. peripheral function register name timer p (n = 0 to 3) tpnccr0, tpnccr1, tpncnt timer p (n = 1, 2) tqnccr0, tqnccr1, tqnccr2, tqnccr3, tqncnt watchdog timer 2 wdtm2 a/d converter (n = 0 to 23) ada0m0, ada0crn, ada0crnh can controller each control register, each message buffer register (b) on-chip debug mode register (ocdm) for details, see chapter 27 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and the operation clock of the watchdog timer 2. the watchdog timer 2 automatically st arts in the reset mode after reset is released. write the wdtm2 register to activate this operation. for details, refer to chapter 10 functions of watchdog timer 2 . chapter 3 cpu functions user?s manual u17830ee1v0um00 182 (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the clock of the peripheral bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for accessing the cpu changes when the peripheral hardware is accessed, so that correct data is transferred. as a result, the cpu does not start processing of the next instruction but enters the wait state. if this wait state occurs, the num ber of clocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o registers are accesse d, more wait states may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. (1/2) peripheral function register name access k tpncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter p (tmp) (n = 0 to 4) tpnccr0, tpnccr1 read 1 or 2 tqncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter q (tmq) (n= 0 (v850es/fe2, v850es/ff2)) (n= 0, 1 (v850es/fg2)) (n= 0 to 3 (v850es/fj2)) tqnccr0 to tqnccr3 read 1 or 2 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 ada0m0 read 1 or 2 ada0cr0 to ada0crn read 1 or 2 a/d converter (n= 9 (v850es/fe2)) (n= 11 (v850es/ff2)) (n= 15 (v850es/fg2)) (n= 23 (v850es/fj2)) ada0cr0h to ada0crnh read 1 or 2 chapter 3 cpu functions user?s manual u17830ee1v0um00 183 (2/2) peripheral function register name access k cngmctrl, cngmcs, cngmabt, cngmabtd, cnmaskal, cnmaskah, cnctrl, cnlec, cninfo, cnerc, cnie, cnints, cnbrp, cnbtr, cnts read/write (f xx /f canmod + 1)/(2 + j) (min.) note (2 f xx /f canmod + 1)/(2 + j) (max.) note write (f xx /f canmod + 1)/(2 + j) (min.) note (2 f xx /f canmod + 1)/(2 + j) (max.) note cnrgpt, cntgpt read (3 f xx /f canmod + 1)/(2 + j) (min.) note (4 f xx /f canmod + 1)/(2 + j) (max.) note cnlipt, cnlopt read (3 f xx /f canmod + 1)/(2 + j) (min.) note (4 f xx /f canmod + 1)/(2 + j) (max.) note write (8 bits) (4 f xx /f canmod + 1)/(2 + j) (min.) note (5 f xx /f canmod + 1)/(2 + j) (max.) note write (16 bits) (2 f xx /f canmod + 1)/(2 + j) (min.) note (3 f xx /f canmod + 1)/(2 + j) (max.) note can controller (n= 0 (pd703230)) (n= 0 (pd70f3231)) (n= 0 (pd703232)) (n= 0 (pd703233)) (n = 0, 1 (pd70f3234)) (n = 0, 1 (pd70f3235)) (n = 0, 1 (pd70f3236)) (n = 0, 1 (pd70f3237)) (n = 0 to 3 (pd70f3238)) (n = 0 to 3 (pd70f3239)) (m = 0 to 31, a = 1 to 4) cnmdata01m, cnmdata0m, cnmdata1m, cnmdata23m, cnmdata2m, cnmdata3m, cnmdata45m, cnmdata4m, cnmdata5m, cnmdata67m, cnmdata6m, cnmdata7m, cnmdlcm, cnmconfm, cnmidlm, cnmidhm, cnmctrlm read (8/16 bits) (3 f xx /f canmod + 1)/(2 + j) (min.) note (4 f xx /f canmod + 1)/(2 + j) (max.) note number of clocks necessary for access = 3 + i + j + (2 + j) k note digits below the decimal point are rounded up. caution accessing the above register s is prohibited in th e following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock remark f xx : main clock frequency = f xx f canmod : can module system clock i: values (0) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register user?s manual u17830ee1v0um00 184 chapter 4 port functions 4.1 features o i/o ports: 51 (v850es/fe2), 67 (v850es/ff2), 84 (v850es/fg2), or 128 (v850es/fj2) o port pins function alternately as other peripheral-function i/o pins o can be set in input or output mode in 1-bit units. 4.2 basic port configuration 4.2.1 basic port configuration on v850es/fe2 the v850es/fe2 has a total of 51 i/o ports, ports 0, 3 to 5, 7, 9, cm and dl. the port configuration is shown below. figure 4-1. port configuration (v850es/fe2) p00 p06 port 0 pcm0 pcm1 port cm p96 p99 port 9 p913 p915 p90 p91 pdl0 pdl7 port dl p40 p42 port 4 p50 p55 port 5 p70 p79 port 7 p30 p35 port 3 table 4-1 pin i/o buffer power supplies (v850es/fe2) power supply corresponding pin av ref0 port 7 ev dd port 0, port 3, port 4, port 5, port 9, port cm, port dl, reset chapter 4 port functions user?s manual u17830ee1v0um00 185 4.2.2 port configuration on v850es/ff2 the v850es/ff2 has a total of 67 i/o ports, ports 0, 3 to 5, 7, 9, cm, cs, ct and dl. the port configuration is shown below. figure 4-2. port configuration (v850es/ff2) p00 p06 port 0 pcm0 pcm3 port cm pcs0 pcs1 port cs p96 p99 port 9 p913 p915 p90 p91 pct0 pct1 port ct pct4 pct6 pdl0 pdl11 port dl p40 p42 port 4 p50 p55 port 5 p70 p711 port 7 p30 p35 port 3 p38 p39 table 4-2 pin i/o buffer power supplies (v850es/ff2) power supply corresponding pin av ref0 port 7 ev dd port 0, port 3, port 4, port 5, port 9, port cm, port cs, port ct, port dl, reset chapter 4 port functions user?s manual u17830ee1v0um00 186 4.2.3 port configuration on v850es/fg2 the v850es/fg2 has a total of 84 i/o ports, ports 0, 1, 3 to 5, 7, 9, cm, cs, ct, and dl. the port configuration is shown below. figure 4-3. port configuration (v850es/fg2) p00 p06 port 0 p90 p915 port 9 pcm0 pcm3 port cm pcs0 pcs1 port cs pct0 pct1 port ct pct4 pct6 pdl0 pdl13 port dl p30 p39 port 3 p40 p42 port 4 p50 p55 port 5 p70 p715 port 7 p10 p11 port 1 table 4-3 pin i/o buffer power supplies (v850es/fg2) power supply corresponding pin av ref0 port 7 ev dd port 0, port 1, port 3, port 4, port 5, port 9, reset bv dd port cm, port cs, port ct, port dl chapter 4 port functions user?s manual u17830ee1v0um00 187 4.2.4 port configuration on v850es/fj2 the v850es/fj2 features a total of 128 i/o ports consisting of ports 0, 1, 3 to 9, 12, cd, cm, cs, ct, and dl. the port configuration is shown below. figure 4-4. port configuration (v850es/fj2) p00 p06 port 0 p90 p915 port 9 p120 p127 port 12 pcd0 pcd3 port cd pcm0 pcm5 port cm pcs0 pcs7 port cs pct0 pct7 port ct pdl0 pdl15 port dl p30 p39 port 3 p40 p42 port 4 p50 p55 port 5 p60 p615 port 6 p70 p715 port 7 p10 p11 port 1 p80 p81 port 8 table 4-4 pin i/o buffer power supplies (v850es/fj2) power supply corresponding pin av ref0 port 7, port 12 bv dd port cd, port cm, port cs, port ct, port dl ev dd port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, reset chapter 4 port functions user?s manual u17830ee1v0um00 188 4.3 port configuration the following tables give the relevant registers to configure ports on v850es/fe 2, v850es/ff2, v850es/fg2, v850es/fj2. table 4-5 port configuration (v850es/fe2) item configuration port mode register (pmn: n = 0, 3, 4, 5, 7l, 7h, 9, cm, or dl) port mode control register (pmcn: n = 0, 3, 4, 5, 9, cm, or dl) port function control register (pfcn: n = 0, 3l, 5, or 9) port function control expansion register (pfcen: n = 3l, 5, or 9) control registers pull-up resistor option register (pun: n = 0, 3, 4, 5, or 9) ports 51 table 4-6 port configuration (v850es/ff2) item configuration port mode register (pmn: n = 0, 3, 4, 5, 7l, 7h, 9, cm, cs, ct, or dl) port mode control register (pmcn: n = 0, 3, 4, 5, 9, cm, cs, ct, or dl) port function control register (pfcn: n = 0, 3l, 5, or 9) port function control expansion register (pfcen: n = 3l, 5, or 9) control registers pull-up resistor option register (pun: n = 0, 3, 4, 5, or 9) ports 67 table 4-7 port configuration (v850es/fg2) item configuration port mode register (pmn: n = 0, 1, 3, 4, 5, 7l, 7h, 9, cm, cs, ct, or dl) port mode control register (pmcn: n = 0, 1, 3, 4, 5, 9, cm, or dl) port function control register (pfcn: n = 0, 3l, 5, or 9) port function control expansion register (pfcen: n = 3l, 5, or 9) control registers pull-up resistor option register (pun: n = 0, 1, 3, 4, 5, or 9) ports 84 table 4-8 port configuration (v850es/fj2) item configuration port mode register (pmn: n = 0, 1, 3, 4, 5, 6, 7l, 7h, 8, 9, 12, cd, cm, cs, ct, or dl) port mode control register (pmcn: n = 0, 1, 3, 4, 5, 6, 8, 9, cd, cm, cs, ct, or dl) port function control register (pfcn: n = 0, 3l, 5, 6, or 9) port function control expansion register (pfcen: n = 3l, 5, or 9) control registers pull-up resistor option register (pun: n = 0, 1, 3, 4, 5, 6, 8, or 9) ports 128 chapter 4 port functions user?s manual u17830ee1v0um00 189 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 outputs 0 outputs 1 pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-9 writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read. input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note . the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. chapter 4 port functions user?s manual u17830ee1v0um00 190 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mo de can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the por t can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w chapter 4 port functions user?s manual u17830ee1v0um00 191 (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function (5) port n function control expansion register (pfcen) the pfcen register specifies the alte rnate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 chapter 4 port functions user?s manual u17830ee1v0um00 192 (6) port n function register (pfn) the pfn register specifies normal output or n-ch open-drain output. each bit of this register corresponds to one pin of por t n, and the output mode of the port pin can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is specified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input mode is specified), the set value of the pfn register is invalid. chapter 4 port functions user?s manual u17830ee1v0um00 193 (7) port setting set a port as illustrated below. figure 4-5. setting of each register and pin function pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pfcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. chapter 4 port functions user?s manual u17830ee1v0um00 194 4.3.1 port 0 port 0 is a 7-bit (p00 to p06) port for wh ich i/o settings can be controlled in 1-bit units. the number of i/o port pins is the same for all products. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 v850es/fj2 7-bit i/o port (p00 to p06) (1) functions of port 0 ? the input/output data of the port can be specified in 1-bit units. specified by port register 0 (p0) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 0 (pm0) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 0 (pmc0) ? control mode 1 or control mode 2 can be specified in 1-bit units. specified by port function control register 0 (pfc0) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 0 (pu0) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 0 (intf0) and external interrupt rising edge specification register 0 (intr0) chapter 4 port functions user?s manual u17830ee1v0um00 195 port 0 includes the following alternate-function pins. table 4-10 alternate-function pins of port 0 pin name alternate-function pin name i/o remark block type p00 tp31/top31 g-1 p01 tp30/top30 g-1 p02 nmi note 1 l-1 p03 intp0/adtrg n-1 p04 intp1 l-1 p05 intp2/drst note 2 aa-1 port 0 p06 intp3 i/o l-2 notes 1. the nmi pin is used in combination with the p02 pin. (1) after reset the p02 pin function is active. set the pmc0.pmc02 bit when you make nmi effective. (2) moreover, the nmi pin initialization is "no edge dete ction". select an effective edge of the nmi pin by the intf0 and the intr0 register. 2. the drst pin is for on-chip debugging (flash memory version only). if on-chip debugging is not used, fix the p05/intp 2/drst pin to low level between when the reset signal of the reset pin is released and when t he ocdm.ocdm0 bit is cleared (0). although the mask rom versions do not support the on-chip debug mode, handle the p05/intp2 pin the same as in flash memory versions. for details, see 4.4.3 cautions on on-chip debug pins. caution: the p00 to p06 pins have hysteresis ch aracteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. chapter 4 port functions user?s manual u17830ee1v0um00 196 (2) registers (a) port register 0 (p0) port register 0 (p0) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff400h 7 6 5 4 3 2 1 0 p0 0 p06 p05 p04 p03 p02 p01 p00 p0n control of output data (in output mode) (n = 0 to 6) 0 output 0. 1 output 1. (b) port mode register 0 (pm0) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff420h 7 6 5 4 3 2 1 0 pm0 1 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n control of input/output mode (n = 0 to 6) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 197 (c) port mode control register 0 (pmc0) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff440h 7 6 5 4 3 2 1 0 pmc0 0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 pmc06 specification of operation mode of p06 pin 0 i/o port 1 intp3 input pmc05 specification of operation mode of p05 pin 0 i/o port 1 intp2/drst input pmc04 specification of operation mode of p04 pin 0 i/o port 1 intp1 input pmc03 specification of operation mode of p03 pin 0 i/o port 1 intp0/adtrg input pmc02 specification of operation mode of p02 pin 0 i/o port 1 nmi input pmc01 specification of operation mode of p01 pin 0 i/o port 1 tip30/top30 i/o pmc00 specification of operation mode of p00 pin 0 i/o port 1 tip31/top31 i/o caution the p05/intp2/drst pin functions as th e drst pin when the o cdm0 bit of the ocdm register is 1, regardless of the value of the pmc05 bit. chapter 4 port functions user?s manual u17830ee1v0um00 198 (d) port function control register 0 (pfc0) this is an 8-bit register that specifies control mode 1 or control mode 2. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff460h 7 6 5 4 3 2 1 0 pfc0 0 0 0 0 pfc03 0 pfc01 pfc00 pfc03 specification of operation mode when p03 pin is in control mode 0 intp0 input 1 adtrg input pfc01 specification of operation mode when p01 pin is in control mode 0 tip30 input 1 top30 output pfc00 specification of operation mode when p00 pin is in control mode 0 tip31 input 1 top31 output (e) pull-up resistor option register 0 (pu0) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc40h 7 6 5 4 3 2 1 0 pu0 0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 pu0n control of on-chip pull-up resistor connection (n = 0 to 6) 0 not connected 1 connected chapter 4 port functions user?s manual u17830ee1v0um00 199 (f) external interrupt falling edge specification register 0 (intf0) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf0n and intr0n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. 3. for how to set the internal noise filter (analog delay/digita l delay) of intp3, refer to chapter 17 interrupt/exception processing function. after reset: 00h r/w address: fffffc00h 7 6 5 4 3 2 1 0 intf0 0 intf06 intf05 intf04 intf03 intf02 0 0 remark refer to table 4-11 for how to specify a valid edge. (g) external interrupt rising edge specification register 0 (intr0) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf0n and intr0n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. 3. for how to set the internal noise filter (analog delay/digita l delay) of intp3, refer to chapter 17 interrupt/exception processing function. after reset: 00h r/w address: fffffc20h 7 6 5 4 3 2 1 0 intr0 0 intr06 intr05 intr04 intr03 intr02 0 0 remark refer to table 4-11 for how to specify a valid edge. chapter 4 port functions user?s manual u17830ee1v0um00 200 table 4-11 valid edge specification intf0n bit intr0n bit valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3: control of intp0 pin n = 4: control of intp1 pin n = 5: control of intp2 pin n = 6: control of intp3 pin chapter 4 port functions user?s manual u17830ee1v0um00 201 4.3.2 port 1 port 1 is a 2-bit port (p10 and p11) for which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 v850es/ff2 - v850es/fg2 v850es/fj2 2-bit i/o port (p10 and p11) (1) functions of port 1 o the input/output data of the port can be specified in 1-bit units. specified by port register 1 (p1) o the input/output mode of the port can be specified in 1-bit units. specified by port mode register 1 (pm1) o port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 1 (pmc1) o an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 1 (pu1) o the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 1 (intf1) and external interrupt rising edge specification register 1 (intr1) port 1 functions alternately as the following pins. table 4-12 alternate-function pins of port 1 pin name alternate-function pin name i/o remark block type p10 intp9 l-1 port 1 p11 intp10 i/o ? l-1 caution: the p10 to p11 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis char acteristics in the port mode. chapter 4 port functions user?s manual u17830ee1v0um00 202 (2) registers (a) port register 1 (p1) port register 1 (p1) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff402h (i) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 p1 0 0 0 0 0 0 p11 p10 p1n control of output data (in output mode) (n = 0, 1) 0 output 0. 1 output 1. (b) port mode register 1 (pm1) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff422h (i) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 pm1 1 1 1 1 1 1 pm11 pm10 pm1n control of input/output mode (n = 0, 1) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 203 (c) port mode control register 1 (pmc1) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff442h (i) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 pmc1 0 0 0 0 0 0 pmc11 pmc10 pmc11 specification of operation mode of p11 pin 0 i/o port 1 intp10 input pmc10 specification of operation mode of p10 pin 0 i/o port 1 intp9 input (d) pull-up resistor option register 1 (pu1) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc42h (i) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 pu1 0 0 0 0 0 0 pu11 pu10 pu1n control of on-chip pull-up resistor connection (n = 0, 1) 0 not connected 1 connected chapter 4 port functions user?s manual u17830ee1v0um00 204 (e) external interrupt falling edge specification register 1 (intf1) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf1n and intr1n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc02h (i) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 intf1 0 0 0 0 0 0 intf11 intf10 remark refer to table 4-13 for how to specify a valid edge. (f) external interrupt rising edge specification register 1 (intr1) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf1n and intr1n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc22h (i) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 intr1 0 0 0 0 0 0 intr11 intr10 remark refer to table 4-13 for how to specify a valid edge. chapter 4 port functions user?s manual u17830ee1v0um00 205 table 4-13 valid edge specification intf1n bit intr1n bit valid edge specification (n = 0, 1) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of intp9 pin n = 1: control of intp10 pin chapter 4 port functions user?s manual u17830ee1v0um00 206 4.3.3 port 3 port 3 is a 10-bit port (p30 to p39) for whic h i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 6-bit i/o port (p30 to p35) v850es/ff2 8-bit i/o port (p30 to p35, p38, p39) note v850es/fg2 v850es/fj2 10-bit i/o port (p30 to p39) note in the v850es/ff2, the alternate functions of t he p38 and p39 pins (txda2, rxda2/intp8) are not available. (1) function of port 3 ? the input/output data of the port can be specified in 1-bit units. specified by port register 3 (p3) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 3 (pm3) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 3 (pmc3) ? control mode can be specified in 1-bit units. specified by port function control register 3 (p fc3) and port function control expansion register 3l (pfce3l) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 3 (pu3) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 3 (intf3) and external interrupt rising edge specification register 3 (intr3) port 3 functions alternately as the following pins. table 4-14 alternate-function pins of port 3 pin name alternate-function pin name i/o remark block type p30 txda0 e-2 p31 rxda0/intp7 l-2 p32 ascka0/tip00/top00/top01 u-13 p33 tip01/top01/ctxd0 u-3 p34 tip10/top10/crxd0 u-2 p35 tip11/top11 g-1 p36 ctxd1 e-2 p37 crxd1 e-1 p38 txda2 e-2 port 3 p39 rxda2/intp8 i/o l-2 caution: the p31 to p35, p37, p39 pins have hysteresis character istics in the input mode of the alternate function, but do not have hyst eresis characteristics in the port mode. chapter 4 port functions user?s manual u17830ee1v0um00 207 (2) registers (a) port register 3 (p3) port register 3 (p3) is a 16-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p3 register are used as the p3h register, and th e lower 8 bits as the p3l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff406h, fffff407h (i) v850es/fe2 15 14 13 12 11 10 9 8 p3 (p3h note ) 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 (p3l) 0 0 p35 p34 p33 p32 p31 p30 (ii) v850es/ff2 15 14 13 12 11 10 9 8 p3 (p3h note ) 0 0 0 0 0 0 p39 p38 7 6 5 4 3 2 1 0 (p3l) 0 0 p35 p34 p33 p32 p31 p30 (iii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 p3 (p3h note ) 0 0 0 0 0 0 p39 p38 7 6 5 4 3 2 1 0 (p3l) p37 p36 p35 p34 p33 p32 p31 p30 p3n control of output data (in output mode) (n = 0 to 9) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of t he p3 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the p3h register. note that the v850es/fe2 is not provided with a p3h register. therefore, the p3 register can be used only as the p3l register in the v850es/fe2. chapter 4 port functions user?s manual u17830ee1v0um00 208 (b) port mode register 3 (pm3) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pm3 regi ster are used as the pm3h register, and the lower 8 bits as the pm3l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffffh r/w address: fffff426h, fffff427h (i) v850es/fe2 15 14 13 12 11 10 9 8 pm3 (pm3h note ) 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 (pm3l) 1 1 pm35 pm34 pm33 pm32 pm31 pm30 (ii) v850es/ff2 15 14 13 12 11 10 9 8 pm3 (pm3h note ) 1 1 1 1 1 1 pm39 pm38 7 6 5 4 3 2 1 0 (pm3l) 1 1 pm35 pm34 pm33 pm32 pm31 pm30 (iii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 pm3 (pm3h note ) 1 1 1 1 1 1 pm39 pm38 7 6 5 4 3 2 1 0 (pm3l) pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n control of i/o mode (n = 0 to 9) 0 output mode 1 input mode note to read or write bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. note that the v 850es/fe2 is not provided with a pm3h register. therefore, the pm3 register can be used only as the pm3l register in the v850es/fe2. chapter 4 port functions user?s manual u17830ee1v0um00 209 (c) port mode control register 3 (pmc3) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmc3 r egister are used as the pmc3h regi ster, and the lower 8 bits as the pmc3l register, however, these registers can be read or written in 8-bit or 1-bit units. (1/2) after reset: 0000h r/w address: fffff446h, fffff447h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 pmc3 (pmc3h note 1 ) 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 (pmc3l) 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 pmc3 (pmc3h note 1 ) 0 0 0 0 0 0 pmc39 pmc38 7 6 5 4 3 2 1 0 (pmc3l) pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pmc39 specification of operation mode of p39 pin 0 i/o port 1 rxda2/intp8 input note 2 pmc38 specification of operation mode of p38 pin 0 i/o port 1 txda2 output notes 1. to read or write bits 8 to 15 of the pmc3 regist er in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. note that the v850es/fe2, v850es/ff2 are not provided with a pmc3h register. therefore, the pmc3 register can be used only as the pmc3l register in the v850es/fe2, v850es/ff2. 2. the intp8 pin functions alternately as the rxda 2 pin. to use as the rxda2 pin, invalidate the edge detection function of the alternate-f unction intp8 pin (by fixing the intf39 bit of the intf3 register to 0 and the intr39 bit of the intr3 register to 0). to use as the intp8 pin, stop the reception operation of uarta2 (by clearing the ua2rxe bit of the ua2ctl0 register to 0). chapter 4 port functions user?s manual u17830ee1v0um00 210 (2/2) pmc37 specification of operation mode of p37 pin 0 i/o port 1 crxd1 input pmc36 specification of operation mode of p36 pin 0 i/o port 1 ctxd1 output pmc35 specification of operation mode of p35 pin 0 i/o port 1 tip11/top11 i/o pmc34 specification of operation mode of p34 pin 0 i/o port 1 tip10/top10/crxd0 i/o pmc33 specification of operation mode of p33 pin 0 i/o port 1 tip01/top01/ctxd0 i/o pmc32 specification of operation mode of p32 pin 0 i/o port 1 ascka0/tip00/top00/top01 i/o pmc31 specification of operation mode of p31 pin 0 i/o port 1 rxda0/intp7 input note pmc30 specification of operation mode of p30 pin 0 i/o port 1 txda0 output note the intp7 pin functions alternately as the rxda0 pin. to use as the rxda0 pin, invalidate the edge detection function of the alternate-functi on intp7 pin (by fixing the intf31 bit of the intf3 register to 0 and the intr31 bit of the intr 3 register to 0). to use as the intp7 pin, stop the reception operation of uarta0 (by clear ing the ua0rxe bit of the ua0ctl0 register to 0). chapter 4 port functions user?s manual u17830ee1v0um00 211 (d) port function control register 3l (pfc3l) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff466h 7 6 5 4 3 2 1 0 pfc3l 0 0 pfc35 pfc34 pfc33 pfc32 0 0 remark for how to specify a control mode, refer to 4.3.4 (2) (f) setting of control mode of p3 pin . (e) port function control expa nsion register 3l (pfce3l) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff706h 7 6 5 4 3 2 1 0 pfce3l 0 0 0 pfce34 pfce33 pfce32 0 0 remark for how to specify a control mode, refer to 4.3.4 (2) (f) setting of control mode of p3 pin . (f) setting of control mode of p3 pin pfc35 specification of control mode of p35 pin 0 tip11 input 1 top11 output pfce34 pfc34 specification of control mode of p34 pin 0 0 tip10 input 0 1 top10 output 1 0 crxd0 input 1 1 setting prohibited chapter 4 port functions user?s manual u17830ee1v0um00 212 pfce33 pfc33 specification of control mode of p33 pin 0 0 tip01 input 0 1 top01 output 1 0 ctxd0 output 1 1 setting prohibited pfce32 pfc32 specification of control mode of p32 pin 0 0 ascka0 input 0 1 top01 output 1 0 tip00 input 1 1 top00 output chapter 4 port functions user?s manual u17830ee1v0um00 213 (g) pull-up resistor option register 3 (pu3) this is a 16-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 16- or 1-bit units. if the higher 8 bits of the pu3 regi ster are used as the pu3h register, and the lower 8 bits as the pu3l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc46h, fffffc47h (i) v850es/fe2 15 14 13 12 11 10 9 8 pu3 (pu3h note ) 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 (pu3l) 0 0 pu35 pu34 pu33 pu32 pu31 pu30 (ii) v850es/ff2 15 14 13 12 11 10 9 8 pu3 (pu3h note ) 0 0 0 0 0 0 pu39 pu38 7 6 5 4 3 2 1 0 (pu3l) 0 0 pu35 pu34 pu33 pu32 pu31 pu30 (iii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 pu3 (pu3h note ) 0 0 0 0 0 0 pu39 pu38 7 6 5 4 3 2 1 0 (pu3l) pu37 pu36 pu35 pu34 pu33 pu32 pu31 pu30 pu3n control of on-chip pull-up resistor connection (n = 0 to 9) 0 not connected 1 connected note to read/write bits 8 to 15 of the pu3 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the pu3h register. note that the v850es/fe2 is not provided with a pu3h register. therefore, the pu3 register can be used only as the pu3l register in the v850es/fe2. chapter 4 port functions user?s manual u17830ee1v0um00 214 (h) external interrupt falling edge specification register 3 (intf3) this is a 16-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 16-bit units. if the higher 8 bits of the intf3 register are used as the intf3h register, and the lower 8 bits as the intf3l register, however, these registers can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf3n and intr3n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc06h, fffffc07h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 intf3 (intf3h note ) 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 (intf3l) 0 0 0 0 0 0 intf31 0 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 intf3 (intf3h note ) 0 0 0 0 0 0 intf39 0 7 6 5 4 3 2 1 0 (intf3l) 0 0 0 0 0 0 intf31 0 note to read/write bits 8 to 15 of the in tf3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the intf3h register. note that the v 850es/fe2, v850es/ff2 is not provided with an intf3h register. therefore, the intf3 register can be used only as the intf3l register in the v850es/fe2, v850es/fe2. remark refer to table 4-15 for how to specify a valid edge. chapter 4 port functions user?s manual u17830ee1v0um00 215 (i) external interrupt rising edge specification register 3 (intr3) this is a 16-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 16-bit units. if the higher 8 bits of the intr3 register are used as the intr3h register, and the lower 8 bits as the intr3l register, however, these registers can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf3n and intr3n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc26h, fffffc27h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 intr3 (intr3h note ) 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 (intr3l) 0 0 0 0 0 0 intr31 0 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 intr3 (intr3h note ) 0 0 0 0 0 0 intr39 0 7 6 5 4 3 2 1 0 (intr3l) 0 0 0 0 0 0 intr31 0 note to read/write bits 8 to 15 of the intr3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the intr3h register. note that the v850es/fe2, v850es/ff2 is not provided with an intr3h register. therefore, the intr3 register can be used only as the intr3l register in the v850es/fe2, v850es/ff2. remark refer to 4-15 for how to specify a valid edge. table 4-15 valid edge specification intf3n bit intr3n bit valid edge specification (n = 1, 9) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 1: control of intp7 pin n = 9: control of intp8 pin chapter 4 port functions user?s manual u17830ee1v0um00 216 4.3.4 port 4 port 4 is a 3-bit port (p40 to p42) for whic h i/o settings can be controlled in 1-bit units. the number of i/o port pins is the same for all products. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 v850es/fj2 3-bit i/o port (p40 to p42) (1) functions of port 4 ? the input/output data of the port can be specified in 1-bit units. specified by port register 4 (p4) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 4 (pm4) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 4 (pmc4) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 4 (pu4) port 4 functions alternately as the following pins. table 4-16 alternate-function pins of port 4 pin name alternate-function pin name i/o remark block type p40 sib0 e-1 p41 sob0 e-2 port 4 p42 sckb0 i/o ? e-3 caution: the p40 to p42 pins h ave hysteresis characteristics in th e input mode of the alternate function, but do not have hysteresis characteristics in the port mode. chapter 4 port functions user?s manual u17830ee1v0um00 217 (2) registers (a) port register 4 (p4) port register 4 (p4) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff408h 7 6 5 4 3 2 1 0 p4 0 0 0 0 0 p42 p41 p40 p4n control of output data (in output mode) (n = 0 to 2) 0 output 0. 1 output 1. (b) port mode register 4 (pm4) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff428h 7 6 5 4 3 2 1 0 pm4 1 1 1 1 1 pm42 pm41 pm40 pm4n control of input/output mode (n = 0 to 2) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 218 (c) port mode control register 4 (pmc4) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff448h 7 6 5 4 3 2 1 0 pmc4 0 0 0 0 0 pmc42 pmc41 pmc40 pmc42 specification of operation mode of p42 pin 0 i/o port 1 sckb0 input/output pmc41 specification of operation mode of p41 pin 0 i/o port 1 sob0 output pmc40 specification of operation mode of p40 pin 0 i/o port 1 sib0 input (d) pull-up resistor option register 4 (pu4) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc48h 7 6 5 4 3 2 1 0 pu4 0 0 0 0 0 pu42 pu41 pu40 pu4n control of on-chip pull-up resistor connection (n = 0 to 2) 0 not connected 1 connected chapter 4 port functions user?s manual u17830ee1v0um00 219 4.3.5 port 5 port 5 is a 6-bit port (p50 to p55) for whic h i/o settings can be controlled in 1-bit units. the number of i/o port pins is the same for all products. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 v850es/fj2 6-bit i/o port (p50 to p55) (1) functions of port 5 ? the input/output data of the port can be specified in 1-bit units. specified by port register 5 (p5) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 5 (pm5) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 5 (pmc5) ? control mode can be specified in 1-bit units. specified by port function control register 5 (pfc5) or port function control expansion register 5 (pfce5) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 5 (pu5) port 5 functions alternately as the following pins. chapter 4 port functions user?s manual u17830ee1v0um00 220 table 4-17 alternate-function pins of port 5 pin name alternate-function pin name i/o remark block type p50 kr0/tiq01/toq01 u-4 p51 kr1/tiq02/toq02 u-4 p52 kr2/tiq03/toq03/ddi note u-5 p53 kr3/tiq00/toq00/ddo note u-6 p54 kr4/dck note g-2 port 5 p55 kr5/dms note i/o ? g-2 caution: the p50 to p55 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis char acteristics in the port mode. note the ddi, ddo, dck, and dms pins are for the on-ch ip debug function. to use the ddi, ddo, dck, and dms pins as port pins, not as on-chip debug pins, the following actions must be taken. <1> clear the ocdm0 bit of the ocdm register (special register) to 0. <2> fix the p05/intp2/drst pin to the low level until the above action has been taken. when the on-chip debug function is not used, inputting a high level to the drst pin before the above actions are taken may cause a malfunction (cpu deadlo ck). exercise utmost care in handling the p05 pin. when a high level is not input to the p05/intp2/drst pi n (when this pin is fixed to low level), it is not necessary to manipulate the ocdm0 bit of the ocdm register. because a pull-down resistor (30 k ? typ) is connected to the buffer of the p05/intp2/drst pin, the pin does not have to be fixed to the low level by an external source. the pull-down resistor is disconnected by clearing the ocdm0 bit to 0. chapter 4 port functions user?s manual u17830ee1v0um00 221 (2) registers (a) port register 5 (p5) port register 5 (p5) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff40ah 7 6 5 4 3 2 1 0 p5 0 0 p55 p54 p53 p52 p51 p50 p5n control of output data (in output mode) (n = 0 to 5) 0 output 0. 1 output 1. (b) port mode register 5 (pm5) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff42ah 7 6 5 4 3 2 1 0 pm5 1 1 pm55 pm54 pm53 pm52 pm51 pm50 pm5n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 222 (c) port mode control register 5 (pmc5) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. caution if the control mode is specified by using the pmc5 regi ster when the pfc5n bit of the pfc5 register and the pfce5n bit of the pfce5 register ar e the default values (0), the output becomes undefined. for this reason, first set the pfc5n bit of the pfc5 register and the pfce5n bit of the pfce5 register, and then set the pmc5 n bit to 1 to set the control mode. after reset: 00h r/w address: fffff44ah 7 6 5 4 3 2 1 0 pmc5 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 pmc55 specification of operation mode of p55 pin 0 i/o port 1 kr5 input pmc54 specification of operation mode of p54 pin 0 i/o port 1 kr4 input pmc53 specification of operation mode of p53 pin 0 i/o port 1 kr3/tiq00/toq00 i/o pmc52 specification of operation mode of p52 pin 0 i/o port 1 kr2/tiq03/toq03 i/o pmc51 specification of operation mode of p51 pin 0 i/o port 1 kr1/tiq02/toq02 i/o pmc50 specification of operation mode of p50 pin 0 i/o port 1 kr0/tiq01/toq01 i/o chapter 4 port functions user?s manual u17830ee1v0um00 223 (d) port function control register 5 (pfc5) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff46ah 7 6 5 4 3 2 1 0 pfc5 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 remark for how to specify a control mode, refer to 4.3.6 (2) (f) setting of control mode of p5 pin . (e) port function control ex pansion register 5 (pfce5) this is an 8-bit register that specifie s control mode 1, 2, 3, or 4. it c an be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff70ah 7 6 5 4 3 2 1 0 pfce5 0 0 0 0 pfce53 pfce52 pfce51 pfce50 remark for how to specify a control mode, refer to 4.3.6 (2) (f) setting of control mode of p5 pin . (f) setting of control mode of p5 pin caution if the control mode is specified by using the pmc5 regi ster when the pfc5n bit of the pfc5 register and pfce5n bit of the pfce5 re gister are the default values (0), the output becomes undefined. for this reason, first set the pfc5n bit of the pfc5 register and the pfce5n bit of the pfce5 register, and then set the pmc5 n bit to 1 to set the control mode. pfc55 specification of control mode of p55 pin 0 setting prohibited 1 kr5 input pfc54 specification of control mode of p54 pin 0 setting prohibited 1 kr4 input chapter 4 port functions user?s manual u17830ee1v0um00 224 pfce53 pfc53 specification of control mode of p53 pin 0 0 setting prohibited 0 1 tiq00/kr3 note input 1 0 toq00 output 1 1 setting prohibited pfce52 pfc52 specification of control mode of p52 pin 0 0 setting prohibited 0 1 tiq03/kr2 note input 1 0 toq03 output 1 1 setting prohibited pfce51 pfc51 specification of control mode of p51 pin 0 0 setting prohibited 0 1 tiq02/kr1 note input 1 0 toq02 output 1 1 setting prohibited pfce50 pfc50 specification of control mode of p50 pin 0 0 setting prohibited 0 1 tiq01/kr0 note input 1 0 toq01 output 1 1 setting prohibited note the krn pin functions alternately as the tiq0m pin. to use this pin as the tiq0m pin, invalidate the key return detection function of the alternate-function kr n pin (by clearing the krmn bit of the krm register to 0). to use this pin as the krn pin, invalidat e the edge detection function of the alternate-function tiq0m pin (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm0 bit of krm register = 0 tq0tig2, tq0tig3 bit of tq0ioc1 register = 0 kr1/tiq02 krm1 bit of krm register = 0 tq0tig4, tq0tig5 bit of tq0ioc1 register = 0 kr2/tiq03 krm2 bit of krm register = 0 tq0tig6, tq0tig7 bit of tq0ioc1 register = 0 kr3/tiq00 krm3 bit of krm register = 0 tq0tig0, tq0tig1 bit of tq0ioc1 register = 0 tq0ees0, tq0ees1 bit of tq0ioc2 register = 0 tq0ets0, tq0ets1 bit of tq0ioc2 register = 0 chapter 4 port functions user?s manual u17830ee1v0um00 225 (g) pull-up resistor option register 5 (pu5) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc4ah 7 6 5 4 3 2 1 0 pu5 0 0 pu55 pu54 pu53 pu52 pu51 pu50 pu5n control of on-chip pull-up resistor connection (n = 0 to 5) 0 not connected 1 connected chapter 4 port functions user?s manual u17830ee1v0um00 226 4.3.6 port 6 port 6 is a 16-bit port (p60 to p615) for which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 - v850es/fj2 16-bit i/o port (p60 to p615) note note in the pd70f3237, the alternate functions of the p65 to p68 pins (ctxd2, crxd2, ctxd3, crxd3) are not available. (1) functions of port 6 ? the input/output data of the port can be specified in 1-bit units. specified by port register 6 (p6) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 6 (pm6) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 6 (pmc6) ? control mode 1 or control mode 2 can be specified in 1-bit units. specified by port function control register 6 (pfc6) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 6 (pu6) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificati on register 6l (intf6l) and external interrupt rising edge specification regi ster 6l (intr6l) port 6 functions alternately as the following pins. chapter 4 port functions user?s manual u17830ee1v0um00 227 table 4-18 alternate-function pins of port 6 pin name alternate-function pin name i/o remark block type p60 intp11 n-2 p61 intp12 n-2 p62 intp13 n-2 p63 ? c-1 p64 ? c-1 p65 ctxd2 g-3 p66 crxd2 g-4 p67 ctxd3 g-3 p68 crxd3 g-4 p69 ? c-1 p610 tiq20/toq20 g-1 p611 tiq21/toq21 g-1 p612 tiq22/toq22 g-1 p613 tiq23/toq23 g-1 p614 ? c-1 port 6 p615 ? i/o ? c-1 caution: the p60 to p62, p66, p68, p610 to p613 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (p66 and p68 only pd70f3238, pd70f3239 chapter 4 port functions user?s manual u17830ee1v0um00 228 (2) registers (a) port register 6 (p6) port register 6 (p6) is a 16-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p6 register are used as the p6h register, and th e lower 8 bits as the p6l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff40ch, fffff40dh (i) v850es/fj2 15 14 13 12 11 10 9 8 p6 (p6h note ) p615 p614 p613 p612 p611 p610 p69 p68 7 6 5 4 3 2 1 0 (p6l) p67 p66 p65 p64 p63 p62 p61 p60 p6n control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of t he p6 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the p6h register. chapter 4 port functions user?s manual u17830ee1v0um00 229 (b) port mode register 6 (pm6) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pm6 regi ster are used as the pm6h register, and the lower 8 bits as the pm6l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff42ch, fffff42dh (i) v850es/fj2 15 14 13 12 11 10 9 8 pm6 (pm6h note ) pm615 pm614 pm613 pm612 pm611 pm610 pm69 pm68 7 6 5 4 3 2 1 0 (pm6l) pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pm6n control of i/o mode (n = 0 to 15) 0 output mode 1 input mode note to read or write bits 8 to 15 of the pm6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm6h register. chapter 4 port functions user?s manual u17830ee1v0um00 230 (c) port mode control register 6 (pmc6) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmc6 r egister are used as the pmc6h regi ster, and the lower 8 bits as the pmc6l register, however, these registers can be read or written in 8-bit or 1-bit units. caution if the control mode is specified by using the pmc6 regi ster when the pfc6n bit of the pfc6 register is the default value (0), the output becomes undefined (n = 0 to 8). for this reason, first set the pfc6n bit of th e pfc6 register to 1, and then set the pmc6n bit to 1 to set the control mode. (1/2) after reset: 0000h r/w address: fffff44ch, fffff44dh (i) v850es/fj2 ( pd70f3237) 15 14 13 12 11 10 9 8 pmc6 (pmc6h note ) 0 0 pmc613 pmc612 pmc611 pmc610 0 0 7 6 5 4 3 2 1 0 (pmc6l) 0 0 0 0 0 pmc62 pmc61 pmc60 (ii) v850es/fj2 ( pd70f3238, pd70f3239) 15 14 13 12 11 10 9 8 pmc6 (pmc6h note ) 0 0 pmc613 pmc612 pmc611 pmc610 0 pmc68 7 6 5 4 3 2 1 0 (pmc6l) pmc67 pmc66 pmc65 0 0 pmc62 pmc61 pmc60 pmc613 specification of operation mode of p613 pin 0 i/o port 1 tiq23/toq23 i/o pmc612 specification of operation mode of p612 pin 0 i/o port 1 tiq22/toq22 i/o pmc611 specification of operation mode of p611 pin 0 i/o port 1 tiq21/toq21 i/o note to read or write bits 8 to 15 of the pmc6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc6h register. chapter 4 port functions user?s manual u17830ee1v0um00 231 (2/2) pmc610 specification of operation mode of p610 pin 0 i/o port 1 tiq20/toq20 i/o pmc68 specification of operation mode of p68 pin 0 i/o port 1 crxd3 input pmc67 specification of operation mode of p67 pin 0 i/o port 1 ctxd3 output pmc66 specification of operation mode of p66 pin 0 i/o port 1 crxd2 input pmc65 specification of operation mode of p65 pin 0 i/o port 1 ctxd2 output pmc62 specification of operation mode of p62 pin 0 i/o port 1 intp13 input pmc61 specification of operation mode of p61 pin 0 i/o port 1 intp12 input pmc60 specification of operation mode of p60 pin 0 i/o port 1 intp11 input chapter 4 port functions user?s manual u17830ee1v0um00 232 (d) port function control register 6 (pfc6) this is a 16-bit register that specifies control mode 1 or 2. it can be read or written in 16-bit units. if the higher 8 bits of the pfc6 regi ster are used as the pfc6h register, and the lower 8 bits as the pfc6l register, however, these registers can be read or written in 8-bit or 1-bit units. caution if the control mode is specified by using the pmc6 regi ster when the pfc6n bit of the pfc6 register is the default value (0), the output becomes undefined (n = 0 to 8). for this reason, first set the pfc6n bit of th e pfc6 register to 1, and then set the pmc6n bit to 1 to set the control mode. (1/2) after reset: 0000h r/w address: fffff46ch, fffff46dh (i) v850es/fj2 ( pd70f3237) 15 14 13 12 11 10 9 8 pfc6 (pfc6h note ) 0 0 pfc613 pfc612 pfc611 pfc610 0 0 7 6 5 4 3 2 1 0 (pfc6l) 0 0 0 0 0 pfc62 pfc61 pfc60 (ii) v850es/fj2 ( pd70f3238, pd70f3239) 15 14 13 12 11 10 9 8 pfc6 (pfc6h note ) 0 0 pfc613 pfc612 pfc611 pfc610 0 pfc68 7 6 5 4 3 2 1 0 (pfc6l) pfc67 pfc66 pfc65 0 0 pfc62 pfc61 pfc60 pfc613 specification of control mode of p613 pin 0 tiq23 input 1 toq23 output pfc612 specification of control mode of p612 pin 0 tiq22 input 1 toq22 output pfc611 specification of control mode of p611 pin 0 tiq21 input 1 toq21 output note to read or write bits 8 to 15 of the pfc6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc6h register. chapter 4 port functions user?s manual u17830ee1v0um00 233 (2/2) pfc610 specification of control mode of p610 pin 0 tiq20 input 1 toq20 output pfc68 specification of control mode of p68 pin 0 setting prohibited 1 crxd3 input pfc67 specification of control mode of p67 pin 0 setting prohibited 1 ctxd3 output pfc66 specification of control mode of p66 pin 0 setting prohibited 1 crxd2 input pfc65 specification of control mode of p65 pin 0 setting prohibited 1 ctxd2 output pfc62 specification of control mode of p62 pin 0 setting prohibited 1 intp13 input pfc61 specification of control mode of p61 pin 0 setting prohibited 1 intp12 input pfc60 specification of control mode of p60 pin 0 setting prohibited 1 intp11 input chapter 4 port functions user?s manual u17830ee1v0um00 234 (e) pull-up resistor option register 6 (pu6) this is a 16-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 16-bit units. if the higher 8 bits of the pu6 regi ster are used as the pu6h register, and the lower 8 bits as the pu6l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffffc4ch, fffffc4dh (i) v850es/fj2 15 14 13 12 11 10 9 8 pu6 (pu6h note ) pu615 pu614 pu613 pu612 pu611 pu610 pu69 pu68 7 6 5 4 3 2 1 0 (pu6l) pu67 pu66 pu65 pu64 pu63 pu62 pu61 pu60 pu6n control of on-chip pull-up resistor connection (n = 0 to 15) 0 not connected 1 connected note to read/write bits 8 to 15 of the pu6 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the pu6h register. (f) external interrupt falling edge specification register 6l (intf6l) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf6n and intr6n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc0ch (i) v850es/fj2 7 6 5 4 3 2 1 0 intf6l 0 0 0 0 0 intf62 intf61 intf60 remark refer to table 4-19 for how to specify a valid edge. chapter 4 port functions user?s manual u17830ee1v0um00 235 (g) external interrupt rising edge specification register 6l (intr6l) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf6n and intr6n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc2ch (i) v850es/fj2 7 6 5 4 3 2 1 0 intr6l 0 0 0 0 0 intr62 intr61 intr60 remark refer to table 4-19 for how to specify a valid edge. table 4-19 valid edge specification intf6n bit intr6n bit valid edge specification (n = 0 to 2) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of intp11 pin n = 1: control of intp12 pin n = 2: control of intp13 pin chapter 4 port functions user?s manual u17830ee1v0um00 236 4.3.7 port 7 port 7 is a 10-bit, 12-bit or16-bit port (p70 to p715) for which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 10-bit i/o port (p70 to p79) v850es/ff2 12-bit i/o port (p70 to p711) v850es/fg2 v850es/fj2 16-bit i/o port (p70 to p715) (1) functions of port 7 ? the input/output data of the port can be specified in 1-bit units. specified by port register 7 (p7) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 7l, h p7l, p h port 7 functions alternately as the following pins. table 4-20 alternate-function pins of port 7 pin name alternate-function pin name i/o remark block type p70 ani0 a-1 p71 ani1 a-1 p72 ani2 a-1 p73 ani3 a-1 p74 ani4 a-1 p75 ani5 a-1 p76 ani6 a-1 p77 ani7 a-1 p78 ani8 a-1 p79 ani9 a-1 p710 ani10 a-1 p711 ani11 a-1 p712 ani12 a-1 p713 ani13 a-1 p714 ani14 a-1 port 7 p715 ani15 i/o ? a-1 chapter 4 port functions user?s manual u17830ee1v0um00 237 (2) registers (a) port register 7h, port register 7l (p7h, p7l) port registers 7h and 7l (p7h and p7l) are 8-bit regist ers that control reading t he pin level and writing the output level. these registers can be read or written in 8-bit or 1-bit units. they cannot be accessed in 16-bit units. after reset: undefined r/w address: fffff40fh, fffff40eh (i) v850es/fe2 7 6 5 4 3 2 1 0 p7h 0 0 0 0 0 0 p79 p78 7 6 5 4 3 2 1 0 p7l p77 p76 p75 p74 p73 p72 p71 p70 (ii) v850es/ff2 7 6 5 4 3 2 1 0 p7h 0 0 0 0 p711 p710 p79 p78 7 6 5 4 3 2 1 0 p7l p77 p76 p75 p74 p73 p72 p71 p70 (iii) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 p7h p715 p714 p713 p712 p711 p710 p79 p78 7 6 5 4 3 2 1 0 p7l p77 p76 p75 p74 p73 p72 p71 p70 p7n control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. caution do not read the p7h and p7 l registers during a/d conversion. chapter 4 port functions user?s manual u17830ee1v0um00 238 (b) port mode registers 7h, 7l (pm7h, pm7l) these are 8-bit registers that specify an input or output mode. they c an be read or written in 8-bit or 1-bit units. these registers cannot be accessed in 16-bit units. after reset: ffh r/w address: fffff42fh, fffff42eh (i) v850es/fe2 7 6 5 4 3 2 1 0 pm7h 0 0 0 0 0 0 pm79 pm78 7 6 5 4 3 2 1 0 pm7l pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 (ii) v850es/ff2 7 6 5 4 3 2 1 0 pm7h 0 0 0 0 pm711 pm710 pm79 pm78 7 6 5 4 3 2 1 0 pm7l pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 (iii) v850es/fg2, v850es/fj2 7 6 5 4 3 2 1 0 pm7h pm715 pm714 pm713 pm712 pm711 pm710 pm79 pm78 7 6 5 4 3 2 1 0 pm7l pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7n control of i/o mode (n = 0 to 15) 0 output mode 1 input mode caution to use the alternate functi on of p7n (anin), set pm7n to 1. chapter 4 port functions user?s manual u17830ee1v0um00 239 4.3.8 port 8 port 8 is a 2-bit port (p80, p81) for which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 - v850es/fj2 2-bit i/o port (p80, p81) note note in the pd70f3237, the alternate functions of the p80 and p81 pins (rxda3 and txda3) are not available. the alternate function of the p80 pin in the pd70f3237 is intp14 only. (1) functions of port 8 o the input/output data of the port can be specified in 1-bit units. specified by port register 8 (p8) o the input/output mode of the port can be specified in 1-bit units. specified by port mode register 8 (pm8) o port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 8 (pmc8) o an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 8 (pu8) o the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificatio n register 8 (intf8) and external interrupt rising edge specification register 8 (intr8) port 8 functions alternately as the following pins. table 4-21 alternate-function pins of port 8 pin name alternate-function pin name i/o remark block type p80 rxda3/intp14 l-1 note port 8 p81 txda3 i/o ? c-1 note note in the pd70f3237, the alternate functions of the p80 and p81 pins (rxda3 and txda3) are not available. moreover, the port type becomes p80: l-1 and p81: c-1. caution: the p80 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteris tics in the port mode. chapter 4 port functions user?s manual u17830ee1v0um00 240 (2) registers (a) port register 8 (p8) port register 8 (p8) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff410h (i) v850es/fj2 7 6 5 4 3 2 1 0 p8 0 0 0 0 0 0 p81 p80 p8n control of output data (in output mode) (n = 0, 1) 0 output 0. 1 output 1. (b) port mode register 8 (pm8) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff430h (i) v850es/fj2 7 6 5 4 3 2 1 0 pm8 1 1 1 1 1 1 pm81 pm80 pm8n control of i/o mode (n = 0, 1) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 241 (c) port mode control register 8 (pmc8) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff450h (i) v850es/fj2 ( pd70f3237) 7 6 5 4 3 2 1 0 pmc8 0 0 0 0 0 0 0 pmc80 (ii) v850es/fj2 ( pd70f3238, pd70f3239) 7 6 5 4 3 2 1 0 pmc8 0 0 0 0 0 0 pmc81 pmc80 pmc81 specification of operation mode of p81 pin 0 i/o port 1 txda3 output pmc80 specification of operation mode of p80 pin 0 i/o port 1 rxda3/intp14 input note note the pd70f3237 does not have rxda3. the intp14 pin of the pd70f3238, pd70f3239 functions alternately as the rxda3 pin. to use this pin as the rxda3 pin, invalidate the edge detection function of the alternate-function intp14 pin (by clearing the intf80 bit of the in tf8 register to 0 and the intr80 bit of the intr8 register to 0). to use this pin as the intp14 pin, stop the recept ion operation of uarta3 (by clearing the ua3rxe bit of the ua3ctl0 register to 0). chapter 4 port functions user?s manual u17830ee1v0um00 242 (d) pull-up resistor option register 8 (pu8) this is an 8-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffffc50h (i) v850es/fj2 7 6 5 4 3 2 1 0 pu8 0 0 0 0 0 0 pu81 pu80 pu8n control of on-chip pull-up resistor connection (n = 0, 1) 0 not connected 1 connected (e) external interrupt falling edge specification register 8 (intf8) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf80 and intr80 bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address fffffc10h (i) v850es/fj2 7 6 5 4 3 2 1 0 intf8 0 0 0 0 0 0 0 intf80 remark refer to table 4-22 or how to specify a valid edge. chapter 4 port functions user?s manual u17830ee1v0um00 243 (f) external interrupt rising edge specification register 8 (intr8) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf80 and intr80 bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address fffffc30h (i) v850es/fj2 7 6 5 4 3 2 1 0 intr8 0 0 0 0 0 0 0 intr80 remark refer to table 4-22 for how to specify a valid edge. table 4-22 valid edge specification intf80 bit intr80 bit valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark control of intp14 pin chapter 4 port functions user?s manual u17830ee1v0um00 244 4.3.9 port 9 port 9 is a 9-bit or 16-bit port (p90 to p915) fo r which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 v850es/ff2 9-bit i/o port (p90, p91, p96 to p99, p913 to p915) v850es/fg2 v850es/fj2 16-bit i/o port (p90 to p915) note note in the v850es/fg2, the alternate func tions of the p910 to p912 pins (sib2, sob2, sckb2) are not available. (1) functions of port 9 ? the input/output data of the port can be specified in 1-bit units. specified by port register 9 (p9) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 9 (pm9) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register 9 (pmc9) ? control mode can be specified in 1-bit units. specified by port function control register 9 (pfc9) and port function control expansion register 9 (pfce9) ? an on-chip pull-up resistor can be connected in 1-bit units. specified by pull-up resistor option register 9 (pu9) ? the valid edge of the external interrupt (alter nate function) can be specified in 1-bit units. specified by external interrupt falling edge specificati on register 9h (intf9h) and external interrupt rising edge specification regi ster 9h (intr9h) port 9 functions alternately as the following pins. chapter 4 port functions user?s manual u17830ee1v0um00 245 table 4-23 alternate-function pins of port 9 pin name alternate-function pin name i/o remark block type p90 kr6/txda1 u-12 p91 kr7/rxda1 u-7 p92 tiq11/toq11 u-11 p93 tiq12/toq12 u-11 p94 tiq13/toq13 u-11 p95 tiq10/toq10 u-11 p96 tip21/top21 u-9 p97 sib1/tip20/top20 u-8 p98 sob1 g-3 p99 sckb1 g-5 p910 sib2 g-4 p911 sob2 g-3 p912 sckb2 g-5 p913 intp4/pcl w-1 p914 intp5 n-2 port 9 p915 intp6 i/o ? n-2 caution the p90 to p97, p910, p912 to p915 pins have hyster esis characteristics in the input mode of the alternate function, but do not have hyst eresis characteristics in the port mode. chapter 4 port functions user?s manual u17830ee1v0um00 246 (2) registers (a) port register 9 (p9) port register 9 (p9) is a 16-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p9 register are used as the p9h register, and th e lower 8 bits as the p9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff412h, fffff413h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 p9 (p9h note ) p915 p914 p913 0 0 0 p99 p98 7 6 5 4 3 2 1 0 (p9l) p97 p96 0 0 0 0 p91 p90 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 p9 (p9h note ) p915 p914 p913 p912 p911 p910 p99 p98 7 6 5 4 3 2 1 0 (p9l) p97 p96 p95 p94 p93 p92 p91 p90 p9n control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of t he p9 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the p9h register. chapter 4 port functions user?s manual u17830ee1v0um00 247 (b) port mode register 9 (pm9) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pm9 regi ster are used as the pm9h register, and the lower 8 bits as the pm9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffffh r/w address: fffff432h, fffff433h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 pm9 (pm9h note ) pm915 pm914 pm913 1 1 1 pm99 pm98 7 6 5 4 3 2 1 0 (pm9l) pm97 pm96 1 1 1 1 pm91 pm90 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 pm9 (pm9h note ) pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 7 6 5 4 3 2 1 0 (pm9l) pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n control of i/o mode (n = 0 to 15) 0 output mode 1 input mode note to read or write bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. chapter 4 port functions user?s manual u17830ee1v0um00 248 (c) port mode control register 9 (pmc9) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmc9 r egister are used as the pmc9h regi ster, and the lower 8 bits as the pmc9l register, however, these registers can be read or written in 8-bit or 1-bit units. caution if the control mode is specified by using the pmc9 regi ster when the pfc9n bit of the pfc9 register and the pfce9n bit of the pfce9 register ar e the default values (0), the output becomes undefined. for this reason, first set the pfc9n bit of the pfc9 register and the pfce9n bit of the pfce9 register to 1, and then set the pmc9n bit to 1 to set the control mode. (1/3) after reset: 0000h r/w address: fffff452h, fffff453h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 pmc9 (pmc9h note ) pmc915 pmc914 pmc913 0 0 0 pmc99 pmc98 7 6 5 4 3 2 1 0 (pmc9l) pmc97 pmc96 0 0 0 0 pmc91 pmc90 (ii) v850es/fg2 15 14 13 12 11 10 9 8 pmc9 (pmc9h note ) pmc915 pmc914 pmc913 0 0 0 pmc99 pmc98 7 6 5 4 3 2 1 0 (pmc9l) pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 (iii) v850es/fj2 15 14 13 12 11 10 9 8 pmc9 (pmc9h note ) pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 7 6 5 4 3 2 1 0 (pmc9l) pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 specification of operation mode of p915 pin 0 i/o port 1 intp6 input pmc914 specification of operation mode of p914 pin 0 i/o port 1 intp5 input note to read or write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. chapter 4 port functions user?s manual u17830ee1v0um00 249 (2/3) pmc913 specification of operation mode of p913 pin 0 i/o port 1 intp4/pcl i/o pmc912 specification of operation mode of p912 pin 0 i/o port 1 sckb2 i/o pmc911 specification of operation mode of p911 pin 0 i/o port 1 sob2 output pmc910 specification of operation mode of p910 pin 0 i/o port 1 sib2 input pmc99 specification of operation mode of p99 pin 0 i/o port 1 sckb1 i/o pmc98 specification of operation mode of p98 pin 0 i/o port 1 sob1 output pmc97 specification of operation mode of p97 pin 0 i/o port 1 sib1/tip20/top20 i/o pmc96 specification of operation mode of p96 pin 0 i/o port 1 tip21/top21 i/o pmc95 specification of operation mode of p95 pin 0 i/o port 1 tiq10/toq10 i/o pmc94 specification of operation mode of p94 pin 0 i/o port 1 tiq13/toq13 i/o chapter 4 port functions user?s manual u17830ee1v0um00 250 (3/3) pmc93 specification of operation mode of p93 pin 0 i/o port 1 tiq12/toq12 i/o pmc92 specification of operation mode of p92 pin 0 i/o port 1 tiq11/toq11 i/o pmc91 specification of operation mode of p91 pin 0 i/o port 1 kr7/rxda1 input pmc90 specification of operation mode of p90 pin 0 i/o port 1 kr6/txda1 i/o chapter 4 port functions user?s manual u17830ee1v0um00 251 (d) port function control register 9 (pfc9) this is a 16-bit register that specif ies control mode 1, 2, 3, or 4. it can be read or written in 16-bit units. if the higher 8 bits of the pfc9 regi ster are used as the pfc9h register, and the lower 8 bits as the pfc9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffff472h, fffff473h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 pfc9 (pfc9h note ) pfc915 pfc914 pfc913 0 0 0 pfc99 pfc98 7 6 5 4 3 2 1 0 (pfc9l) pfc97 pfc96 0 0 0 0 pfc91 pfc90 (ii) v850es/fg2 15 14 13 12 11 10 9 8 pfc9 (pfc9h note ) pfc915 pfc914 pfc913 0 0 0 pfc99 pfc98 7 6 5 4 3 2 1 0 (pfc9l) pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 (iii) v850es/fj2 15 14 13 12 11 10 9 8 pfc9 (pfc9h note ) pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 7 6 5 4 3 2 1 0 (pfc9l) pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 note to read or write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. remark for how to specify a control mode, refer to 4.3.10 (2) (f) setting of control mode of p9 pin . chapter 4 port functions user?s manual u17830ee1v0um00 252 (e) port function control ex pansion register 9 (pfce9) this is a 16-bit register that specif ies control mode 1, 2, 3, or 4. it can be read or written in 16-bit units. if the higher 8 bits of the pfc9 regi ster are used as the pfc9h register, and the lower 8 bits as the pfc9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffff712h, fffff713h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 pfce9 (pfce9h note ) 0 0 pfce913 0 0 0 0 0 7 6 5 4 3 2 1 0 (pfce9l) pfce97 pfce96 0 0 0 0 pfce91 pfce90 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 pfce9 (pfce9h note ) 0 0 pfce913 0 0 0 0 0 7 6 5 4 3 2 1 0 (pfce9l) pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 note to read or write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfce9h register. remark for how to specify a control mode, refer to 4.3.10 (2) (f) setting of control mode of p9 pin . (f) setting of control mode of p9 pin caution if the control mode is specified by using the pfc9 regi ster when the pfc9n bit of the pfc9 register and pfce9n bit of the pfce9 re gister are the default values (0), the output becomes undefined. for this reason, first set the pfc9n bit of the pfc9 register and the pfce9n bit of the pfce9 register, and then set the pmc9 n bit to 1 to set the control mode. pfc915 specification of control mode of p915 pin 0 setting prohibited 1 intp6 input pfc914 specification of control mode of p914 pin 0 setting prohibited 1 intp5 input chapter 4 port functions user?s manual u17830ee1v0um00 253 pfce913 pfc913 specification of control mode of p913 pin 0 0 setting prohibited 0 1 intp4 input 1 0 pcl output 1 1 setting prohibited pfc912 specification of control mode of p912 pin 0 setting prohibited 1 sckb2 i/o pfc911 specification of control mode of p911 pin 0 setting prohibited 1 sob2 output pfc910 specification of control mode of p910 pin 0 setting prohibited 1 sib2 input pfc99 specification of control mode of p99 pin 0 setting prohibited 1 sckb1 i/o pfc98 specification of control mode of p98 pin 0 setting prohibited 1 sob1 input pfce97 pfc97 specification of control mode of p97 pin 0 0 setting prohibited 0 1 sib1 input 1 0 tip20 input 1 1 top20 output pfce96 pfc96 specification of control mode of p96 pin 0 0 setting prohibited 0 1 setting prohibited 1 0 tip21 input 1 1 top21 output chapter 4 port functions user?s manual u17830ee1v0um00 254 pfce95 pfc95 specification of control mode of p95 pin 0 0 setting prohibited 0 1 tiq10 input 1 0 toq10 output 1 1 setting prohibited pfce94 pfc94 specification of control mode of p94 pin 0 0 setting prohibited 0 1 tiq13 input 1 0 toq13 output 1 1 setting prohibited pfce93 pfc93 specification of control mode of p93 pin 0 0 setting prohibited 0 1 tiq12 input 1 0 toq12 output 1 1 setting prohibited pfce92 pfc92 specification of control mode of p92 pin 0 0 setting prohibited 0 1 tiq11 input 1 0 toq11 output 1 1 setting prohibited pfce91 pfc91 specification of control mode of p91 pin 0 0 setting prohibited 0 1 kr7 input 1 0 rxda1 input 1 1 setting prohibited pfce90 pfc90 specification of control mode of p90 pin 0 0 setting prohibited 0 1 kr6 input 1 0 txda1 output 1 1 setting prohibited note kr7 and rxda1 pins are using combined. invalidate the key return detection of kr7 pins when y ou use the pins as an rxda1pin ("0" is set to the krm7 bit of the krm register). moreover, it is recommended to set it to pfc91 bit = 1, pfce91 bit =0 when using it as kr7 pin. chapter 4 port functions user?s manual u17830ee1v0um00 255 (g) pull-up resistor option register 9 (pu9) this is a 16-bit register that specif ies connection of an on-chip pull-up resist or. it can be read or written in 16-bit units. if the higher 8 bits of the pu9 regi ster are used as the pu9h register, and the lower 8 bits as the pu9l register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffffc52h, fffffc53h (i) v850es/fe2, v850es/ff2 15 14 13 12 11 10 9 8 pu9 (pu9h note ) pu915 pu914 pu913 0 0 0 pu99 pu98 7 6 5 4 3 2 1 0 (pu9l) pu97 pu96 0 0 0 0 pu91 pu90 (ii) v850es/fg2, v850es/fj2 15 14 13 12 11 10 9 8 pu9 (pu9h note ) pu915 pu914 pu913 pu912 pu911 pu910 pu99 pu98 7 6 5 4 3 2 1 0 (pu9l) pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 pu9n control of on-chip pull-up resistor connection (n = 0 to 15) 0 not connected 1 connected note to read/write bits 8 to 15 of the pu9 register in 8-bit or 1-bit units , specify these bits as bits 0 to 7 of the pu9h register. chapter 4 port functions user?s manual u17830ee1v0um00 256 (h) external interrupt falling edge specification register 9h (intf9h) this is an 8-bit register that specifies detection of th e falling edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf9n and intr9n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc13h 7 6 5 4 3 2 1 0 intf9h intf915 intf914 intf913 0 0 0 0 0 remark refer to table 4-24 or how to specify a valid edge. (i) external interrupt rising edge specification register 9h (intr9h) this is an 8-bit register that specif ies detection of the rising edge of the external interrupt pin. it can be read or written in 8-bit or 1-bit units. cautions 1. when the external interrupt function (alternate function) is switched to the port function, an edge may be detected. set the port mode after clearing the intf9n and intr9n bits to 0. 2. an analog-delay-based noise eliminator is connected to the exte rnal interrupt input pin. after reset: 00h r/w address: fffffc33h 7 6 5 4 3 2 1 0 intr9h intr915 intr914 intr913 0 0 0 0 0 remark refer to table 4-24 or how to specify a valid edge. table 4-24 valid edge specification intf9n bit intr9n bit valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13: control of intp4 pin n = 14: control of intp5 pin n = 15: control of intp6 pin chapter 4 port functions user?s manual u17830ee1v0um00 257 4.3.10 port 12 port 12 is an 8-bit port (p120 to p127) for which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 - v850es/fj2 8-bit i/o port (p120 to p127) (1) functions of port 12 ? the input/output data of the port can be specified in 1-bit units. specified by port register 12 (p12) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register 12 (pm12) port 12 functions alternately as the following pins. table 4-25 alternate-function pins of port 12 pin name alternate-function pin name i/o remark block type p120 ani16 a-1 p121 ani17 a-1 p122 ani18 a-1 p123 ani19 a-1 p124 ani20 a-1 p125 ani21 a-1 p126 ani22 a-1 port 12 p127 ani23 i/o ? a-1 chapter 4 port functions user?s manual u17830ee1v0um00 258 (2) registers (a) port register 12 (p12) port register 12 (p12) is an 8-bit r egister that controls reading the pi n level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff418h (i) v850es/fj2 7 6 5 4 3 2 1 0 p12 p127 p126 p125 p124 p123 p122 p121 p120 p12n control of output data (in output mode) (n = 0 to 7) 0 output 0. 1 output 1. (b) port mode register 12 (pm12) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff438h (i) v850es/fj2 7 6 5 4 3 2 1 0 pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 pm12n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode caution to use the alternate function of p12n (anin), set pm12n to 1. chapter 4 port functions user?s manual u17830ee1v0um00 259 4.3.11 port cd port cd is a 4-bit port (pcd0 to pcd3) for wh ich i/o settings can be cont rolled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 v850es/ff2 v850es/fg2 - v850es/fj2 4-bit i/o port (pcd0 to pcd3) (1) functions of port cd ? the input/output data of the port can be specified in 1-bit units. specified by port register cd (pcd) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register cd (pmcd) port cd functions alternately as the following pins. table 4-26. alternate-function pins of port cd pin name alternate-function pin name i/o remark block type pcd0 ? b-1 pcd1 ? b-1 pcd2 ? b-1 port cd pcd3 ? i/o ? b-1 chapter 4 port functions user?s manual u17830ee1v0um00 260 (2) registers (a) port register cd (pcd) port register cd (pcd) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff00eh (i) v850es/fj2 7 6 5 4 3 2 1 0 pcd 0 0 0 0 pcd3 pcd2 pcd1 pcd0 pcdn control of output data (in output mode) (n = 0 to 3) 0 output 0. 1 output 1. (b) port mode register cd (pmcd) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff02eh (i) v850es/fj2 7 6 5 4 3 2 1 0 pmcd 1 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 pmcdn control of i/o mode (n = 0 to 3) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 261 4.3.12 port cm port cm is a 2-bit, 4-bit, or 6-bit port (pcm0 to pcm5 ) for which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 2-bit i/o port (pcm0, pcm1) note 1 v850es/ff2 v850es/fg2 4-bit i/o port (pcm0 to pcm3) note 2 v850es/fj2 4-bit i/o port (pcd0 to pcd3) notes 1. in the v850es/fe2, the alternate function of the pcm0 pin (wait) is not available. 2. in the v850es/ff2 and v850es/fg2, the alternate functions of the pcm0, pcm2, and pcm3 pins. (wait, hldak, hldrq) are not available. (1) functions of port cm ? the input/output data of the port can be specified in 1-bit units. specified by port register cm (pcm) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register cm (pmcm) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register cm (pmccm) port cm functions alternately as the following pins. table 4-27 alternate-function pins of port cm pin name alternate-function pin name i/o remark block type pcm0 wait d-1 pcm1 clkout d-2 pcm2 hldak d-2 pcm3 cldrq d-1 pcm4 ? b-1 port cm pcm5 ? i/o ? b-1 chapter 4 port functions user?s manual u17830ee1v0um00 262 (2) registers (a) port register cm (pcm) port register cm (pcm) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff00ch (i) v850es/fe2 7 6 5 4 3 2 1 0 pcm 0 0 0 0 0 0 pcm1 pcm0 (ii) v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pcm 0 0 0 0 pcm3 pcm2 pcm1 pcm0 (iii) v850es/fj2 7 6 5 4 3 2 1 0 pcm 0 0 pcm5 pcm4 pcm3 pcm2 pcm1 pcm0 pcmn control of output data (in output mode) (n = 0 to 5) 0 output 0. 1 output 1. chapter 4 port functions user?s manual u17830ee1v0um00 263 (b) port mode register cm (pmcm) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff02ch (i) v850es/fe2 7 6 5 4 3 2 1 0 pmcm 1 1 1 1 1 1 pmcm1 pmcm0 (ii) v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pmcm 1 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 (iii) v850es/fj2 7 6 5 4 3 2 1 0 pmcm 1 1 pmcm5 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 pmcmn control of i/o mode (n = 0 to 5) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 264 (c) port mode control register cm (pmccm) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff04ch (i) v850es/fe2, v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pmccm 0 0 0 0 0 0 pmccm1 0 (ii) v850es/fj2 7 6 5 4 3 2 1 0 pmccm 0 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 pmccm3 specification of operation mode of pcm3 pin 0 i/o port 1 hldrq input pmccm2 specification of operation mode of pcm2 pin 0 i/o port 1 hldak output pmccm1 specification of operation mode of pcm1 pin 0 i/o port 1 clkout output pmccm0 specification of operation mode of pcm0 pin 0 i/o port 1 wait input chapter 4 port functions user?s manual u17830ee1v0um00 265 4.3.13 port cs port cs is a 2-bit or 8-bit port (pcs0 to pcs7) or which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 - v850es/ff2 v850es/fg2 2-bit i/o port (pcs0, pcs1) note v850es/fj2 8-bit i/o port (pcs0 to pcs7) note in the v850es/ff2 and v850es/fg2, the alternate functi ons of the pcs0 and pcs1 pins (cs0, cs1) are not available. (1) functions of port cs ? the input/output data of the port can be specified in 1-bit units. specified by port register cs (pcs) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register cs (pmcs) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register cs (pmccs) port cs functions alternately as the following pins. table 4-28 alternate-function pins of port cs pin name alternate-function pin name i/o remark block type pcs0 cs0 d-2 pcs1 cs1 d-2 pcs2 cs2 d-2 pcs3 cs3 d-2 pcs4 ? b-1 pcs5 ? b-1 pcs6 ? b-1 port cs pcs7 ? i/o ? b-1 chapter 4 port functions user?s manual u17830ee1v0um00 266 (2) registers (a) port register cs (pcs) port register cs (pcs) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff008h (i) v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pcs 0 0 0 0 0 0 pcs1 pcs0 (ii) v850es/fj2 7 6 5 4 3 2 1 0 pcs pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 pcsn control of output data (in output mode) (n = 0 to 7) 0 output 0. 1 output 1. chapter 4 port functions user?s manual u17830ee1v0um00 267 (b) port mode register cs (pmcs) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff028h (i) v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pmcs 1 1 1 1 1 1 pmcs1 pmcs0 (ii) v850es/fj2 7 6 5 4 3 2 1 0 pmcs pmcs7 pmcs6 pmcs5 pmcs4 pmcs3 pmcs2 pmcs1 pmcs0 pmcsn control of i/o mode (n = 0 to 7) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 268 (c) port mode control register cs (pmccs) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff048h (i) v850es/fj2 7 6 5 4 3 2 1 0 pmccs 0 0 0 0 pmccs3 pmccs2 pmccs1 pmccs0 pmccs3 specification of operation mode of pcs3 pin 0 i/o port 1 cs3 output pmccs2 specification of operation mode of pcs2 pin 0 i/o port 1 cs2 output pmccs1 specification of operation mode of pcs1 pin 0 i/o port 1 cs1 output pmccs0 specification of operation mode of pcs0 pin 0 i/o port 1 cs0 output chapter 4 port functions user?s manual u17830ee1v0um00 269 4.3.14 port ct port ct is a 4-bit or 8-bit port (pct0 to pct7) or which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 - v850es/ff2 v850es/fg2 4-bit i/o port (pct0, pct1, pct4, pct6) note v850es/fj2 8-bit i/o port (pct0 to pct7) note in the v850es/ff2 and v850es/fg2, the alternate f unctions of the pct0, pct1, pct4, and pct6 pins (wr0, wr1, rd, astb) are not available. (1) functions of port ct ? the input/output data of the port can be specified in 1-bit units. specified by port register ct (pct) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register ct (pmct) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode c ontrol register ct (pmcct) port ct functions alternately as the following pins. table 4-29 alternate-function pins of port ct pin name alternate-function pin name i/o remark block type pct0 wr0 d-2 pct1 wr1 d-2 pct2 ? b-1 pct3 ? b-1 pct4 rd d-2 pct5 ? b-1 pct6 astb d-2 port ct pct7 ? i/o ? b-1 chapter 4 port functions user?s manual u17830ee1v0um00 270 (2) registers (a) port register ct (pct) port register ct (pct) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff00ah (i) v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pct 0 pct6 0 pct4 0 0 pct1 pct0 (ii) v850es/fj2 7 6 5 4 3 2 1 0 pct pct7 pct6 pct5 pct4 pct3 pct2 pct1 pct0 pctn control of output data (in output mode) (n = 0 to 7) 0 output 0. 1 output 1. chapter 4 port functions user?s manual u17830ee1v0um00 271 (b) port mode register ct (pmct) this is an 8-bit register that specif ies the input or output mode. it can be read or written in 8-bit or 1-bit units. after reset: ffh r/w address: fffff02ah (i) v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 pmct 1 pmct6 1 pmct4 1 1 pmct1 pmct0 (ii) v850es/fj2 7 6 5 4 3 2 1 0 pmct pmct7 pmct6 pmct5 pmct 4 pmct3 pmct2 pmct1 pmct0 pmctn control of i/o mode (n = 0 to 7) 0 output mode 1 input mode chapter 4 port functions user?s manual u17830ee1v0um00 272 (c) port mode control register ct (pmcct) this is an 8-bit register that specif ies the port mode or control mode. it can be read or written in 8-bit or 1- bit units. after reset: 00h r/w address: fffff04ah (i) v850es/fj2 7 6 5 4 3 2 1 0 pmcct 0 pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 pmcct6 specification of operation mode of pct3 pin 0 i/o port 1 astb output pmcct4 specification of operation mode of pct2 pin 0 i/o port 1 rd output pmcct1 specification of operation mode of pct1 pin 0 i/o port 1 wr1 output pmcct0 specification of operation mode of pct0 pin 0 i/o port 1 wr0 output chapter 4 port functions user?s manual u17830ee1v0um00 273 4.3.15 port dl port dl is an 8-bit, 12-bit, 14-bit, or 16-bit port (pdl0 to pdl15) or which i/o settings can be controlled in 1-bit units. the number of i/o port pins di ffers depending on the product. product number of i/o port pins v850es/fe2 8-bit i/o port (pdl0 to pdl7) note v850es/ff2 12-bit i/o port (pdl0 to pdl11) note v850es/fg2 14-bit i/o port (pdl0 to pdl13) note v850es/fj2 16-bit i/o port (pdl0 to pdl15) note in the v850es/fe2, v850es/ff2, and v850es/fg2, the alternate functi on of the pdln pin (adn) is not available. the alternate function of the pdl5 pi n in the v850es/fe2, v850es/ff2, and v850es/fg2 is flmd1 only. (1) function of port dl ? the input/output data of the port can be specified in 1-bit units. specified by port register dl (pdl) ? the input/output mode of the port can be specified in 1-bit units. specified by port mode register dl (pmdl) ? port mode or control mode (alternate function) can be specified in 1-bit units. specified by port mode control register dl (pmcdl) chapter 4 port functions user?s manual u17830ee1v0um00 274 port dl functions alternately as the following pins. table 4-30 alternate-function pins of port dl pin name alternate-function pin name i/o remark block type pdl0 ad0 d-3 pdl1 ad1 d-3 pdl2 ad2 d-3 pdl3 ad3 d-3 pdl4 ad4 d-3 pdl5 ad5/flmd1 note d-3 pdl6 ad6 d-3 pdl7 ad7 d-3 pdl8 ad8 d-3 pdl9 ad9 d-3 pdl10 ad10 d-3 pdl11 ad11 d-3 pdl12 ad12 d-3 pdl13 ad13 d-3 pdl14 ad14 d-3 port dl pdl15 ad15 i/o ? d-3 note because the flmd1 pin is used in the flash progra mming mode, it does not have to be manipulated by using a port control register. for details, refer to chapter 25 flash memory . chapter 4 port functions user?s manual u17830ee1v0um00 275 (2) registers (a) port register dl (pdl) port register dl (pdl) is a 16-bit re gister that controls reading the pin level and writing the output level. this register can be read or written in 16-bit units. if the higher 8 bits of the pdl regi ster are used as the pdlh register , and the lower 8 bits as the pdll register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: undefined r/w address: fffff004h, fffff005h (i) v850es/fe2 7 6 5 4 3 2 1 0 pdl pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 (ii) v850es/ff2 15 14 13 12 11 10 9 8 pdl (pdlh note ) 0 0 0 0 pdl11 pdl10 pdl9 pdl8 7 6 5 4 3 2 1 0 (pdll) pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 (iii) v850es/fg2 15 14 13 12 11 10 9 8 pdl (pdlh note ) 0 0 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 7 6 5 4 3 2 1 0 (pdll) pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 (iv) v850es/fj2 15 14 13 12 11 10 9 8 pdl (pdlh note ) pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 7 6 5 4 3 2 1 0 (pdll) pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdln control of output data (in output mode) (n = 0 to 15) 0 output 0. 1 output 1. note to read or write bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pdlh register. chapter 4 port functions user?s manual u17830ee1v0um00 276 (b) port mode register dl (pmdl) this is a 16-bit register that specifies the input or output mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmdl r egister are used as the pmdlh register, and the lower 8 bits as the pmdll register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: ffffh r/w address: fffff024h, fffff025h (i) v850es/fe2 7 6 5 4 3 2 1 0 pmdl pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 (ii) v850es/ff2 15 14 13 12 11 10 9 8 pmdl (pmdlh note ) 1 1 1 1 pmdl11 pmdl10 pmdl9 pmdl8 7 6 5 4 3 2 1 0 (pmdll) pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 (iii) v850es/fg2 15 14 13 12 11 10 9 8 pmdl (pmdlh note ) 1 1 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 7 6 5 4 3 2 1 0 (pmdll) pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 (iv) v850es/fj2 15 14 13 12 11 10 9 8 pmdl (pmdlh note ) pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 7 6 5 4 3 2 1 0 (pmdll) pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdln control of i/o mode (n = 0 to 15) 0 output mode 1 input mode note to read or write bits 8 to 15 of t he pmdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmdlh register. chapter 4 port functions user?s manual u17830ee1v0um00 277 (c) port mode control register dl (pmcdl) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written in 16-bit units. if the higher 8 bits of the pmcdl r egister are used as the pmcdlh regi ster, and the lower 8 bits as the pmcdll register, however, these registers can be read or written in 8-bit or 1-bit units. after reset: 0000h r/w address: fffff044h, fffff045h (i) v850es/fj2 15 14 13 12 11 10 9 8 pmcdl (pmcdlh note ) pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 7 6 5 4 3 2 1 0 (pmcdll) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 pmcdln specification of operation mode of pdl15 pin (n = 0 to 15) 0 i/o port 1 adn i/o (address/data bus i/o) note to read or write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmcdlh register. chapter 4 port functions user?s manual u17830ee1v0um00 278 4.3.16 port pins that function alternately as on-chip debug function the pins shown in table 4-31 function alternately as on -chip debug pins. after an external reset, these pins are initialized as on-chip debug pins (drst, ddi, ddo, dck, and dms). table 4-31 on-chip debug pins pin name alternate function pin p05 intp2/drst p52 kr2/tiq03/toq03/ddi p53 kr3/tiq00/toq00/ddo p54 kr4/dck p55 kr5/dms to use these pins as port pins, not as on-chip debug pi ns, the following actions must be taken after an external reset. <1> clear the ocdm0 bit of the ocdm register (special register) to 0. <2> fix the p05/intp2/drst pin to the low le vel until the above action has been taken. when the on-chip debug function is not used, inputting a high level to the drst pin before the above actions are taken may cause a malfunction (cpu deadlock). exercise utmost care in handling the p05 pin. when a high level is not input to the p05 /intp2/drst pin (when this pin is fixed to low level), it is not necessary to manipulate the ocdm0 bit of the ocdm register. because a pull-down resistor (30 k ? typ) is connected to the buffer of the p05/intp2/drst pin, the pin does not have to be fixed to the low level by an external source. the pull-down resistor is disc onnected by clearing the ocdm0 bit to 0. for details, refer to chapter 27 on-chip debug function (on-chip debug unit) . chapter 4 port functions user?s manual u17830ee1v0um00 279 4.3.17 register settings to use port pins as alternate-function pins table 4-32 register settings to use port pins as alternate-function pins (1/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) tip31 input setting not required pmc00 = 1 pfc00 = 0 ? p00 top31 output setting not required pmc00 = 1 pfc00 = 1 ? tip30 input setting not required pmc01 = 1 pfc01 = 0 ? p01 top30 output setting not required pmc01 = 1 pfc01 = 1 ? p02 nmi input setting not required pmc02 = 1 ? ? intp0 input setting not required pmc03 = 1 pfc03 = 0 ? intx03 (intx0) p03 adtrg output setting not required pmc03 = 1 pfc03 = 1 ? p04 intp1 input setting not required pmc04 = 1 ? ? intx04 (intx0) intp2 input setting not required pmc05 = 1 ? ? intx05 (intx0) p05 note drst input setting not required setting not required ? ? ocdm0 (ocdm) = 1 p06 intp3 input setting not required pmc06 = 1 ? ? intx06 (intx0) p10 intp9 input setting not required pmc10 = 1 ? ? intx10 (intx1) p11 intp10 input setting not required pmc11 = 1 ? ? intx11 (intx1) note after an external reset, the p05/intp2/drst pin is initia lized as an on-chip debug pin (drst). to not use the p05/intp2/drst pin as an on-chip debug pin, refer to chapter 27 on-chip debug function (on- chip debug unit) . remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions user?s manual u17830ee1v0um00 280 table 4-32 register settings to use port pins as alternate-function pins (2/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) p30 txda0 output setting not required pmc30 = 1 ? ? rxda0 input setting not required pmc31 = 1 ? ? note 1 p31 intp7 input setting not required pmc31 = 1 ? ? note 1 , intx31 (intx3) ascka0 input setting not required pmc32 = 1 pfc32 = 0 pfce32 = 0 top01 output setting not required pmc32 = 1 pfc32 = 1 pfce32 = 0 tip00 input setting not required pmc32 = 1 pfc32 = 0 pfce32 = 1 p32 top00 output setting not required pmc32 = 1 pfc32 = 1 pfce32 = 1 tip01 input setting not required pmc33 = 1 pfc33 = 0 pfce33 = 0 top01 output setting not required pmc33 = 1 pfc33 = 1 pfce33 = 0 p33 ctxd0 output setting not required pmc33 = 1 pfc33 = 0 pfce33 = 1 tip10 input setting not required pmc34 = 1 pfc34 = 0 pfce34 = 0 top10 output setting not required pmc34 = 1 pfc34 = 1 pfce34 = 0 p34 crxd0 input setting not required pmc34 = 1 pfc34 = 0 pfce34 = 1 tip11 input setting not required pmc35 = 1 pfc35 = 0 ? p35 top11 output setting not required pmc35 = 1 pfc35 = 1 ? p36 ctxd1 output setting not required pmc36 = 1 ? ? p37 crxd1 input setting not required pmc37 = 1 ? ? p38 txda2 output setting not required pmc38 = 1 ? ? rxda2 input setting not required pmc39 = 1 ? ? note 2 p39 intp8 input setting not required pmc39 = 1 ? ? note 2 , intx39 (intx3) p40 sib0 input setting not required pmc40 = 1 ? ? p41 sob0 output setting not required pmc41 = 1 ? ? p42 sckb0 i/o setting not required pmc42 = 1 ? ? notes 1. the intp7 pin functions alternately as the rxda0 pin. to use this pin as the rxda0 pin, invalidate the edge detection function of the alternate-function intp7 pin (by clearing the intf31 bit of the intf3 register to 0 and the intr31 bit of the intr3 register to 0). to use this pin as the in tp7 pin, stop the reception operation of uarta0 (by clearing the ua0rxe bit of the ua0ctl0 register to 0). 2. the intp8 pin functions alternately as the rxda2 pin. to use this pin as the rxda2 pin, invalidate the edge detection function of the alternate-function intp8 pin (by clearing the intf39 bit of the intf3 register to 0 and the intr39 bit of the intr3 register to 0). to use this pin as the in tp8 pin, stop the reception operation of uarta2 (by clearing the ua2rxe bit of the ua2ctl0 register to 0). remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions user?s manual u17830ee1v0um00 281 table 4-32 register settings to use port pins as alternate-function pins (3/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) kr0 input setting not required pmc50 = 1 pfc50 = 1 pfce50 = 0 note 1 tiq01 input setting not required pmc50 = 1 pfc50 = 1 pfce50 = 0 note 1 p50 toq01 output setting not required pmc50 = 1 pfc50 = 0 pfce50 = 1 kr1 input setting not required pmc51 = 1 pfc51 = 1 pfce54 = 0 note 1 tiq02 input setting not required pmc51 = 1 pfc51 = 1 pfce51 = 0 note 1 p51 toq02 output setting not required pmc51 = 1 pfc51 = 0 pfce51 = 1 kr2 input setting not required pmc52 = 1 pfc52 = 1 pfce52 = 0 note 1 tiq03 input setting not required pmc52 = 1 pfc52 = 1 pfce52 = 0 note 1 toq03 output setting not required pmc52 = 1 pfc52 = 0 pfce52 = 1 p52 ddi note 2 input setting not required setting not required setting not required setting not required ocdm0 (ocdm) = 1 kr3 input setting not required pmc53 = 1 pfc53 = 1 pfce53 = 0 note 1 tiq00 input setting not required pmc53 = 1 pfc53 = 1 pfce53 = 0 note 1 toq00 output setting not required pmc53 = 1 pfc53 = 0 pfce53 = 1 p53 ddo note 2 output setting not required setting not required setting not required setting not required ocdm0 (ocdm) = 1 kr4 input setting not required pmc54 = 1 pfc54 = 1 ? p54 dck note 2 output setting not required setting not required setting not required ? ocdm0 (ocdm) = 1 kr5 input setting not required pmc55 = 1 pfc55 = 1 ? p55 dms note 2 output setting not required setting not required setting not required ? ocdm0 (ocdm) = 1 notes 1. the krn pin functions alternately as the tiq0m pin. to use this pin as the tiq0m pin, invalidate the key return detection function of the alternate-function krn pin (by clearing the krmn bit of the krm register to 0). to use this pin as the krn pin, invalidate the ed ge detection function of the alternate-function tiq0m pin (n = 0 to 3, m = 0 to 3). pin name when used as tiq0m pin when used as krn pin kr0/tiq01 krm0 bit of krm register = 0 tq0t ig2, tq0tig3 bits of tq0ioc1 register = 0 kr1/tiq02 krm1 bit of krm register = 0 tq0t ig4, tq0tig5 bits of tq0ioc1 register = 0 kr2/tiq03 krm2 bit of krm register = 0 tq0t ig6, tq0tig7 bits of tq0ioc1 register = 0 kr3/tiq00 krm3 bit of krm register = 0 tq0tig0, tq0tig1 bits of tq0ioc1 register = 0 tq0ees0, tq0ees1 bits of tq0ioc2 register = 0 tq0ets0, tq0ets1 bits of tq0ioc2 register = 0 2. the ddi, ddo, dck, and dms pins are on-chip debug pins . to not use these pins as on-chip debug pins after an external reset, refer to chapter 27 on-chip debug function (on-chip debug unit) . caution if the control mode is specifi ed by using the pmc5 re gister when the pfc5n bi t of the pfc5 register and the pfce5n bit of the pfce5 register are th e default values (0), the output becomes undefined. for this reason, first set the pfc5n bit of the pfc5 register and the pf ce5n bit of the pfce5 register, and then set the pmc5n bit to 1 to set the control mode. remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions user?s manual u17830ee1v0um00 282 table 4-32 register settings to use port pins as alternate-function pins (4/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) p60 intp11 input setting not required pmc60 = 1 pfc60 = 1 ? intx60 (intx6l) p61 intp12 input setting not required pmc61 = 1 pfc61 = 1 ? intx61 (intx6l) p62 intp13 input setting not required pmc62 = 1 pfc62 = 1 ? intx62 (intx6l) p65 ctxd2 output setting not required pmc65 = 1 pfc65 = 1 ? p66 crxd2 input setting not required pmc66 = 1 pfc66 = 1 ? p67 ctxd3 output setting not required pmc67 = 1 pfc67 = 1 ? p68 crxd3 input setting not required pmc68 = 1 pfc68 = 1 ? tiq20 input setting not required pmc610 = 1 pfc610 = 0 ? p610 toq20 output setting not required pmc610 = 1 pfc610 = 1 ? tiq21 input setting not required pmc611 = 1 pfc611 = 0 ? p611 toq21 output setting not required pmc611 = 1 pfc611 = 1 ? tiq22 input setting not required pmc612 = 1 pfc612 = 0 ? p612 toq22 output setting not required pmc612 = 1 pfc612 = 1 ? tiq23 input setting not required pmc613 = 1 pfc613 = 0 ? p613 toq23 output setting not required pmc613 = 1 pfc613 = 1 ? p70 ani0 input pm70 = 1 note ? ? ? p71 ani1 input pm71 = 1 note ? ? ? p72 ani2 input pm72 = 1 note ? ? ? p73 ani3 input pm73 = 1 note ? ? ? p74 ani4 input pm74 = 1 note ? ? ? p75 ani5 input pm75 = 1 note ? ? ? p76 ani6 input pm76 = 1 note ? ? ? p77 ani7 input pm77 = 1 note ? ? ? p78 ani8 input pm78 = 1 note ? ? ?? p79 ani9 input pm79 = 1 note ? ? ? p710 ani10 input pm710 = 1 note ? ? ? p711 ani11 input pm711 = 1 note ? ? ? p712 ani12 input pm712 = 1 note ? ? ? p713 ani13 input pm713 = 1 note ? ? ? p714 ani14 input pm714 = 1 note ? ? ? p715 ani15 input pm715 = 1 note ? ? ? note set pm7n to 1 to use the alternate function of p7n (anin). caution if the control mode is specifi ed by using the pmc6 register when the pfc6n bit (n = 0 to 8) of the pfc6 register is the default valu e (0), the output becomes undefined. for this reason, first set the pfc6n bit of the pfc6 register and then set th e pmc6n bit to 1 to set the control mode. remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn chapter 4 port functions user?s manual u17830ee1v0um00 283 table 4-32 register settings to use port pin as alternate-function pins (5/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) rxda3 input setting not required pmc80 = 1 ? ? note 2 p80 intp14 input setting not required pmc80 = 1 ? ? note, intx80 (intx8) p81 txda3 output setting not required pmc81 = 1 ? ? kr6 input setting not required pmc90 = 1 pfc90 = 1 pfce90 = 0 p90 txda1 output setting not required pmc90 = 1 pfc90 = 0 pfce90 = 1 pfc91 = 1 pfce91 = 0 kr7 note 1 input setting not required pmc91 = 1 pfc91 = 0 pfce91 = 1 p91 rxda1 input setting not required pmc91 = 1 pfc91 = 0 pfce91 = 1 tiq11 input setting not required pmc92 = 1 pfc92 = 1 pfce92 = 0 p92 toq11 output setting not required pmc92 = 1 pfc92 = 0 pfce92 = 1 tiq12 input setting not required pmc93 = 1 pfc93 = 1 pfce93 = 0 p93 toq12 output setting not required pmc93 = 1 pfc93 = 0 pfce93 = 1 tiq13 input setting not required pmc94 = 1 pfc94 = 1 pfce94 = 0 p94 toq13 output setting not required pmc94 = 1 pfc94 = 0 pfce94 = 1 tiq10 input setting not required pmc95 = 1 pfc95 = 1 pfce95 = 0 p95 toq10 output setting not required pmc95 = 1 pfc95 = 0 pfce95 = 1 tip21 input setting not required pmc96 = 1 pfc96 = 0 pfce96 = 1 p96 top21 output setting not required pmc96 = 1 pfc96 = 1 pfce96 = 1 sib1 input setting not required pmc97 = 1 pfc97 = 1 pfce97 = 0 tip20 input setting not required pmc97 = 1 pfc97 = 0 pfce97 = 1 p97 top20 output setting not required pmc97 = 1 pfc97 = 1 pfce97 = 1 p98 sob1 output setting not required pmc98 = 1 pfc98 = 1 ? p99 sckb1 i/o setting not required pmc99 = 1 pfc99 = 1 ? p910 sib2 input setting not required pmc910 = 1 pfc910 = 1 ? p911 sob2 output setting not required pmc911 = 1 pfc911 = 1 ? p912 sckb2 i/o setting not required pmc912 = 1 pfc912 = 1 ? intp4 input setting not required pmc913 = 1 pfc913 = 1 pfce913 = 0 intx913 (intx9h) p913 pcl output setting not required pmc913 = 1 pfc913 = 0 pfce913 = 1 p914 intp5 input setting not required pmc914 = 1 pfc914 = 1 ? intx914 (intx9h) p915 intp6 input setting not required pmc915 = 1 pfc915 = 1 ? intx915 (intx9h) note 1. the kr7 pin and the rxda1 pin are using combined. in validate the key return detection of the kr7 pin when you use the terminal as the rxda1 pin ("0" is set to the krm7 bit of the krm register.). moreover, it is recommended to set it to pfc91 bit = 1, pfce91 bit =0 when using it as the kr7 pin. 2 the intp14 pin functions alternately as the rxda3 pin. to use this pin as the rxda3 pin, invalidate the edge detection function of the alternate- function intp14 pin (by clearing the in tf80 bit of the intf8 register to 0 and the intr80 bit of the intr8 register to 0). to use this pin as the intp14 pin, stop the reception operation of uarta3 (by clearing the ua3rxe bit of the ua3ctl0 register to 0). caution if the control mode is specifi ed by using the pmc9 re gister when the pfc9n bi t of the pfc9 register and the pfce9n bit of the pfce9 register are th e default values (0), the output becomes undefined. for this reason, first set the pfc9n bit of the pfc9 register and the pf ce9n bit of the pfce9 register, and then set the pmc9n bit to 1 to set the control mode. chapter 4 port functions user?s manual u17830ee1v0um00 284 remarks 1. the port register (pn) does not have to be set when the alternate function is used. 2. intxn = intfn, intrn table 4-32 register settings to use port pins as alternate-function pins (6/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) p120 ani16 input pm120 = 1 note ? ? ? p121 ani17 input pm121 = 1 note ? ? ? p122 ani18 input pm122 = 1 note ? ? ? p123 ani19 input pm123 = 1 note ? ? ? p124 ani20 input pm124 = 1 note ? ? ? p125 ani21 input pm125 = 1 note ? ? ? p126 ani22 input pm126 = 1 note ? ? ? p127 ani23 input pm127 = 1 note ? ? ? pcm0 wait input setting not required pmccm0 = 1 ? ? pcm1 clkout output setting not required pmccm1 = 1 ? ? pcm2 hldak output setting not required pmccm2 = 1 ? ? pcm3 hldrq input setting not required pmccm3 = 1 ? ? pcs0 cs0 output setting not required pmccs0 = 1 ? ? pcs1 cs1 output setting not required pmccs1 = 1 ? ? pcs2 cs2 output setting not required pmccs2 = 1 ? ? pcs3 cs3 output setting not required pmccs3 = 1 ? ? pct0 wr0 output setting not required pmcct0 = 1 ? ? pct1 wr1 output setting not required pmcct1 = 1 ? ? pct4 rd output setting not required pmcct4 = 1 ? ? pct6 astb output setting not required pmcct6 = 1 ? ? note set pm12n to 1 to use the alternate function of p12n (anin). remark the port register (pn) does not have to be set when the alternate function is used. chapter 4 port functions user?s manual u17830ee1v0um00 285 table 4-32 register settings to use port pins as alternate-function pins (7/7) alternate-function pin pin name name i/o pmn register pmcn register pfcm regist er pfcem register other bits (register) pdl0 ad0 i/o setting not required pmcdl0 = 1 ? ? pdl1 ad1 i/o setting not required pmcdl1 = 1 ? ? pdl2 ad2 i/o setting not required pmcdl2 = 1 ? ? pdl3 ad3 i/o setting not required pmcdl3 = 1 ? ? pdl4 ad4 i/o setting not required pmcdl4 = 1 ? ? ad5 i/o setting not required pmcdl5 = 1 ? ? pdl5 flmd1 input setting not required setting not required ? ? note pdl6 ad6 i/o setting not required pmcdl6 = 1 ? ? pdl7 ad7 i/o setting not required pmcdl7 = 1 ? ? pdl8 ad8 i/o setting not required pmcdl8 = 1 ? ? pdl9 ad9 i/o setting not required pmcdl9 = 1 ? ? pdl10 ad10 i/o setting not required pmcdl10 = 1 ? ? pdl11 ad11 i/o setting not required pmcdl11 = 1 ? ? pdl12 ad12 i/o setting not required pmcdl12 = 1 ? ? pdl13 ad13 i/o setting not required pmcdl13 = 1 ? ? pdl14 ad14 i/o setting not required pmcdl14 = 1 ? ? pdl15 ad15 i/o setting not required pmcdl15 = 1 ? ? note the flmd1 pin does not have to be manipulated by using a port control register becaus e it is used in the flash programming mode. for details, refer to chapter 25 flash memory . remark the port register (pn) does not have to be set when the alternate function is used. chapter 4 port functions user?s manual u17830ee1v0um00 286 4.3.18 operation of port function the operation of a port differs depending on setting of the input or output mode, as follows. (1) writing to i/o port (a) in output mode a value can be written to the output latch by using a tr ansfer instruction. the cont ents of the output latch are output from the pin. once data has been written to the output latch, it is reta ined until new data is written to the output latch. (b) in input mode a value can be written to the output latch by using a tran sfer instruction. because the output buffer is off, however, the status of the pin remains unchanged. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. caution although a 1-bit memory manipulation instruction manipulat es 1 bit, it accesses a port in 8- bit units. if a port has a mixture of input and output pins, therefore, the contents of the output latch of a pin set in the input mode become undefined, even if the pin is not subject to manipulation. (2) reading from i/o port (a) in output mode the contents of the output latch can be read by using a transfer instruction. the contents of the output latch are not changed. (b) in input mode the status of the pi n can be read by using a transfer instruction. the contents of t he output latch are not changed. (3) operation of i/o port (a) in output mode an operation is performed on the contents of the output latch and the result is written to the output latch. the contents of the output latch are output from the pin. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. (b) in input mode the contents of the output la tch become undefined. because the output buff er is off, however, the status of the pin remains unchanged. caution although a 1-bit memory manipulation instruction manipulat es 1 bit, it accesses a port in 8- bit units. if a port has a mixture of input and output pins, therefore, the contents of the output latch of a pin set in the input mode become undefined, even if the pin is not subject to manipulation. chapter 4 port functions user?s manual u17830ee1v0um00 287 4.4 cautions 4.4.1 cautions on setting port pins (1) the general-purpose port function a nd several peripheral function i/o pin share a pin. to switch between the general-purpose port (port mode) a nd the peripheral function i/o pin (alt ernate-function mode), set by the pmcn register. in regards to this register setting sequence, note with caution the following. (a) cautions on switching from port mode to alternate-function mode to switch from the port mode to alternate-function mode in the following order. <1> set the pfn register note : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode if the pmcn register is set first, note with caution that, at that moment or depending on the change of the pin states in accordance with the setti ng of the pfn, pfcn, and pfcen registers, unexpected operations may occur. note no-ch open-drain output pin only caution regardless of the port mode /alternate-function mode, the pn register is read and written as follows. ? pn register read: read the port output latc h value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? . pn register write: write to the port output latch (b) cautions on alternate-function mode (input) the input signal to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the and output of the pmcn register set va lue and the pin level. thus, depending on the port setting and alternate function operation enable timing, unexpected operations may occur. therefore, switch between the port mode and alternate-function mode in the following sequence. ? to switch from port mode to alternate-function mode (input) set the pins to the alternate-function mode using the pmcn register and then enable the alternate function operation. ? to switch from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. (2) in port mode, the pfn.pfnm bit is valid only in t he output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bi t is not reflected in the buffer. chapter 4 port functions user?s manual u17830ee1v0um00 288 4.4.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewrite the output latc h when switching a port from input mode to output mode. 4.4.3 cautions on on-chip debug pins the drst, dck, dms, ddi, and ddo pins are on-chip debug pins (these pins are available only in the flash memory versions). after reset by the reset pin, the p05 /intp2/drst pin is initialized to function as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-chip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the above action is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. caution after reset by the wdt2res signal, clock m onitor (clm), or low-voltage detector (lvi), the p05/intp2/drst pin is not initialized to func tion as an on-chip debug pin (drst). the ocdm register holds the current value. 4.4.4 cautions on p05/intp2/drst pin the p05/intp2/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, a pull-down resistor is connected. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0). user?s manual u17830ee1v0um00 289 chapter 5 bus control function the v850es/fj2 is provided with an external bus interface function by which memories such as rom and ram, or i/o, can be externally connected. v850es/fe2, v8 50es/ff2, v850es/fg2 do not embed this interface. 5.1 features output from a multiplexed bus with a minimum of 3 bus cycles 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states per memory block ? external wait function using wait pin idle state insertion function bus hold function external devices can be connected using alternate-function port pins fixed to little-endian format misaligned access possible chip select function (4 spaces) chapter 5 bus control function user?s manual u17830ee1v0um00 290 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus wait pcm0 input external wait control clkout pcm1 output internal system clock cs0 to cs3 pcs0 to pcs3 output chip select signal wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed the following list shows pin statuses when internal rom, internal ra m, or on-chip peripheral i/o is accessed. access destination address bus data bus control signal internal rom undefined hi-z inactive internal ram undefined hi-z inactive on-chip peripheral i/o note hi-z inactive note when an on-chip peripheral i/o is accessed, the address of the on-chip peripheral i/o being accessed is output via the address bus. 5.2.2 pin status in each operation mode for the pin status of the v850 es/fj2 in each operation mode, see 2.2 pin status . chapter 5 bus control function user?s manual u17830ee1v0um00 291 5.3 memory block function 5.3.1 memory space the 64 mb memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycl e operation mode for each of these bloc ks can be independen tly controlled in one-block units. figure 5-1. data memory map 3ffffffh 3ffffffh 3fec000h 3febfffh 3fff000h 3ffefffh 3ff0000h 3feffffh 3fef000h 3fec000h 3feefffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 01fffffh 00fffffh 0000000h 0000000h 0100000h (80 kb) (2 mb) cs0 cs3 cs2 cs1 use prohibited use prohibited programmable peripheral i/o area on-chip peripheral i/o area (4 kb) internal ram area (60 kb) internal rom/ external memory area note (1 kb) internal rom/ external memory area note (1 kb) external memory area (8 mb) external memory area (4 mb) external memory area (2 mb) note addresses 0000000h to 00fffffh are internal ro m area when a fetch access or read access is performed and external memory area when a write access is performed. chapter 5 bus control function user?s manual u17830ee1v0um00 292 5.3.2 chip select function of the 64 mb address space, the lower 16 mb (0000000h to 0ffffffh) include four chip select functions, cs0 to cs3. the areas that can be selected by cs 0 to cs3 are fixed as shown in table 5-2. however, since the v850es/fj2 has sixteen address pi ns (pdl0/ad0 to pdl15/ad15); 64 kb addresses can be selected linearly. table 5-2. area selected by chip select function pin name area cs0 0000000h to 01fffffh (2 mb) cs1 0200000h to 03fffffh (2 mb) cs2 0400000h to 07fffffh (4 mb) cs3 0800000h to 0ffffffh (8 mb) chapter 5 bus control function user?s manual u17830ee1v0um00 293 5.4 bus access 5.4.1 number of clocks for access the following table shows the number of base clocks required for accessing each resource. table 5-3. number of clocks for access area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 3 + n instruction fetch (branch) 2 1 3 + n operand data access 3 1 3 + n note 2 if a conflict with a data access occurs. remark unit: clocks/access 5.4.2 bus size setting function the bus size of each external memory area selected by cs0 to cs3 can be set (to 8 bits or 16 bits) by using the bus size configuration (bsc) register. the external memory area (01000000h to 0ffffffh) of the v850es/fj2 is selected by cs0 to cs3. (1) bus size configuration (bsc) register the bsc register can be read or written in 16-bit units. caution write to the bsc register after reset, and then do not chan ge the set values. also, do not access an external memory area ot her than the one for this in itialization rout ine until the initial settings of the bsc register are comp lete. however, external memory areas whose initial settings are complete may be accessed. after reset: 5555h r/w address: fffff066h 15 0 7 0 bsn0 0 1 8 bits 16 bits bsc 14 1 6 bs30 13 0 5 0 12 1 4 bs20 11 0 3 0 10 1 2 bs10 9 0 1 0 8 1 0 bs00 data bus size of csn space (n = 0 to 3) cs0 cs3 csn signal cs2 cs1 caution be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. chapter 5 bus control function user?s manual u17830ee1v0um00 294 5.4.3 access according to bus size the v850es/fj2 accesses the on-chip peripheral i/o and exte rnal memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/fj2 supports only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function user?s manual u17830ee1v0um00 295 (2) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function user?s manual u17830ee1v0um00 296 (3) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17830ee1v0um00 297 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17830ee1v0um00 298 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17830ee1v0um00 299 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17830ee1v0um00 300 5.5 wait function 5.5.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. the number of wait states can be pr ogrammed for each chip select area (cs0 to cs3) by using data wait control register 0 (dwc0). immediately after system rese t, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. cautions 1. the internal rom and internal ram areas are not subj ect to programmable wait, and are always accessed without a wait state. the on- chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initia lization routine until the initial settings of the dwc0 register ar e complete. however, external memory areas whose initial settings are complete may be accessed. after reset: 7777h r/w address: fffff484h 15 0 7 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 14 dw32 6 dw12 13 dw31 5 dw11 12 dw30 4 dw10 11 0 3 0 10 dw22 2 dw02 9 dw21 1 dw01 8 dw20 0 dw00 number of wait states inserted in csn space (n = 0 to 3) cs3 csn signal cs2 cs1 csn signal cs0 caution be sure to clear bits 15, 11, 7, and 3 to 0. chapter 5 bus control function user?s manual u17830ee1v0um00 301 5.5.2 external wait function to synchronize an extremely slow external memory, i/o devi ce, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the se tup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 5.5.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. figure 5-3. wait control wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-4. inserting wait example t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function user?s manual u17830ee1v0um00 302 5.5.4 programmable address wait function address-setup or address-hold waits to be inserted in eac h bus cycle can be set by using the address wait control register (awc). address wait insertion is set for each chip select area (cs0 to cs3). if an address setup wait is inserted, it seem s that the high-clock period of the t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-cl ock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. after reset: ffffh r/w address: fffff488h 15 1 ahw3 ahwn 0 1 not inserted inserted awc 14 1 6 asw3 13 1 ahw2 12 1 asw2 11 1 ahw1 10 1 asw1 9 1 ahw0 8 1 asw0 specification of insertion of address hold wait in csn space (n = 0 to 3) 1 2 3 4 5 7 0 aswn 0 1 not inserted inserted specification of insertion of address setup wait in csn space (n = 0 to 3) cs0 cs3 cs2 cs1 csn signal caution be sure to set bits 15 to 8 to 1. chapter 5 bus control function user?s manual u17830ee1v0um00 303 5.6 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted afte r the t3 state in the bus cycle that is executed for each space select ed by the chip select function. by in serting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted can be prog rammed by using the bus cycle control (bcc) register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control (bcc) register the bcc register can be read or written in 16-bit units. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area ot her than the one for this in itialization routine until the initial settings of the bcc register are comple te. however, external memory areas whose initial settings are complete may be accessed. after reset: aaaah r/w address: fffff48ah 15 1 bc31 bcn1 0 1 not inserted i nserted bcc 14 0 6 0 13 1 bc21 12 0 0 11 1 bc11 10 0 0 9 1 bc01 8 0 0 specification of insertion of idle state (n = 0 to 3) 1 2 3 4 5 7 0 cs0 csn signal cs2 cs1 cs3 caution be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0. chapter 5 bus control function user?s manual u17830ee1v0um00 304 5.7 bus hold function 5.7.1 functional outline the hldak and hldrq functions are valid if the pc m2 and pcm3 pins are set in the control mode. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). if the request for bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until a peripheral i/o register or the ex ternal memory is accessed. the bus hold status is indicated by a ssertion of the hldak pin (low level). the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-acce ss cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function user?s manual u17830ee1v0um00 305 5.7.2 bus hold procedure the bus hold status transition pr ocedure is shown in figure 5-5. figure 5-5. bus hold status transition <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.7.3 operation in power save mode because the internal system clock is stopped in the so ftware stop, idle1, idle2 and sub idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deassert ed, the hldak pin is also deasserted, and the bus hold status is cleared. chapter 5 bus control function user?s manual u17830ee1v0um00 306 5.8 bus priority bus hold, instruction fetch (branch), instruction fetch (s uccessive), and operand data accesses are executed in the external bus cycle. bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu 5.9 boundary operation conditions 5.9.1 program space (1) if a branch instruction exists at t he upper limit of the internal ram area, a prefetch operation straddling over the on-chip peripheral i/o area (inv alid fetch) does not occur. (2) instruction execution to the external memory area ca nnot be continued without a br anch from the internal rom area to the external memory area. 5.9.2 data space the v850es/fj2 has an address misalign function. with this function, data can be placed at all addresses, rega rdless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (1) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (2) word-length data access (a) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are gener ated in that order if the least significant bit of the address is 1. (b) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10. chapter 5 bus control function user?s manual u17830ee1v0um00 307 5.10 bus timing 5.10.1 multiplexed bus figure 5-6. basic bus cycle t1 t3 t1 tw tw t2 ti t2 t3 t1 clkout ad15 to ad0 astb csn wait rd a3 a1 a2 d1 d2 programmable weight external weight idle state notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. csn (n = 3 to 0) becomes low level, as shown abov e, when the corresponding csn area is accessed. otherwise, csn is always high level. remark : sampling clock at the time of 8bit access odd number address even number address ad15-ad8 data ? ad7-ad0 ? data chapter 5 bus control function user?s manual u17830ee1v0um00 308 figure 5-7. when wait state (1 wait) is inserted a1 a2 d1 d2 a3 a1 a2 t1 t3 t1 tw tw t2 ti t2 t3 t1 clkout ad15 to ad8 ad7 to ad0 astb csn wait rd programmable weight external weight idle state notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. csn (n = 3 to 0) becomes low level, as shown abov e, when the corresponding csn area is accessed. otherwise, csn is always high level. remark . : sampling clock chapter 5 bus control function user?s manual u17830ee1v0um00 309 figure 5-8. when idle state is inserted a1 d1 a2 d2 a3 00 00 t1 t3 t1 tw tw t2 ti t2 t3 t1 clkout ad15 to ad0 astb csn wait wr1, wr0 programmable weight external weight idle state notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. csn (n = 3 to 0) becomes low level, as shown abov e, when the corresponding csn area is accessed. otherwise, csn is always high level. remark. : sampling clock at the time of 8bit access odd number address even number address ad15-ad8 data uncertain ad7-ad0 uncertain data wrn (n = 1 or 0) 01 10 chapter 5 bus control function user?s manual u17830ee1v0um00 310 figure 5-9. when wait state (1 wait) and idle state are inserted a1 a2 d1 d2 a3 a1 a2 10 10 t1 t3 t1 tw tw t2 ti t2 t3 t1 clkout ad15 to ad8 ad7 to ad0 astb csn wait wr1, wr0 programmable weight external weight idle state notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. csn (n = 3 to 0) becomes low level, as shown abov e, when the corresponding csn area is accessed. otherwise, csn is always high level. remark. : sampling clock chapter 5 bus control function user?s manual u17830ee1v0um00 311 figure 5-10. when address wait state is inserted a1 d1 00 00 t1 tasw t2 tahw t1 t2 t3 clkout ad15 to ad0 astb csn wait wr1, wr0 address data notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. csn (n = 3 to 0) becomes low level, as shown ab ove, when the corresponding csn area is accessed. otherwise, csn is always high level. remark. : sampling clock chapter 5 bus control function user?s manual u17830ee1v0um00 312 figure 5-11. basic bus cycle a1 d1 a2 d2 undefined undefined all all bus idle t2 t3 th th ti th t1 th ti t2 t1 t3 clkout hldak hldrq ad15 to ad0 astb rd csn notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. 3. csn (n = 3 to 0) becomes low level, as shown abov e, when the corresponding csn area is accessed. otherwise, csn is always high level. 4. idle state (ti) that does not depe nd on the setting value of bcc register. user?s manual u17830ee1v0um00 313 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator ? in clock-through mode f x = 4 to 5 mhz (f xx = 4 to 5 mhz) ? in pll (phase locked loop) mode f x = 4 to 5 mhz (f xx = 16 to 20 mhz) { subclock oscillator (sub-resonator) ? 32.768 khz ? 20 khz (rcr = 390 k ? , c = 47 pf) { multiply ( 4) function via pll (phase locked loop) ? clock-through mode/pll mode selectable { ring osc ? f r = 200 khz (typ.) { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function { programmable clock output (pcl) function remarks: 1. f x main clock oscillation frequency 2. f xx main clock frequency 3. f r internal oscillator clock frequency chapter 6 clock generation function user?s manual u17830ee1v0um00 314 6.2 configuration figure 6-1. clock generator ring-osc xt1 xt2 clkout x1 x2 pcl pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1024 f x /2 to f x /2 12 f xt f xx f x f r 8 frc bit mfrc bit ck2 to ck0 bits ck3 bit selpll bit pllon bit software stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock peripheral clock internal system clock main clock oscillator main clock oscillator stop control idle mode 1, 2 selector selector selector 1/8 divider watch timer (wt) clock, csib0 clock rstp bit watchdog timer 2 (wdt2) clock 1/2 divider selector idle control idle mode 1, 2 watch timer clock prescaler 3 select oscillator selector pck1, pck0 bit prescaler 4 watchdog timer 2 (wdt2) selector f xt xtal f x to f x /128 f xt rc main clock oscillator stop detection (1) main clock oscillator the main clock oscillator oscillates the following frequencies (f x ). ? in clock-through mode f x = 4 to 5 mhz (internal f xx = 4 to 5 mhz) ? in pll mode f x = 4 to 5 mhz (internal f xx = 16 to 20 mhz) (2) subclock oscillator the subclock oscillator oscillates a frequency (f xt ) of 32.768 khz or 20 khz. chapter 6 clock generation function user?s manual u17830ee1v0um00 315 (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscill ator is stopped in the software stop mode or when the mck bit of the pcc register = 1 (valid only when the cls bit of the pcc register = 1). (4) ring-osc outputs a frequency (f r ) = 200 khz (typ.) (5) prescaler 1 this prescaler generates the clock (fxx to fxx/1,024) to be supplied to on-chip peripheral functions. peripheral functions are as follows. tmp0-tmp3, tmq0-tmq2, tmm0, csib0- csib2, uarta0-uarta3, adc, wdt2. (6) prescaler 2 this circuit divides the cpu clock (f cpu ) and main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the internal system clock (f clk ). f clk is the clock supplied to the intc, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, see chapter 10 watch timer functions . (8) prescaler 4 this prescaler generates the clock (f x to f x /1048) to be supplied to on-chip peripheral functions such as the only wdt2. (9) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by using the selpll bit of the pll control register (pllctl). pll is started or stopped by the p llon bit of the pllctl register. chapter 6 clock generation function user?s manual u17830ee1v0um00 316 6.3 control registers (1) processor clock control register (pcc) the pcc register is a special register . data can be written to this register in combination of specific sequences (see 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 03h. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 enable oscillation oscillation stopped mck 0 1 operation of main clock used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. note the cls bit is a read-only bit. chapter 6 clock generation function user?s manual u17830ee1v0um00 317 (2/2) f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 cautions 1. do not change the cpu clock (by us ing the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation inst ruction to manipulate the ck3 (0 1 or 1 0) bit. when using an 8-bit manipulation instruction, do not ch ange the set values of the ck2 to ck0 bits. remark : don?t care (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use a bit manipulation instruction. do not change the ck2 to ck0 bits. <2> subclock operation: it takes up to the following num ber of instructions after the ck3 bit is set until the subclock operation is started. 1/subclock frequency (f xt ) therefore, read the cls bit to che ck if the subclock oper ation has started. <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the main clock, stop the pll. 2. if the following conditions are not satisfied, change the ck2 to ck0 bits so that the conditions are satisfied, then change to th e subclock operation mode. setting clock by ck2-ck0 (fxx-fxx/32) > subclock (f xt ) x4 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock oscillation starts. <2> insert wait cycles by program and wait until t he oscillation of the main clock has stabilized. <3> ck3 bit 0: use a bit manipulation instruction. do not change the ck2 to ck0 bits. <4> main clock operation: it takes up to the followin g time after the ck3 bit is set until the main clock operation specified by the ck2 to ck0 bits is started. max.: (1/subclock frequency) therefore, read the cls bit to check if the main clock operation has started. chapter 6 clock generation function user?s manual u17830ee1v0um00 318 (2) cpu operation clock status register (ccls) the ccls register indicates the cpu operating clock status. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf cpu operating clock status cclsf 0 1 operates on main clock (f x ) or subclock (f xt ) operates on internal oscillator (f r ) after reset: 00h r address: fffff82eh caution if wdt2 overflows before counting the oscillation stabilization ti me ends after a reset or stop mode release, it is judged as abnormal oscillation of f x (main clock) and the cpu operates on the ring-osc clock. (3) ring-osc mode register (rcm) the rcm register is an 8-bit register t hat sets the operation mode of ring-osc. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 rcm 0 0 0 00 0 rstop ring-osc operating ring-osc stopped rstop 0 1 operation/stop of ring-osc after reset: 00h r/w address: fffff80ch caution 1. ring-osc can be stopped by setting the rsto p bit of the rcm register to 1 only when ?ring- osc stopped? is selected by the option function. caution 2. if rstop bit is set (1), the internal oscillato r is oscillated by .cclsf bit is set (1) (wdt overflow is generated in the oscillation stabilization ti me).then, the rstop bit remains being set (1). (4) oscillation stabilization time select register (osts) the osts register selects the oscillation stabilization time following reset or release of the stop mode. see 11.3 (1) oscillation stabilization time select register (osts) . chapter 6 clock generation function user?s manual u17830ee1v0um00 319 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register cls bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 <1> <2> <3> <4> <5> <6> <7> <6> <7> main clock oscillator (f x ) { { { { { subclock oscillator (f xt ) { { { { { { { { { cpu clock (f cpu ) { { internal system clock (f clk ) { { { peripheral clock (f xx to f xx /1,024) { { wt clock (main) { { { { wt clock (sub) { { { { { { { { { wdt2 clock (ring) { { { { { { { { wdt2 clock (main) { { { { main clock oscillator (fxx) { { pll clock (f pll ) note1 { note 2 { { notes: 1. the stable clock is supplied from beginning operation after the time of 172 passes and through the lock- up time. 2. the operation enable at idle1 mode. stopped at idle2 mode remark cls bit: bit 4 of the processor clock control register (pcc) mck bit: bit 6 of the pcc register o: operable : stopped <1>: reset pin input <2>: during oscillation stabilization time count <3>: halt mode <4>: idle1, idle2 mode <5>: software stop mode <6>: subclock operation mode <7>: sub-idle mode chapter 6 clock generation function user?s manual u17830ee1v0um00 320 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the ck3 to ck0 bits of the processor clock control register (pcc). the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 6-1 and the pin can output the clock when it is in the operable status . it outputs a low level in the stopped stat us. however, the alternate-function pin (pcm1: input mode) is selected in <1> and <2> af ter the reset signal has been input. consequently, the clkout pin goes into a high-impedance state. 6.5 pll function 6.5.1 overview the pll function is used to output the operating clock of the cpu and peripheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. when pll function is used: input clock = 4 to 5 mhz (output: 16 to 20 mhz) clock-through mode: input clock = 4 to 5 mhz (output: 4 to 5 mhz) 6.5.2 control registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 control of pll operation/stop clock-through mode pll mode selpll 0 1 cpu operation clock selection after reset: 01h r/w address: fffff82ch cautions 1. the selpll bit can be set to 1 only wh en the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the sel oll bit if data is written to it. 2. when the pllon bit is clear ed to 0, the selpll bit is auto matically cleared to 0 (clock- through mode). chapter 6 clock generation function user?s manual u17830ee1v0um00 321 (2) lock register (lockr) phase lock occurs at a given frequency following powe r application or immediately after the software stop mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). this time until stabilization is called the lockup status, and the stabilized state is ca lled the locked status. the lock register (lockr) includes a lock bit that reflects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. remark: at the lockup time (frequency stabilization time) lockr is set (1) 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h caution the lock register does not reflect the lock status of the pll in real time. the set/reset conditions are as follows. [set conditions] ? in idle2 or upon system reset note ? in software stop mode ? upon setting of pll stop (clearing of pl lon bit of pllctl register to 0) ? upon stopping main clock and using cpu with subclock (setting of ck3 bit of pcc register to 1 and setting of mck bit of same register to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [reset conditions] ? upon overflow of oscillation stabilization time following reset release (osts register default time) ? upon oscillation stabilization timer overflow (time set by osts register) following software stop mode release, when the software stop mode was set in the pll operating status ? upon pll lockup timer overflow (time set by plls r egister) when the pllon bit of the pllctl register is changed from 0 to 1 ? upon oscillation stabilization timer overflow (time set by osts register) following software idle2 mode release, when the software idle2 mode was set in the pll operating status chapter 6 clock generation function user?s manual u17830ee1v0um00 322 (3) pll lockup time specification register (plls) the plls register is an 8-bit regist er used to select the pll lockup ti me when the pllon bit of the pllctl register is changed from 0 to 1. this register can be read or written in 8-bit units. reset input sets this register to 03h. 0 setting prohibited setting prohibited 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h caution set so that the lockup time is 800 s or longer. chapter 6 clock generation function user?s manual u17830ee1v0um00 323 (4) programmable clock mode register (pclm) the pclm register is an 8-bit regi ster used to control the pcl output. this register can be read or written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff82fh 0 pcle 0 1 f xx /2 f xx /4 f xx /8 f xx /16 pcl output disabled (fixed to low level) pcl output enabled pck1 0 0 1 1 pck0 0 1 0 1 selection of pll output clock selection of pcl output operation pclm 0 0 pcle 0 0 pck1 pck0 caution set the port-related control registers (pm, pmc, pfc, pfce, etc.) first, and then set pcle to 1. caution set pcle to 1 only during pll operation. to stop the pll, clear pcle to 0. 6.5.3 usage (1) to use pll ? after the reset signal has been released, the pll oper ates (pllon bit = 1), but because the default mode is the clock-through mode (selpll bit = 0) , select the pll mode (selpll bit = 1). ? to operate the pll from the stopped status, set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit = 0 (the lockup time can be counted by setting the lockup time to the plls register and monitoring the lock flag of the lockr register). ? to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0) when shifting to the idle2 or stop mode while remainin g in the pll operation mode, set the osts register as follows. ? software stop mode: oscillation stab ilization time > pll lockup time (800 s (min.)) ? idle2 mode: setup time > pll lockup time (800 s (min.)) when shifting to the idle1 mode, the pll does not stop.stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected after the reset signal has been released, but the pll is operating (pllon bit = 1) and must therefore be stopped (pllon bit = 0). user?s manual u17830ee1v0um00 324 chapter 7 16-bit timer/event counter p the v850es/fe2, v850es/ff2, v850es/fg2, v850es/fj2 incl ude 16-bit timer/event counter p (tmp0 to tmp3). 7.1 features timer p (tmp) is a 16-bit timer/event c ounter that can be used in various ways. tmp can perform the following operations. ? pwm output ? interval timer ? external event counter (operation disabled when clock is stopped) ? one-shot pulse output ? pulse width measurement function ? timer synchronized operation function ? free-running function ? external trigger pulse output function 7.2 functional outline ? capture trigger input signal 2 ? external trigger input signal 1 ? clock selection 8 ? external event count input 1 ? readable counter 1 ? capture/compare reload register 2 ? capture/compare match interrupt 2 ? timer output (topn0, topn1) 2 remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 325 7.3 configuration tmp consists of the following hardware. table 7-1. configuration of tmp0 to tmp3 item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter read buffer register (tpncnt) ccr0, ccr1 buffer registers timer inputs 2 (tipn0 note 1 , tipn1) timer outputs 2 (topn0, topn1) control registers tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) selector operation control registers 0, 1 (selcnt0, selcnt1 note 2 ) tipnm pin noise elimination control register (pnmnfc) notes 1. tipn0 functions alternately as a capture trigger input signal, external trigger input signal, and external event count input signal. 2. selcnt1 is incorporated only in the pd70f3239. remark n = 0 to 3, m = 0, 1 the pins of tmp function alter nately as port pins. for how to set the alternate function, refer to the description of the registers in chapter 4 port functions . table 7-2. tmp pin list pin name alternate-function pin i/o function tip00 p32/ascka0/top00/top01 tip01 p33/top01/ctxd0 external event/clock input (tmp0) tip10 p34/top10/crxd0 tip11 p35/top11 external event/clock input (tmp1) tip20 p97/sib1/top20 tip21 p96/top21 external event/clock input (tmp2) tip30 p01/top30 tip31 p00/top31 input external event/clock input (tmp3) top00 p32/ascka0/tip00/top01 top01 p32/ascka0/tip00/top00 p33/tip01/ctxd0 timer output (tmp0) top10 p34/tip10/crxd0 top11 p35/tip11 timer output (tmp1) top20 p97/sib1/tip20 top21 p96/tip21 timer output (tmp2) top30 p01/tip30 top31 p00/tip31 output timer output (tmp3) chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 326 figure 7-1. block diagram of timer p internal bus tpnccr0 tpnccr1 counter control trigger control tpncnt0 clear 16-bit counter ccr0 buffer register ccr1 buffer register tpnctl1 tpnsye tpnest tpneee tpnmd2 tpnmd1 tpnmd0 tpnopt0 tpnccs1 tpnccs0 tpnovf tpnioc1 tpnis3 to tpnis0 selcnt0/1 isel11 to isel10, isel06 to isel00 tpnioc0 tpnce tpnce inttpncc0 tpnctl0 tpnce tpncks2 tpncks1 tpncks0 tpnol1 tpnoe1 tpnol0 tpnoe0 tpnioc2 tpnees1 tpnees0 tpnets1 tpnets0 selector selector selector selector f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 selector internal bus edge detector edge detector edge detector edge detector load load inttpnov inttpncc1 topn0 output controller capture/compare selection function tipn0 note 3 f xt note 2 f xx /128 note 1 note 4 tipn1 topn1 notes 1. tmp0, tmp2 2. tmp1, tmp3 3. tsout signal of can0 block (tmp0) rxda0 pin (tmp1) tsout signal of can2 block (tmp2) rxda2 pin (tmp3) refer to 7.4 (7) selector operation control register 0 (selcnt0) and 7.4 (8) selector operation control register 1 (selcnt1) . 4. inttm0eq0 interrupt of tmm block or tsout signal of can1 block (tmp0) rxda1 pin (tmp1) tsout signal of can3 block (tmp2) rxda3 pin (tmp3) refer to 7.7 (1) selector operation control register 0 (selcnt0) and 7.7 (2) selector operation control register 1 (selcnt1) . remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 327 (1) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register is a 16-bit register that has a capture function and a compare function. only in the free-running mode, this register is used as a capture register or a compare register, this behavior can be specified by using the tpn ccs0 bit of the tpnopt0 register. in the pulse width measurement mode, this register works only as a capture register. in all the modes other than the free-running mode and pu lse width measurement mode, this register functions as a compare register. in the default status, the tpnccr0 regi ster functions as a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution at the time of subclock operated a nd main clock stopped, the access to tpnccr0 is prohibited. for details, refer to 3. 4. 10 2 after reset: 0000h r/w address: tp0ccr0: fffff596h, tp1ccr0: fffff5a6h, tp2ccr0: fffff5b6h, tp3ccr0: fffff5c6h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tpnccr0 (n = 0 to 3) ? when used as compare register tpnccr0 can be rewritten when tpnce = 1. tmp operation mode method of writing tpnccr0 register pwm output mode or external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse output mode, or interval timer mode anytime write pulse width measurement mode cannot be used because used only as capture register ? when used as capture register the count value is stored in tpnccr0 on detection of the edge of the capture trigger (tipn0) input. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 328 (2) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is a 16-bit register that has a capture function and a compare function. only in the free-running mode, this register is used as a capture register or a compare register, this behavior can be specified by using the tpn ccs0 bit of the tpnopt0 register. in the pulse width measurement mode, this register works only as a capture register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution at the time of subclock operation an d main clock stopped, the access to tpnccr1 is prohibited. for details, refer to 3. 4. 10 2 after reset: 0000h r/w address: tp0ccr1: fffff598h, tp1ccr1: fffff5a8h, tp2ccr1: fffff5b8h, tp3ccr1: fffff5c8h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tpnccr1 (n = 0 to 3) ? when used as compare register tpnccr1 can be rewritten when tpnce = 1. tmp operation mode method of writing tpnccr1 register pwm output mode or external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse output mode, or interval timer mode anytime write pulse width measurement mode cannot be used because used only as capture register ? when used as capture register the count value is stored in tpnccr1 on detection of the edge of the capture trigger (tipn1) input. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 329 (3) tmpn counter read bu ffer register (tpncnt) the tpncnt register is a read buffer register that can read the value of the 16-bit counter. this register is read-only, in 16-bit units. reset input sets this register to ffffh. although the hardware status is ffffh when tp nce = 0, 0000h is read from this register. the counter value of the 16-bit c ounter is read when tpnce = 1. caution at subclock operated and at main clock stopped, the acsess to tpncnt register is not enable. for details, refer to 3. 4. 10 2 after reset: ffffh r address: tp0cnt: fffff59ah, tp1cnt: fffff5aah, tp2cnt: fffff5bah, tp3cnt: fffff5cah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tpncnt (n = 0 to 3) chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 330 7.4 control registers (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of timer p. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tpnctl0 register cannot be rewritten in operati ng. but only tpnce bit can always be rewritten. (1/2) after reset: 00h r/w address: tp0ctl0: fffff590h, tp1ctl0: fffff5a0h, tp2ctl0: fffff5b0h, tp3ctl0: fffff5c0h 7 6 5 4 3 2 1 0 tpnctl0 tpnce 0 0 0 0 tpncks2 tpncks1 tpncks0 (n = 0 to 3) tpnce control of operation of timer pn 0 disable internal operating clock o peration (asynchronously reset tmpn). 1 enable internal operating clock operation. the tpnce bit controls the internal operating cloc k and asynchronously resets tmpn. when this bit is cleared to 0, the internal operating clock of tmpn is stopped (fixed to the low level), and tmpn is asynchronously reset. when the tpnce bit is set to 1, the internal oper ating clock is enabled within 2 input clocks, and tmpn counts up. tpncks2 tpncks1 tpncks0 selection of internal count clock n = 0, 2 n = 1, 3 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /8 1 0 0 f xx /16 1 0 1 f xx /32 1 1 0 f xx /64 1 1 1 f xx /128 f xt caution set the tpncks2 to tpncks0 bits when tpnce = 0. when the tpnce bit setting is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set at the same time. remark f xx : main system clock frequency f xt : xt1 input clock frequency chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 331 (2/2) resolution and maximum number of counts resolution [ s] maximum count time [ms] internal count clock f xx = 16 mhz f xx = 20 mhz f xx = 16 mhz f xx = 20 mhz f xx 0.0625 0.050 4.10 3.28 f xx /2 0.125 0.100 8.19 6.55 f xx /4 0.250 0.200 16.38 13.11 f xx /8 0.500 0.400 32.77 26.21 f xx /16 1.000 0.800 65.54 52.43 f xx /32 2.000 1.600 131.11 104.86 f xx /64 4.000 3.200 262.14 209.72 f xx /128 8.000 6.400 524.29 419.43 resolution [ s] maximum count time [ms] internal count clock f xt = 32.768 khz f xt = 32.768 khz f xt 30.52 2000.00 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 332 (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of timer p. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. (1/2) after reset: 00h r/w address: tp0ctl1: fffff591h, tp1ctl1: fffff5a1h, tp2ctl1: fffff5b1h, tp3ctl1: fffff5c1h 7 6 5 4 3 2 1 0 tpnctl1 tpnsye tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 (n = 0 to 3) tpnsye tuned operation mode enable control 0 independent operation mode (asynchronous operation mode) 1 tuned operation mode (specification of slave operation) in this mode, timer p can operate in syn chronization with a master timer. master timer slave timer tmp0 tmp1 ? tmp2 tmp3 tmq0 tmq1 tmq2 ? for the tuned operation mode, refer to 7.6 timer synchronized operation function . caution be sure to clear the tp0sye and tp2sye bits to 0. tpnest software trigger control 0 no operation 1 in one-shot pulse mode: one-shot pulse software trigger in external trigger pulse output mode: pulse output software trigger the tpnest bit functions as a software trigger in the one-shot pulse mode or external trigger pulse output mode (this bit is invalid in any other mode). by setting tpnest to 1 when tpnce = 1, a software trigger is issued. therefore, be sure to set tpnest to 1 when tpnce = 1. the tipn0 pin is used for an external trigger. t he read value of the tpnest bit is always 0. tpneee selection of count clock 0 internal clock (clock selected by tpncks2 to tpncks0 bits) 1 external event count input (edge of input to tipn0) the valid edge is specified by the tpnees1 and tpnees0 bits when tpneee = 1 (external event count input: tipn0). chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 333 (2/2) tpnmd2 tpnmd1 tpnmd0 selection of timer mode 0 0 0 interval timer mode 0 0 1 external event count mode 0 1 0 external trigger pulse output mode 0 1 1 one-shot pulse mode 1 0 0 pwm mode 1 0 1 free-running mode 1 1 0 pulse width measurement mode 1 1 1 setting prohibited cautions 1. set the tpneee and tpnmd2 to tpnmd0 bits when tpnce = 0 (the same value can be written when tpnce = 1). if these bits are rewritten when tpnce = 1, the ope ration cannot be guaranteed. if these bits are rewritten by mistake, clear tpnce to 0 and then set them again. 2. the external event count input is selected regardless of the value of the tpneee bit at an ex ternal event count mode. 3. set "0" to bit 3 and 4. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 334 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register t hat controls the timer outputs (topn0 and topn1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tp0ioc0: fffff592h, tp1ioc0: fffff5a2h, tp2ioc0: fffff5b2h, tp3ioc0: fffff5c2h 7 6 5 4 3 2 1 0 tpnioc0 0 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 (n = 0 to 3) tpnolm setting of topnm output level (m = 0, 1) 0 normal output 1 inverted output tpnoem setting of topnm output (m = 0, 1) 0 disable timer output (topnm pin outputs low level when tpnolm = 0, and high level when tpnolm = 1). 1 enable timer output (topnm pin outputs pulses). cautions 1. rewrite the tpnol1, tpnoe1 , tpnol0 and tpnoe0 bits when tpnce = 0 (the same value can be written wh en tpnce = 1). if these bits are rewritten by mistake, clear tpnce to 0 and then set them again. 2. to enable the timer output, be sure to set the corresponding alternate-function pins tpnis3 to tpnis0 of the tpnioc1 register to ?detect no edge? and invalidate the capture operation. then set the corresponding alternate-function port to output mode. 3. in the state of tpnce bit = 0 and tpnoem bit = 0, the output level of topnm pin changes even when the tpnolm bit is operated. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 335 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit regi ster that controls the valid edge of the external input signals (tipn0 and tipn1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tp0ioc1: fffff593h, tp1ioc1: fffff5a3h, tp2ioc1: fffff5b3h, tp3ioc1: fffff5c3h 7 6 5 4 3 2 1 0 tpnioc1 0 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 (n = 0 to 3) tpnis3 tpnis2 setting of valid edge of capture input (tipn1) 0 0 detect no edge (capture operation is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. tpnis1 tpnis0 setting of valid edge of capture input (tipn0) 0 0 detect no edge (capture operation is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. cautions 1. rewrite the tpnis3 to tpnis0 bits when tpnce0 = 0 (the same value can be written when tpnce = 1). if these bits are rewritten by mistake, clear tpnce to 0 and then set them again. 2. the tpnis3 to tpnis0 bits are valid only in the free-running mode and pulse width measurement mode. a capture operation is not performed in any other mode. 3. if used as the capture input , be sure to set the corresponding alternate-function pins tpnoe1 and tpnoe0 of the tpnioc0 register to ?disable timer output? and set the capture input valid edge. then set the corresponding alternate-function port to input mode 4. set it without the edge detection of the tipn0 capture input (tpnis1 and 0 bit = 00b) when using it in the external event count mode (tpneee bit = 1 of tpnctl1). chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 336 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tipn0) and external trigger input signal (tipn0). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tp0ioc2: fffff594h, tp1ioc2: fffff5a4h, tp2ioc2: fffff5b4h, tp3ioc2: fffff5c4h 7 6 5 4 3 2 1 0 tpnioc2 0 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 (n = 0 to 3) tpnees1 tpnees0 setting of valid edge of external event count input (tip00) 0 0 detect no edge (external event count is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. tpnets1 tpnets0 setting of valid edge of external trigger input (tip00) 0 0 detect no edge (external trigger is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. cautions 1. rewrite the tpnees1, tp nees0, tpnets1and tpnets0 bits when tpnce = 0 (the same value can be wr itten when tpnce = 1). if these bits are rewritten by mistake, clear tpnce to 0 and then set them again. 2. the tpnees1 and tpnees0 bits are valid when tpneee = 1 or when the external event count mode is set (tpnmd2 to tpnmd of tipnctl1 register = 001). 3. tpnets1and tpnets0 bits are valid when the external trigger pulse output mode (tpnmd2-0=010b of tpnctl register) and the one-shot pulse output mode (tpnmd2-0=011b of tpnctl1 register) is set. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 337 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit regi ster that selects a capture or com pare operation, and detects an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tp0opt0: fffff595h, tp1opt0: fffff5a5h, tp2opt0: fffff5b5h, tp3opt0: fffff5c5h 7 6 5 4 3 2 1 0 tpnopt0 0 0 tpnccs1 tpnccs0 0 0 0 tpnovf (n = 0 to 3) tpnccsm selection of capture or compare operation of tpnccrm register (m = 0, 1) 0 compare register 1 capture register the set value of the tpnccsm bit is valid only in the free-running mode. tpnovf detection of overflow of timer p set (1) overflow occurred reset (0) 0 written to tpnovf bit or tpnce = 0 ? the tpnovf bit is set when the 16-bit counter overflows from ffffh to 0000h in the free-running mode and pulse width measurement mode. ? as soon as the tpnovf bit has been set to 1, an interrupt request signal (inttpnov) is generated. the inttpnov signal is not generated in any mode other than the free-running mode and pulse width measurement mode. ? the tpnovf bit is not cleared even if the tpnovf bit and tpnopt0 register are read when tpnovf = 1. ? the tpnovf bit can be read and written, but 1 can not be written to the tpnovf bit. writing 1 to this bit does not affect the operation of timer p. caution rewrite the tpnccs1 and tpnccs0 bits when tpnce0 = 0 (the same value can be written when tpnce = 1). if these bits are rewritten by mistake, clear tpnce to 0 and then set them again. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 338 (7) tipnm pin noise elimination control register n (pnmnfc) the pnmnfc register is an 8-bit regist er that sets the digital noise filter of the timer p input pin for noise elimination. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: p00nfc : fffffb00h (tip00 pin) p01nfc : fffffb04h (tip01 pin) p10nfc : fffffb08h (tip10 pin) p11nfc : fffffb0ch (tip11 pin) p20nfc : fffffb10h (tip20 pin) p21nfc : fffffb14h (tip21 pin) p30nfc : fffffb18h (tip30 pin) p31nfc : fffffb1ch (tip31 pin) 7 6 5 4 3 2 1 0 pnmnfc 0 nfsts 0 0 0 nfc2 nfc1 nfc0 nfsts setting of number of times of sampling by digital noise filter 0 3 times 1 2 times sampling clock nfc2 nfc1 nfc0 n = 0, 2 n = 1, 3 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /16 f xx /8 1 0 0 f xx /32 f xx /16 1 0 1 f xx /64 f xt other than above setting prohibited cautions 1. be sure to clear bits 3 to 5 and 7 to 0. 2. a signal input to the timer input pin (tipnm) before the pnmnfc register is set is output wi th digital noise eliminated. therefore, set the sampling clock (nfc2 to nfc0) and the number of times of sampling (nfsts) by using the pnmnfc register, wait for initialization time = (sampling clock) (number of times of sampling), and enable the timer operation. remarks 1. the width of the noise that can be accurately eliminated is (sampling clock) (number of times of sampling ? 1). even noise with a width narrower than this may cause a miscount if it is synchronized with the sampling clock. 2. n: number of timer channels (0 to 3) m: number of input pins (0, 1) chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 339 7.5 operation timer p performs the following operations. operation tpnest (software trigger bit) tipn0 (external trigger input) capture/compare selection compare write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only reload one-shot pulse output mode note 2 valid valid compare only anytime write pwm mode invalid invalid compare only reload free-running mode invalid invalid capture/compare selectable anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event counter function, specify that the input edge of the tipn0 pin is not detected (by clearing the tpnis1 and tpnis0 bits of the tpnioc1 register to ?00?). 2. to use the external trigger pulse output mode, one- shot pulse mode, or pulse width measurement mode, select a count clock (by clearing the tpneee bit of the tpnctl1 register to 0). remark n = 0 to 3 7.5.1 anytime write and reload timer p allows rewriting of the tpnccr0 and tpnccr1 regi sters while the timer is operating (tpnce = 1). these registers are written differently (anytime write or reload) depending on the mode. (1) anytime write when data is written to the tpnccrm register during time r operation, it is transferred at any time to the ccrm buffer register and is compared wit h the value of the 16-bit counter. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 340 figure 7-2. flowchart of basic operation of anytime write start initial setting enable timer operation (tpnce = 1) transfer values of tpnccr0 and tpnccr1 to ccr0 buffer register and ccr1 buffer register ? ccr0 buffer register matches 16-bit counter. ? clear and start 16-bit counter. inttpncc0 occurs rewrite tpnccr0 transfer to ccr0 buffer register rewrite tpnccr1 transfer to ccr1 buffer register remarks 1. this is an example in the interval timer mode. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 341 figure 7-3. timing chart of anytime write d 01 d 01 d 01 d 01 0000h tpnce = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register remarks 1. d 01 , d 02 : set value of tpnccr0 r egister (0000h to ffffh) d 11 , d 12 : set value of tpnccr1 r egister (0000h to ffffh) 2. this is an example in the interval timer mode. 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 342 (2) reload when data is written to the tpnccr0 and tpnccr1 regist ers during timer operation, it is compared with the value of the 16-bit counter transferred to the ccrm bu ffer register after reserved until the written value becoming a specific state. the valu es of the tpnccr0 and tpnccr1 regi sters can be rewritten when tpnce = 1. so that the set values of the tpnccr0 and tpnccr1 registers are compared with the value of the 16-bit counter (the set values are reloaded to the ccrm buffer register), the value of the tpnccr0 register must be rewritten and then a value must be written to the tpnc cr1 register before the va lue of the 16-bit counter matches the value of tpnccr0. when the value of th e tpnccr0 register matches the value of the 16-bit counter, the values of the tpnccr0 and tpnccr1 registers are reloaded. whether the next reload timing is made valid or not is c ontrolled by writing to the tpnccr1 register. therefore, write the same value to the tpnccr1 register when it is necessary to rewrite the value of only the tpnccr0 register. figure 7-4. flowchart of basic operation of reload start initial setting enable timer operation (tpnce = 1) transfer value of tpnccrm to ccrm buffer register inttpncc0 occurs rewrite tpnccr0. rewrite tpnccr1. reload is enabled ? tpnccr0 matches 16-bit counter. ? clear and start 16-bit counter. ? value of tpnccrm is reloaded to ccrm buffer register. caution writing the tpnccr1 regist er includes an operation to enable reload. therefore, rewrite the tpnccr1 register after rewriting the tpnccr0 register. remarks 1. this is an example in the pwm mode. 2. n = 0 to 3, m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 343 figure 7-5. timing chart of reload d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 d 03 0000h d 11 d 12 tpnce = 1 note d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register note same value write d 02 d 12 note the value is not reloaded because the tpnccr1 register is not written. remarks 1. d 01 , d 02 , d 03 : set value of tpnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tpnccr1 register (0000h to ffffh) 2. this is an example in the pwm mode. 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 344 7.5.2 interval timer mode (tpnmd2 to tpnmd0 = 000) in the interval timer mode, an interrupt request signal (inttpncc0) is generated when the set value of the tpnccr0 register matches the value of the 16-bit counter, and the 16-bit counter is cleared. rewr iting the tpnccr0 register is enabled when tpnce = 1. when a value is set to the tpnccrm register, it is transferred to the ccrm buffer register by means of anytime write, an d is compared with the value of the 16 bit counter. the 16-bit counter is not cleared by using the tpnccr1 register. however, the set value of the tpnccr1 register is trans ferred to the ccr1 buffer register and compared with the value of the 16-bit counter. as a result, an interrupt request (inttpncc1) is generated. the value can also be output from the topnm pin by setting the tpnoem bit to 1. when the tpnccr1 register is not used, it is re commended to set the tpn ccr1 register to ffffh. remarks 1 . refer to 7.5.1 anytime write and reload about write operation of tpnccr0, tpnccr1 during timer operation (tpnce = 1). 2 . n = 0 to 3, m = 0, 1 figure 7-6. flowchart of basic op eration in interval timer mode start 16-bit counter and ccr0 buffer register match. clear and start 16-bit counter. inttpncc0 occurs enable timer operation (tpnce = 1) transfer values of tpnccr0 and tpnccr1 to ccr0 buffer register and ccr1 buffer register 16-bit counter matches ccr1 buffer register note . inttpncc1 occurs initial setting ? select clock (tpnctl0: tpncks2 to tpncks0). ? set interval timer mode (tpnctl1: tpnmd2 to tpnmd0 = 000). ? set compare register (tpnccr0, tpnccr1). note the 16-bit counter is not cleared when its value matches the value of tpnccr1. remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 345 figure 7-7. timing of basic operat ion in interval timer mode (1/2) (a) when d 1 > d 2 > d 3 , only tpnccr0 register value is wri tten, and topn0 and topn1 are not output (tpnoe0 = 0, tpnoe1 = 0, tpnol0 = 0, tpnol1 = 1) tpnce = 1 d 1 d 1 d 2 d 1 0000h 0000h d 3 d 3 d 2 d 1 d 2 d 3 d 3 d 3 ffffh 16-bit counter note tpnccr0 tpnccr1 inttpncc0 inttpncc1 topn0 topn1 t d1 t d1 t d2 l h ccr0 buffer register ccr1 buffer register note the 16-bit counter is not cleared when its value matches the value of tpnccr1. remarks 1. d 1 , d 2 : set value of tpnccr0 register (0000h to ffffh) d 3 : set value of tpnccr1 register (0000h to ffffh) 2. interval time (t dn ) = (dn + 1) (count clock cycle) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 346 figure 7-7. timing of basic operat ion in interval timer mode (2/2) (b) when d 1 = d 2 , tpnccr0 and tpnccr1 ar e not rewritten, and topn0 and topn1 are output (tpnoe0 = 1, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 1) 0000h d 1 d 1 ffffh tpnccr0 tpnccr1 inttpncc0 inttpncc1 topn0 topn1 0000h d 2 d 2 tpnce = 1 d 1 = d 2 d 1 = d 2 d 1 = d 2 t d1 = t d2 t d1 = t d2 t d1 = t d2 16-bit counter ccr0 buffer register ccr1 buffer register remarks 1. d 1 : set value of tpnccr0 register (0000h to ffffh) d 2 : set value of tpnccr1 register (0000h to ffffh) 2. interval time (t dn ) = (dn + 1) (count clock cycle) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 347 7.5.3 external event count mode (tpnmd2 to tpnmd0 = 001) in the external event count mode, the external event coun t input (tipn0 pin input) is used as a count-up signal. regardless of the setting of the tpneee bit of the tpnct l0 register, 16-bit timer/event counter p counts up the external event count input (tipn0 pin input) when it is set in the external event count mode. in the external event count mode, an interrupt reques t (inttpncc0) is generated when the set value of the tpnccr0 register matches the value of the 16-bit co unter, and the value of the 16-bit counter is cleared. when a value is set to the tpnccrm register, it is transferred to the ccr0 buffer register, and is compared with the value of the 16-bit counter. the 16-bit counter cannot be cleared by using the tpnccr1 register. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register and is compared with the value of the 16-bit counter. as a result, an interrupt request (inttpncc1) is generated. by setting the tpnoe1 bit to 1, a si gnal can be output from the topn1 pin. rewriting the tpnccr0 register is enabled when tpnce = 1. when the tpnccr1 register is not used, it is recommended to set tpnccr1 to ffffh. remarks 1 . refer to 7.5.1 anytime write and reload about write operation of tpnccr0, tpnccr1 during timer operation (tpnce = 1). 2 . n = 0 to 3 caution 1. topn0 pin output in an external event count mode cannot be u sed. set to tpneee = 1by interval timer mode (tpnmd2 to 0 = 000b) when topn0 pin output in an external event count mode is used. 2. in external event count mode, when tpnccrm register value is set to 0000h the interrupt occurs after the overflow of the timer (ffffh to 0000h) chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 348 figure 7-8. flowchart of basic operation in external event count mode start 16-bit counter matches ccr0 buffer register. clear and start 16-bit counter. inttpncc0 occurs enable timer operation (tpnce = 1) transfer values of tpnccr0 and tpnccr1 to ccr0 buffer register and ccr1 buffer register 16-bit counter matches ccr1 buffer register note 2 . inttpncc1 occurs initial setting ? set external event count mode (tpnctl1: tpnmd2 to tpnmd0 = 001) note 1 . ? set valid edge (tpnioc2: tpnees1, tpnees0). ? set compare register (tpnccr0, tpnccr1). notes 1. selecting the tpneee bit has no effect. 2. the 16-bit counter is not cleared when it matches the ccr1 buffer register. remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 349 figure 7-9. timing of basic operation in external event count mode (1/2) (a) when d 1 > d 2 > d 3 , only tpnccr0 register value is rewritten, and topn1 is not output (tpnoe0 = 0, tpnoe1 = 0, tpnol0 = 0, tpnol1 = 1) tpnce = 1 d 1 d 1 d 2 d 1 0000h 0000h d 3 d 3 d 2 d 1 d 2 d 3 d 3 d 3 ffffh 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register remarks 1. d 1 , d 2 : set value of tpnccr0 register (0000h to ffffh) d 3 : set value of tpnccr1 register (0000h to ffffh) 2. whenever times of (set value of tpnccrm register +1) are detected, the compare match interrupt is generated (m = 0, 1) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 350 figure 7-9. timing of basic operation in external event count mode (2/2) (b) when d 1 = d 2 , tpnccr0 and tpnccr1 are not re written, and topn1 is output (tpnoe0 = 0, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 1) 0000h d 1 d 1 ffffh 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register 0000h d 2 d 2 tpnce = 1 d 1 = d 2 d 1 = d 2 d 1 = d 2 topn1 remarks 1. d 1 : set value of tpnccr0 register (0000h to ffffh) d 2 : set value of tpnccr1 register (0000h to ffffh) 2. whenever times of (set value of tpnccrm register +1) are detected, the compare match interrupt is generated (m = 0, 1) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 351 7.5.4 external trigger pulse output mode (tpnmd2 to tpnmd0 = 010) when tpnce = 1 in the external trig ger pulse output mode, the 16-bit coun ter keeps at ffffh and waits for input of an external trigger (input of tipn0 pin or set of tpne st bit). when the counter detects the trigger pulse input, it starts counting up. the duty factor of the signal output from the topn1 pin is set by a re load register (tpnccr1) and the period is set by a compare register (tpnccr0). in case of the software trigger mode, pulse of half cycl e setting by tpnccr0 register is outputted from topn0 terminal pin. rewriting the tpnccr0 and tpnccr1 registers is possible when tpnce = 1. to stop timer p, clear tpnce to o. if the edge of the exte rnal trigger (input of tipn0 pin or set tpnest bit) is detected more than once in the external trigger pulse output mode, the 16-bit counter is cl eared at the point of edge detection, and resumes counting up. then, topn0, topn1 terminal pin is initialized at the same time. caution 1. in the external trigger pulse output mode, select the internal clock (t pneee of tpnctl1 register = 0) as the count clock. 2. in the external trigger pulse output m ode, tpnccr0 and tpnccr1 registers are fixed as compare register. therefore, captu re function can not to use. remarks 1. for the reload operation when tpnccr0 and tpnccr1 are rewritten during timer operation, refer to 7.5.1 (2) reload. 2. n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 352 figure 7-10. flowchart of basic operation in external trigger pulse output mode start inttpncc0 occurs enable timer operation (tpnce = 1) transfer values of tpnccr0 and tpnccr1 to ccr0 buffer register and ccr1 buffer register 16-bit counter matches tpnccr0. clear and start 16-bit counter. 16-bit counter matches tpnccr1 note 2 . external trigger (tipn0 pin) input or tpnest = 1 16-bit counter starts counting inttpncc1 occurs initial setting external trigger (tipn0 pin) input clear and start 16-bit counter. ? select clock. (tpnctl1: tpneee = 0) (tpnctl0: tpncks2 to tpncks0) ? set external trigger pulse output mode. (tpnctl1: tpnmd2 to tpnmd0 = 010) ? set compare register. (tpnccr0, tpnccr1) note 1 notes: 1. tpnest bit of tpnctl1 register can be written during timer operation (tpnce = 1) 2. the 16-bit counter is not cleared wh en it matches the ccr1 buffer register. remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 353 figure 7-11. timing of basic operation in external trigger pulse output mode (tpnoe0 = 0, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 1) tpnce = 1 0000h d 01 d 11 d 01 d 02 d 12 d 01 d 02 d 02 ffffh 16-bit counter note d 11 d 12 0000h d 12 d 11 d 11 external trigger (tipn0 pin) tpnccr0 tpnccr1 ccr0 buffer register ccr1 buffer register topn1 note the 16-bit counter is not cleared when it matches the ccr1 buffer register. remarks 1. d 01 , d 02 : set value of tpnccr0 r egister (0000h to ffffh) d 11 , d 12 : set value of tpnccr1 r egister (0000h to ffffh) 2. duty of topn1 output = (set value of tpnccr1 r egister) / (set value of tp0ccr0 register +1) cycle topn1 output = (set value of tpnccr0 +1) (count clock cycle) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 354 7.5.5 one-shot pulse mode (tpnmd2 to tpnmd0 = 011) when tpnce is set to 1 in the one-shot pulse mode, the 16-b it counter waits for the setti ng of the tpnest bit (to 1) or a trigger that is input when the edge of the tipn0 pin is detected, while holding ffffh. when the trigger is input, the 16-bit counter starts counting up. when the value of the 16-bit counter matches the value of the ccr1 buffer register that has been transferred from t he tpnccr1 register, topn1 goes high. when the value of the 16-bit counter matches the value of the ccr0 buffer r egister that has been transferred from the tpnccr0 register, topn1 goes low, and the 16-bit counter is cleared to 0000h and stops. input of a second or subs equent trigger is ignored while the 16- bit counter is operating. be sure to input a second trigger while the 16-bit counter is stopped at 0000h. the waveform of the one-shot pulse is output from t he topn1 pin. the topn0 pin produces an active level output during counting by timer counter. active level is set by tpncl0 register. cautions: 1. select the internal cl ock (tpneee of the tpnctl1 register = 0) as the count clock in the one- shot pulse mode. 2. in the one-shot pulse mode, tpnccr0 and tp nccr1 registers are fixed as compare register. therefore, capture function can not to use. 3. in the one-shot pulse mode, when setting value of tpnccr1 re gister is bigger than setting value of tpnccr0 register, on-shot pulse is not outputted. remarks 1. in the one-shot pulse mode, tpnccr0 and tpnccr1 are rewritten during timer operation (tpnce=1). during timer operation (tpnce=1), for anytime write operation when rewriting of tpnccr0 and tpnccr1, refer to 7.5.1 (1) anytime write. 2. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 355 figure 7-12. flowchart of basic op eration in one-shot pulse mode start 16-bit counter matches ccr0 buffer register. clear 16-bit counter. input external trigger (tipn0 pin) or tpnest = 1 note 1 16-bit counter starts counting inttpncc0 occurs enable timer operation (tpnce = 1) transfer values of tpnccr0 and tpnccr1 to ccr0 buffer register and ccr1 buffer register 16-bit counter matches ccr1 buffer register note 2 . wait for trigger. 16-bit counter stands by at ffffh. wait for trigger. 16-bit counter stands by at 0000h. inttpncc1 occurs initial setting ? select clock. (tpnctl1: tpneee = 0) (tpnctl0: tpncks2 to tpncks0) ? set one-shot pulse mode. (tpnctl1: tpnmd2 to tpnmd0 = 011) ? set compare register. (tpnccr0, tpnccr1) notes: 1. only tpnest bit of tpnctl1 register can be written during timer operation (tpnce = 1). 2. the 16-bit counter is not cleared when it matches the ccr1 buffer register. caution the 16-bit counter is not cleared even if the trigger is input while the counter is counting up, and the trigger input is ignored. remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 356 figure 7-13. timing of basic oper ation in one-shot pulse mode (tpnoe0 = 0, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 0) tpnce = 1 tpnest = 1 d 1 d 0 d 1 d 0 d 1 d 0 d 0 d 0 d 1 d 1 ffffh 16-bit counter external trigger (tipn0 pin) tpnccr0 inttpncc0 tpnccr1 inttpncc1 ccr0 buffer register cc1 buffer register 0000h 0000h note topn0 topn1 note the 16-bit counter starts counting up either when tpnest = 1 or when tipn0 is input. remarks 1. d 0 : set value of tpnccr0 register (0000h to ffffh) d 1 : set value of tpnccr1 register (0000h to ffffh) 2. n = 0 to 3 3. 3. the active level term of topn1 pin output is: (s et value of tpnccr0 - set value of tpnccr1 +1) count clock cycle time of output delay = (set value of tpnccr1register) count clock cycle chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 357 7.5.6 pwm mode (tpnmd2 to tpnmd0 = 100) in the pwm mode, tmpn capture/compare register 1 (tpnccr1) is used to set the duty factor and tmpn capture/compare register 0 (tpn ccr0) is used to set the cycle. by using these two registers and operati ng the timer, variable-duty pwm is output. to stop timer p, clear tpnce to 0. the waveform of pw m is output from the topn1 pi n. the topn0 pin produces a pulse of half the pwm cycle. the tpnccr0 and tpnccr1 registers cann ot be used as capture registers. remark n = 0 to 3 for the reload operation when tpnccr0 and tpnccr1 are rewritten during timer operation (tpnce1=1), refer to 7.5.1 (2) reload . caution in the pwm mode, tpnccr0 and tpnccr1 regist ers are fixed as compare register. therefore, capture function can not to use. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 358 (1) operation flowchart of pwm mode figure 7-14. flowchart of basic operation in pwm mode (1/2) (a) when values of tpnccr0 and tpnccr1 regi sters are not rewritte n during timer operation start inttpncc0 occurs enable timer operation (tpnce = 1) transfer value of tpnccrm register to ccrm buffer register 16-bit counter matches ccr1 buffer register. topn1 outputs low level. 16-bit counter matches ccr0 buffer register. clear and start 16-bit counter. topn1 outputs high level. inttpncc1 occurs initial setting ? select clock. (tpnctl0: tpncks2 to tpncks0) ? set pwm mode. (tpnctl1: tpnmd2 to tpnmd0 = 100) ? set compare register. (tpnccr0, tpnccr1) remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 359 (2) operation flowchart of pwm mode (a) change of pulse width during operation when change of pwm waveform during operation, please write to tpnccr1 register at last. after write to tpnccr1 register, when write to tpnccr0 register again, please rewrite after detection of inttpncc1 signal. figure 7-14. flowchart of basic operation in pwm mode (2/2) (b) when values of tpnccr0 and tpnccr1 re gisters are rewritten during timer operation start inttpncc0 occurs 16-bit counter matches ccr1 buffer register. topn1 outputs low level. enable timer operation (tpnce = 1) transfer value of tpnccrm register to ccrm buffer register 16-bit counter matches tpnccr1. topn1 outputs low level. rewrite tpnccr0. rewrite tpnccr1. 16-bit counter matches tpnccr0. clear and start 16-bit counter. topn1 outputs high level. inttpncc1 occurs reload is enabled note <1> <2> <3> inttpncc0 occurs inttpncc1 occurs initial setting ? select clock. (tpnctl0: tpncks2 to tpncks0) ? set pwm mode. (tpnctl1: tpnmd2 to tpnmd0 = 100) ? set compare register. (tpnccr0, tpnccr1) ? ccr0 buffer register matches 16-bit counter. ? clear and start 16-bit counter. ? value of tpnccrm is reloaded to ccrm buffer register. note the timing of <2> may differ depending on the rewrite timing of <1> and <3> and the value of tpnccr1, but make sure that <3> comes after <1>. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 360 figure 7-15. timing of basic operation in pwm mode (1/2) (a) when rewriting value of tpnccr1 (tpnoe0 = 1, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 0) tpnce = 1 16-bit counter tpnccr0 tpnccr1 topn1 topn0 ccr0 buffer register ccr1 buffer register 0000h 0000h d 10 d 11 d 12 d 13 d 00 d 00 d 00 d 00 d 00 d 00 d 10 d 10 d 10 d 11 d 11 d 12 d 12 d 13 ffffh remarks 1. d 00 : set value of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : set value of tpnccr1 register (0000h to ffffh) 2. duty of topn1 output = (set value of tpnccr1 register +1)/(set value of tp0ccr0 register) cycle of topn1 output = (set value of tpnccr0 register +1)(count clock cycle) toggle width of topn0 output = (set value of tpnccr0 register + 1) (count clock period) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 361 figure 7-15. timing of basic operation in pwm mode (2/2) (b) when rewriting valu es of tpnccr0 and tpnccr1 (tpnoe0 = 1, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 0) tpnce = 1 16-bit counter tpnccr0 tpnccr1 topn1 topn0 0000h 0000h d 10 d 11 d 12 d 12 d 00 d 00 d 10 d 10 d 11 d 11 d 11 d 12 d 12 d 12 d 00 d 01 d 02 d 03 d 01 d 01 d 01 d 02 d 02 d 03 ffffh same value write note note ccr0 buffer register ccr1 buffer register note no value is reloaded because the tpnccr1 register is not rewritten. remarks 1. d 00 , d 01 , d 02 , d 03 : set value of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : set value of tpnccr1 register (0000h to ffffh) 2. duty of topn1 output = (set value of tpnccr1 register +1)/(set value of tp0ccr0 register) cycle of topn1 output = (set value of tpnccr0 register +1)(count clock cycle) toggle width of topn0 output = (set value of tpnccr0 register + 1) (count clock cycle) 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 362 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 8 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 8 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 363 7.5.7 free-running mode (tpnmd2 to tpnmd0 = 101) in the free-running mode, the 16-bit counter free-runs, and the bit that selects the c apture or compare register function can be select by the setting of the tpnccs1 and tpnccs0 bits. setting of the tpnccs1 and tpnccs0 bits of the tpno pt0 register is valid only in the free-running mode. tpnccs1 operation 0 tpnccr1 register is used as compare register. 1 tpnccr1 register is used as capture register. tpnccs0 operation 0 tpnccr0 register is used as compare register. 1 tpnccr0 register is used as capture register. ? when tpnccr1 register is used as compare register when the value of the 16-bit counter ma tches the value of the ccr0 buffer register in the free-running mode, an interrupt is generated. tpnccr1 register is enabled for write operation when tpnce=1. any data is set to tpnccr1 register by anytime write, data is translated to ccr1 buffer register, and data become comparison value with value of the 16 bit counter. if timer output (topn0) is enabled, topn0 produces a toggle output when the value of the 16-bit counter matches the value of the ccr0 buffer register. ? when tpnccr1 register is used as capture register the value of the 16-bit counter is stored in the tpnccr 1 register when the edge of t he tipn1 pin is detected. ? when tpnccr0 register is used as compare register when the value of the 16-bit counter ma tches the value of the ccr1 buffer register in the free-running mode, an interrupt is generated. tpnccr0 register is enabled for write operation when tpnce=1. any data is set to tpnccr0 register by anytime write, data is translated to ccr1 buffer register, and data become comparison value with value of the 16 bit counter. if timer output (topn0) is enabled, topn0 produces a toggle output when the value of the 16-bit counter matches the value of the ccr0 buffer register. ? when tpnccr0 register is used as capture register the value of the 16-bit counter is stored in the tpnccr 0 register when the edge of t he tipn0 pin is detected. caution: external event count input as count cl ock (tpnctrl.tpneee=1), tp nccr0 register can not to use as capture register. remark : using tpnccr0 and tpnccr1 register as a com pare register, the writt en operation at timer operation (tpnce = 1) refer to 7. 5. 1 (1) anytime write. caution: at free running mode, count clear operati on is not used by compare register matches. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 364 figure 7-16. flowchart of basic operation in free-running mode start set tpnccs1 and tpnccs0. initial setting enable timer operation (tpnce = 1) transfer values of tpnccr0 and tpnccr1 to ccr0 buffer register and ccr1 buffer register enable timer operation (tpnce = 1) transfer values of tpnccr1 to ccr1 buffer register ccr1 buffer register matches 16-bit counter. ccr1 buffer register matches 16-bit counter. ccr0 buffer register matches 16-bit counter. edge of tipn0 is detected. value of 16-bit counter is captured to tpnccr0. 16-bit counter overflows. 16-bit counter overflows. set detection of edge of tipn0 (tpnis1, tpnis0). enable timer operation (tpnce = 1) transfer values of tpnccr0 to ccr0 buffer register edge of tipn1 is detected. value of 16-bit counter is captured to tpnccr1. edge of tipn1 is detected. value of 16-bit counter is captured to tpnccr1. edge of tipn0 is detected. value of 16-bit counter is captured to tpnccr0. ccr0 buffer register matches 16-bit counter. 16-bit counter overflows. 16-bit counter overflows. set detection of edge of tipn1 (tpnis3, tpnis2). enable timer operation (tpnce = 1) set detection of edge of tipn1 and tipn0 (tpnis3 to tpnis0). tpnccs1 = 0 tpnccs0 = 0 tpnccs1 = 0 tpnccs0 = 1 tpnccs1 = 1 tpnccs0 = 0 tpnccs1 = 1 tpnccs0 = 1 ? select clock. (tpnctl0: tpncks2 to tpncks0) ? set free-running mode. (tpnctl1: tpnmd2 to tpnmd0 = 101) remark n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 365 (1) when tpnccs1 = 0 and tpnccs0 = 0 (compare function) when tpnce is set to 1, the 16-bit counter counts fr om 0000h to ffffh, and continues counting up in the free-running mode until tpnce is cleared to 0. if a val ue is written to the tpnccr0 and tpnccr1 registers in this mode, it is transferred to the ccr0 and ccr1 buffer registers (anytime write). even if a one-shot pulse trigger is input in this mode, a one-shot pulse is not generated. if tpnoem is set to 1, topnm produces a toggle output when the value of the 16-bit counter matches the value of the ccrm buffer register. remark n = 0 to 3 m = 0, 1 figure 7-17. timing of basic operation in free-running mode (tpnccs1 = 0, tpnccs0 = 0) (tpnoe0 = 1, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 0) tpnce = 1 0000h d 00 d 00 d 00 d 00 d 11 d 11 d 01 d 01 d 01 ffffh 16-bit counter tpnccr0 topn0 topn1 inttpnov tpnovf clear by writing 0 to tpnovf clear by writing 0 to tpnovf inttpncc0 match interrupt inttpncc1 match interrupt tpnccr1 ccr0 buffer register ccr1 buffer register 0000h d 10 d 10 d 10 d 11 d 11 remarks 1. d 00 , d 01 : set value of tpnccr0 r egister (0000h to ffffh) d 10 , d 11 : set value of tpnccr1 r egister (0000h to ffffh) 2. toggle width of topn0 output = (set value of tpnccr0 register) (count clock cycle) toggle width of topn1 output = (set value of tpnccr1 register) 3. topnm output goes high when counting is started. 4. n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 366 (2) when tpnccs1 = 1 and tpn ccs0 = 1 (capture function) when tpnce is set to 1, the 16-bi t counter counts from 0000h to ffffh , and continues counting up in the free-running mode until tpnce is cleared to 0. the valu e captured by the capture trigger is written to the tpnccr0 and tpnccr1 registers. capturing close to an overflow (ffffh) is j udged using the overflow flag (tpnovf). however, if the interval of the captur e trigger is such that the overflow o ccurs twice (two or more cycles of free- running); the tpnovf flag cannot be used for judgment. figure 7-18. timing of basic operation in free-running mode (tpnccs1 = 1, tpnccs0 = 1) (tpnoe0 = 1, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 0) tpnce = 1 d 00 d 10 d 11 d 12 d 00 d 01 d 03 d 02 d 12 d 11 d 10 d 02 d 03 d 01 ffffh 0000h 0000h 16-bit counter tpnccr0 tipn1 tipn0 inttpnov inttpncc0 match interrupt inttpncc1 match interrupt tpnccr1 topn1 topn0 l l remarks 1. d 00 , d 01 , d 02 , d 03 : value captured to tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : value captured to tpnccr1 register (0000h to ffffh) 2. tipn0: rising edge is detected (tpnis1, tpnis0 = 01). tipn1: falling edge is detected (tpnis3, tpnis2 = 10). 3. n = 0 to 3 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 367 (3) when tpnccs1 = 0 and tpnccs0 = 1 when tpnce is set to 1, the 16-bi t counter counts from 0000h to ffffh , and continues counting up in the free-running mode until tpnce is cleared to 0. the tpnc cr1 register is used as a compare register. as an interval function, an interrupt signal is output when the va lue of the 16-bit counter ma tches the set value of the tpnccr1 register. if tpnoe1 is set to 1, topn1 pr oduces a toggle output when the value of the 16-bit counter matches the set value of the tpnccr1 register. figure 7-19. timing of basic operation in free-running mode (tpnccs1 = 0, tpnccs0 = 1) (tpnoe0 = 1, tpnoe1 = 1, tpnol0 = 0, tpnol1 = 0) tpnce = 1 d 00 d 11 d 11 d 10 d 10 d 12 d 12 d 10 d 01 d 11 d 02 d 12 d 03 d 11 d 00 d 02 d 03 d 01 ffffh 0000h 0000h 16-bit counter tpnccr0 topn1 tipn0 topn0 l inttpnov inttpncc0 match interrupt inttpncc1 match interrupt tpnccr1 ccr1 buffer register remarks 1. d 00 , d 01 , d 02 , d 03 : value captured to tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : value captured to tpnccr1 register (0000h to ffffh) 2. tipn0: falling edge is detected (tpnis1, tpnis0 = 10). 3. n = 0 to 3 (4) overflow flag when the counter overflows from ffffh to 0000h in t he free-running mode, the overflow flag (tpnovf) is set to 1, and an overflow interrupt (inttpnov) is generated. after generation of the overflow interrupt (inttpnov), be sure to check if the overflow flag (tpnovf) is set to 1. the overflow flag is cleared by the cpu by writing 0 to it. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 368 7.5.8 pulse width measurement m ode (tpnmd2 to tpnmd0 = 110) in the pulse width measurement mode, free-running counting is performed. the value of the 16-bit counter is captured to capture register 0 (tpn ccr0) when both the rising and falling edges of the tipn0 pin are detected, and the 16-bit counter is cleared to 0000h. in this way, the external input pulse width can be measured. to measure a long pulse width that exceeds the overflow of the 16-bit counter, use the overflow flag for detection. for measurement a pulse width that c auses overflow to occur twice or more, please count number with overflow interrupt, etc. when the edge of the tip n1 pin is detected, the value of the 16-bi t counter is stored in capture register 1 (tpnccr1), and the 16-bit counter is cleared. caution in the pulse width measurement mode, select the internal clock (tpneee of the tpnctl1 register = 0) as the count clock. figure 7-20. flowchart of basic operat ion in pulse width measurement mode start set edge detection of tipn1/tipn0 note . (tpnis3 to tpnis0) input rising edge of pulse to tipnm. capture value to tpnccrm. clear and start 16-bit counter. input falling edge of pulse to tipnm. capture value to tpnccrm. clear and start 16-bit counter. enable timer operation (tpnce = 1). initial setting select clock. (tpnctl0: tpncks2 to tpncks0) set pulse width measurement mode. (tpnctl1: tpnmd2 to tpnmd0 = 110) set compare register. (tpnccr0, tpnccr1) note an external pulse can be input from either tipn0 or ti pn1. only one of them can be used. specify that both the rising and falling edges are detect ed. specify that the input edge of an external pulse input that is not used is not detected. remark n = 0 to 3 m = 0, 1 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 369 figure 7-21. timing of basic operati on in pulse width measurement mode (tpnoe0 = 0, tpnoe1 = 0, tpnol0 = 0, tpnol1 = 0) tpnce = 1 0000h d 01 d 00 d 00 d 01 d 02 d 03 d 02 d 03 ffffh 16-bit counter tipn0 inttpncc0 tpnovf inttpnov tpnccr0 ffffh cleared by writing 0 from cpu remarks 1. d 00 , d 01 , d 02 , d 03 : value captured to tpnccr0 register (0000h to ffffh) 2. tipn0: both the rising and falling e dges are detected (tpnis1, tpnis0 = 11). 3. n = 0 to 34. 4. pulse width = captured value count clock cycle if the valid edge is not input to the tipnm pin even when the 16-bit count er counted up to ffffh, an overflow interrupt request signal (inttpnov) is genera ted at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pulse width can be calculated as follows. pulse width = (10000h tpnovf bit set (1) count + captured value) count clock cycle chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 370 7.6 timer synchronized operation function timer p and timer q have a timer synchroniz ed operation function (tuned operation mode). the timers that can be synchronized are listed in table 7-3. table 7-3. tuned operation mode of timers master timer slave timer tmp0 tmp1 ? tmp2 tmp3 tmq0 tmq1 tmq2 ? cautions 1. the tuned oper ation mode is enabled or disabled by the tpmsye bit of the tpmctl1 register and tqnsye bit of the tqnctl1 register. for tmp2, either or both tmp3 and tmq0 can be specified as slaves. 2. set the tuned operation mode using the following procedure. <1> set the tpmsye bit of the tpmctl1 regi ster and the tqnsye bit of the tqnctl1 register of the slave timer to enable the tuned operation. set the tpmmd2 to tpmmd0 bits of the tp mctl1 register and tqnm d2 to tqnmd0 bits of the tqnctl1 register of the sl ave timer to the free-running mode. <2> set the timer mode by using the tpnmd2 to tpnmd0 bits of the tpnctl1 register and the tpnmd2 to tpnmd0 bits of the tqnctl1 register. at this time, do not set the tpnsye bit of the tpnctl1 register and the tqnsye bit of the tqnctl1 register of the master timer. <3> set the compare register value of the master and slave timers. <4> set the tpmce bit of the tpmctl0 register and the tqnce bit of the tqnctl0 register of the slave timer to enable operati on on the internal operating clock. <5> set the tpnce bit of the tpnctl0 register and the tqnce bit of the tqnctl0 register of the master timer to enable operati on on the internal operating clock. remark n = 1, 3, m = 0, 2 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 371 tables 7-4 and 7-5 show the timer modes that can be used in the tuned operation mode ( : settable, : not settable). table 7-4. timer modes usable in tuned operation mode master timer free-running mode pwm mode triangular wave pwm mode tmp0 tmp2 tmq1 table 7-5. timer output functions free-running mode pwm mode triangular wave pwm mode tuned channel timer pin tuning off tuning on tuning off tuning on tuning off tuning on top00 ppg toggle n/a tmp0 (master) top01 ppg pwm n/a top10 ppg toggle pwm n/a ch0 tmp1 (slave) top11 ppg pwm n/a top20 ppg toggle pwm n/a tmp2 (master) top21 ppg pwm n/a top30 ppg toggle pwm n/a ch1 tmp3 (slave) top31 ppg pwm n/a toq00 ppg toggle pwm toggle n/a ch1 tmq0 (slave) toq01 to toq03 ppg pwm triangular wave pwm n/a toq10 ppg toggle toggle tmq1 (master) toq11 to toq13 ppg pwm triangular wave pwm toq20 ppg toggle toggle triangular wave pwm ch2 tmq2 (slave) toq21 to toq23 ppg pwm triangular wave pwm remark the timing of transmitting data from t he compare register of the master timer to the compare register of the slave timer is as follows. ppg: cpu write timing toggle, pwm, triangular wave pwm: timing at wh ich timer counter and compare register match topn0 and toqm0 (n = 0 to 3, m = 0 to 2) chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 372 figure 7-22. tuned operation image (tmp2, tmp3, tmq0) tmp2 tmp2 (master) + tmp3 (slave) + tmq0 (slave) top21 (pwm output) 16-bit timer/counter unit operation tuned operation five pwm outputs are available when pwm is operated as a single unit. 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare tmp3 top31 (pwm output) tmq0 toq01 (pwm output) toq02 (pwm output) toq03 (pwm output) top21 (pwm output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top30 (pwm output) 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top31 (pwm output) toq01 (pwm output) toq00 (pwm output) toq02 (pwm output) toq03 (pwm output) seven pwm outputs are available when pwm is operated in tuned operation mode. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 373 figure 7-23. basic operation timing of tuned pwm function (tmp2, tmp3, tmq0) top20 top21 top30 toq00 toq01 toq02 toq03 top31 tp2ccr0 tp2ce inttp2cc0 match interrupt inttp2cc1 match interrupt inttp3cc0 match interrupt inttp3cc1 match interrupt inttq0cc0 match interrupt inttq0cc1 match interrupt inttq0cc2 match interrupt inttq0cc3 match interrupt tp3ce tq0ce ffffh 0000h tmp2 16-bit counter d 00 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 tp2ccr1 d 10 tp3ccr0 d 20 tp3ccr1 d 30 tq0ccr0 d 40 tq0ccr1 d 50 tq0ccr2 d 60 tq0ccr3 d 70 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 374 7.7 selector function in the v850es/fx2, the tip input/rxda input and the tip input/tsout signal can be used to select the capture trigger input of tmp. by using this function, the following is possible. ? the tip00 and tip01 input signals can be selected from the port/timer alternate-function pins (tip00 and tip01 pins) and the tsout signal of the can controller. if the tsout signal of can0 or can1 is selected, t he time stamp function of t he can controller can be used. ? the tip10 and tip11 input signals of tmp1 can be sele cted from the port/timer alte rnate-function pins (tip10 and tip11 pins) and the uarta reception alternate-fu nction pins (rxda0 and rxda1). the tip30 and tip31 input signals of tmp3 can be sele cted from a port/timer alternate-functi on pin (tip30 and tip31 pins) and the uarta reception alternate function pin (rxda2 and rxda3). when the rxda0, rxda1, rxda2 or rxda3 signal of uart0, uart1, uart2 or uart3 is selected, the lin reception transfer rate and baud rate error of uarta can be calculated. cautions 1. when using the selector function, set the capture trigger input of tmp before connecting the timer. 2. when setting the selector function, firs t disable the peripheral i/o to be connected (tmp/uarta or tmp/can controller). the capture input for the selector functi on is specified by the following register. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 375 (1) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that selects the capture trigger for tmpn. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff308h (i) v850es/fe2, v850es/ff2, v850es/fg2 7 6 5 4 3 2 1 0 selcnt0 0 0 0 isel04 isel03 isel02 0 isel00 (ii) v850es/fj2: pd70f3237 7 6 5 4 3 2 1 0 selcnt0 0 0 isel05 isel04 isel03 isel02 isel01 isel00 (iii) v850es/fj2: pd70f3238, pd70f3239 7 6 5 4 3 2 1 0 selcnt0 0 isel06 isel05 isel04 isel03 isel02 isel01 isel00 isel06 selection of tip31 input signal (tmp3) 0 tip31 pin input 1 rxda3 pin input isel05 selection of tip30 input signal (tmp3) 0 tip30 pin input 1 rxda2 pin input isel04 selection of tip11 input signal (tmp1) 0 tip11 pin input 1 rxda1 pin input isel03 selection of tip10 input signal (tmp1) 0 tip10 pin input 1 rxda0 pin input isel02 note selection of tip01 input signal (tmp0) 0 signal selected by isel01 bit 1 inttm0eq0 interrupt of tmm0 isel01 selection of tip01 input signal (tmp0) 0 tip01 pin input 1 tsout signal of can1 isel00 selection of tip00 input signal (tmp0) 0 tip00 pin input 1 tsout signal of can0 chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 376 note use the inttm0eq0 interrupt signal as the tip01 input signal in the following range. tmm operation clock cycle tmp operation clock cycle 4 cautions 1. to set the isel06 to isel00 bits to 1, set the corresponding pin in the capture input mode. 2. set tmp0 and can0 after prohibiting operating when you set the isel00 bit. set tmp0 and can1 after prohibiting op erating when you set the isel01 bit. set tmp0 and tmm0 after prohibiting operating when you set the isel02 bit. set tmp1 and uarta0 after prohibiting operating when you set the isel03 bit. set tmp1 and uarta1 after prohibiting operating when you set the isel04 bit. set tmp3 and uarta2 after prohibiting operating when you set the isel05 bit. set tmp3 and uarta3 after prohibiting operating when you set the isel06 bit. (2) selector operation control register 1 (selcnt1) the selcnt1 register is an 8-bit register th at selects the capture trigger for tmpn. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. this register is incorporated only in the pd70f3238 and pd70f3239. after reset: 00h r/w address: fffff30ah (i) v850es/fj2: pd70f3238, pd70f3239 7 6 5 4 3 2 1 0 selcnt1 0 0 0 0 0 0 isel11 isel10 isel11 note selection of tip21 input signal (tmp2) 0 tip21 pin input 1 tsout signal of can3 isel10 note selection of tip20 input signal (tmp2) 0 tip20 pin input 1 tsout signal of can2 note the pd70f3237 does not have the can3 and can2 functions. fix the isel11 and isel10 bits of these products to 0. cautions 1. to set the isel11 and isel 10 bits to 1, set the corresponding pin in the capture input mode. 2. set tmp2 and can2 after prohibi ting operating when you set the isel10 bit. set tmp2 and can3 after prohibiting operating when you set the isel11 bit. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 377 7. 8 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tpnccr0 and tpnccr1 r egisters if the capture trigger is input until operation start of count clock after the tpnce bit is set to 1. (a)free running timer mode count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0002h 0000h tipn0 pin input capture trigger 16 ? bit counter sampling clock capture trigger input (b)pulse mode count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0001h 0000h tipn0 pin input capture trigger 16 bit counter sumpling clock caputure torigger input chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 378 (2) notes on rewriting the tpnccr0 register to change the value of the tpnccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) remark n = 0 to 3 if the value of the tpnccr0 register is changed from d1 to d2 while the count value is greater than d2 but less than d1, the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d2. because the count value has alre ady exceeded d2, however, the 16-bit counter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d2, the inttpncc0 signal is generated. therefore, the inttpncc0 signal may not be generated at the valid edge count of ?(d1 + 1) times? or ?(d2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d2 + 1) times?. chapter 7 16-bit timer/event counter p user?s manual u17830ee1v0um00 379 (3) clearing overflow flag the overflow flag can be cleared to 0 by clearing t he tpnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tpnopt0 register. to accurately detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow fl ag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tpnovf bit) overflow flag (tpnovf bit) l h l remark n = 0 to 3 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. user?s manual u17830ee1v0um00 380 chapter 8 16-bit timer/event counter q the v850es/fe2, v850es/ff2, v850es/fg2, and v850es/fj2 include 16-bit timer/event counter q. the number of channels of timer q (tmq) differs depending on the product. table 8-1. number of channels of timer q product number of channels v850es/fe2 v850es/ff2 1 (tmq0) v850es/fg2 2 (tmq0, tmq1) v850es/fj2 3 (tmq0, tmq1, timq2) 8.1 features timer q (tmq) is a 16-bit timer/event c ounter that can be used in various ways. tmq can perform the following operations. ? pwm output ? interval timer ? external event counter (operation disabled when clock is stopped) ? one-shot pulse output ? pulse width measurement function ? triangular wave pwm output ? timer synchronized operation function ? external trigger pulse output function ? free-running function 8.2 functional outline ? capture trigger input signal 4 ? external trigger input signal 1 ? clock selection 8 ? external event count input 1 ? readable counter 1 ? capture/compare reload register 4 ? capture/compare match interrupt 4 ? timer output (toqn0 to toqn3) 4 remark n = 0 (v850es/fe2, v850es/ff2) n = 0,1 (v850es/fg2) n = 0 to 2 (v850es/fj2) this chapter explains the case where n = 0 to 2. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 381 8.3 configuration tmq consists of the following hardware. table 8-2. configuration of tmq0 to tmq2 item configuration timer register 16-bit counter registers tmqn capture/compare registers 0 to 3 (tqnccr0 to tqnccr3) tmqn counter read buffer register (tqncnt) ccr0 buffer register to ccr3 buffer register timer inputs 4 (tiqn0 note to tiqn3) timer outputs 2 (toqn0 to toqn3) control registers tmqn timer control registers 0, 1 (tqnctl0, tqnctl1) tmqn timer dedicated i/o control registers 0 to 2 (tqnioc0 to tqnioc2) tmqn timer option register 0 (tqnopt0) tiqnm pin noise elimination control register (qnmnfc) note tiqn0 functions alternately as a capt ure trigger input signal, external trigger input signal, and external event count input signal. remark n = 0 to 2, m = 0 to 3 the pins of tmq function alternately as port pins. for how to set the alternate function, refer to the description of the registers in chapter 4 port functions . table 8-3. tmq pin list pin name alternate-function pin i/o function tiq00 p53/kr3/toq00/ddo tiq01 p50/kr0/toq01 tiq02 p51/kr1/toq02 tiq03 p52/kr2/toq03/ddi external event/clock input (tmq0) tiq10 p95/toq10 tiq11 p92/toq11 tiq12 p93/toq12 tiq13 p94/toq13 external event/clock input (tmq1) tiq20 p610/toq20 tiq21 p611/toq21 tiq22 p612/toq22 tiq23 p613/toq23 input external event/clock input (tmq2) toq00 p53/kr3/tiq00/ddo toq01 p50/kr0/tiq01 toq02 p51/kr1/tiq02 toq03 p52/kr2/tiq03/ddi timer output (tmq0) toq10 p95/tiq10 toq11 p92/tiq11 toq12 p93/tiq12 toq13 p94/tiq13 timer output (tmq1) toq20 p610/tiq20 toq21 p611/tiq21 toq22 p612/tiq22 toq23 p613/tiq23 output timer output (tmq2) chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 382 figure 8-1. block diagram of timer q internal bus tqnccr0 tqnccr1 counter control trigger control 16-bit counter tqncnt clear 16-bit counter ccr0 buffer register ccr1 buffer register edge detector edge detector edge detector edge detector edge detector edge detector tqnctl1 tqnsye tqnest tqneee tqnmd2 tqnmd1 tqnmd0 tqnopt0 tqnccs4 to tqnccs0 tqnovf tqnioc1 tqnis7 to tqnis0 tqnioc0 tqnol3 to tqnol0 tqnoe3 to tqnoe0 tqnce tqnce inttqncc0 tqnctl0 tqnce tqncks2 tqncks1 tqncks0 tqnioc2 tqness1 tqness0 tqnets1 tqnets0 selector selector f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector internal bus load load inttqnov inttqnov inttqncc1 inttqncc2 inttqncc3 toqn0 tqnccr2 ccr2 buffer register selector load 16-bit counter tqnccr3 output controller ccr3 buffer register capture/compare selection function selector load tiqn0 tiqn3 tiqn2 tiqn1 toqn1 toqn2 toqn3 remark n = 0 to 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 383 (1) tmqn capture/compare register 0 (tqnccr0) the tqnccr0 register is a 16-bit register that has a capture function and a compare function. a capture register or a compare r egister behavior can be set by the setting of tqnccs0 bit only in the free- running mode. in the pulse width measurement mode, this regi ster functions only as a capture register. in all the modes other than the free-running mode and pu lse width measurement mode, this register functions as a compare register. in the default status, the tqnccr0 regi ster functions as a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: tq0ccr0: fffff546h, tq1ccr0: fffff616h, tq2ccr0: fffff626h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tqnccr0 (n = 0 to 2) ? when used as compare register tqnccr0 can be rewritten when tqnce = 1. each operation mode and capture/ compare register functions and th e method of writing the compare register are as follows. tmq operation mode method of writing tqnccr0 register pwm output mode, external trigger pulse output mode, or triangular wave pwm mode reload free-running mode, external event count mode, one-shot pulse mode, or interval timer mode anytime write pulse width measurement mode cannot be written because used only as capture register ? when used as capture register the count value is stored in tqnccr0 on detection of the edge of the captur e trigger (tiqn0) input. caution: at subclock operated and at main clock stopped, the access to tqnccr0 register is prohibited. for details, refer to 3. 4. 10 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 384 (2) tmqn capture/compare register 1 (tqnccr1) the tqnccr1 register is a 16-bit register that has a capture function and a compare function. a capture register or a compare register behavior can be specified by setting the tqnccs1 bit of the tqnopt0 register only in the free-running mode. in the pulse width measurement mode, this r egister functions only as a capture register. in all the modes other than the free-running mode and pu lse width measurement mode, this register functions as a compare register. reset input clears this register to 0000h. after reset: 0000h r/w address: tq0ccr1: fffff548h, tq1ccr1: fffff618h, tq2ccr1: fffff628h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tqnccr1 (n = 0 to 2) ? when used as compare register tqnccr1 can be rewritten when tqnce = 1. each operation mode and capture/ compare register functions and th e method of writing the compare register are as follows. tmq operation mode method of writing tqnccr1 register pwm output mode, external trigger pulse output mode, or triangular wave pwm mode reload free-running mode, external event count mode, one-shot pulse mode, or interval timer mode anytime write pulse width measurement mode cannot be written because used only as capture register ? when used as capture register the count value is stored in tqnccr1 on detection of the edge of the captur e trigger (tiqn1) input. caution: at subclock operated and at main clock stopped, the access to tqnccr1 register is prohibited. for details, refer to 3. 4. 10 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 385 (3) tmqn capture/compare register 2 (tqnccr2) the tqnccr2 register is a 16-bit register that has a capture function and a compare function. a capture register or a compare register behavior can be specified by setting the tqnccs2 bit of the tqnopt0 register only in the free-running mode. in the pulse width measurement mode, this r egister functions only as a capture register. in all the modes other than the free-running mode and pu lse width measurement mode, this register functions as a compare register. in the default status, the tqnccr2 regi ster functions as a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: tq 0ccr2: fffff54ah, tq1ccr2: fffff61ah, tq2ccr2: fffff62ah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tqnccr2 (n = 0 to 2) ? when used as compare register tqnccr2 can be rewritten when tqnce = 1. each operation mode and capture/ compare register functions and th e method of writing the compare register are as follows. tmq operation mode method of writing tqnccr2 register pwm output mode, external trigger pulse output mode, or triangular wave pwm mode reload free-running mode, external event count mode, one-shot pulse mode, or interval timer mode anytime write pulse width measurement mode cannot be written because used only as capture register ? when used as capture register the count value is stored in tqnccr2 on detection of the edge of the captur e trigger (tiqn2) input. caution: at subclock operated and at main clock stopped, the access to tqnccr1 register is prohibited. for details, refer to 3. 4. 10 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 386 (4) tmqn capture/compare register 3 (tqnccr3) the tqnccr3 register is a 16-bit register that has a capture function and a compare function. a capture register or a compare regi ster can be specified by setting the tq nccs3 bit of the tqnopt0 register only in the free-running mode. in the pulse width measurement mode, this r egister functions only as a capture register. in all the modes other than the free-running mode and pu lse width measurement mode, this register functions as a compare register. in the default status, the tqnccr3 regi ster functions as a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: tq0ccr3: fffff54ch, tq1ccr3: fffff61ch, tq2ccr3: fffff62ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tqnccr3 (n = 0 to 2) ? when used as compare register tqnccr3 can be rewritten when tqnce = 1. each operation mode and capture/ compare register functions and th e method of writing the compare register are as follows. tmq operation mode method of writing tqnccr3 register pwm output mode, external trigger pulse output mode, or triangular wave pwm mode reload free-running mode, external event count mode, one-shot pulse mode, or interval timer mode anytime write pulse width measurement mode cannot be written because used only as capture register ? when used as capture register the count value is stored in tqnccr3 on detection of the edge of the captur e trigger (tiqn3) input. caution: at subclock operated and at main clock stopped, the access to tqnccr1 register is prohibited. for details, refer to 3. 4. 10 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 387 (5) tmqn counter read buffer register (tqncnt) the tqncnt register is a read buffer register that can read the value of the 16-bit counter. this register is read-only, in 16-bit units. reset input clears this register to ffffh. when tqnce bit = 0, the tqncnt register is 000h. at this time if tqncnt r egister is read, the value of 16-bit counter is not read and 0000h is read as it is. if this register is read, the count value of 16-bit counter can be read when tqnce = 1. after reset: ffffh r address: tq0cnt: fffff54eh, tq1cnt: fffff61eh, tq2cnt: fffff62eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tqncnt (n = 0 to 2) caution: at subclock operated a nd at main clock stopped, the access to tqnccr1 register is prohibited. for details , refer to 3. 4. 10 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 388 8.4 control registers (1) tmqn control register 0 (tqnctl0) the tqnctl0 register is an 8-bit register that controls the operation of timer q. this register can be read or written in 8-bit or 1-bit units. reset input clears this register of default value to 00h. rewriting the tqnctl0 register is prohibited while operating (tqnce = 1). however, only the tqnce bit can be rewritten at any time. (1/2) after reset: 00h r/w address: tq0ctl0: fffff540h, tq1ctl0: fffff610h, tq2ctl0: fffff620h 7 6 5 4 3 2 1 0 tqnctl0 tqnce 0 0 0 0 tqncks2 tqncks1 tqncks0 (n = 0 to 2) tqnce control of operation of timer qn 0 disable internal operating clock o peration (asynchronously reset tmqn). 1 enable internal operating clock operation. the tqnce bit controls the internal operating cloc k and asynchronously resets tmqn. when this bit is cleared to 0, the internal operating clock of tmqn is stopped (fixed to the low level), and tmqn is asynchronously reset. when the tqnce bit is set to 1, the internal oper ating clock is enabled within 2 input clocks, and tmqn counts up. tqncks2 tqncks1 tqncks0 selection of internal count clock 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /8 1 0 0 f xx /16 1 0 1 f xx /32 1 1 0 f xx /64 1 1 1 f xx /128 cautions: 1. set the tqncks2 to tqncks0 bits when tqnce = 0. when the tqnce bit setting is changed from 0 to 1, the tqncks2 to tqncks0 bits can be set at the same time. 2. be sure to clear bit 3 to bit 6 to 0. remark f xx : main system clock frequency chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 389 (2/2) resolution and maximum count time resolution [ s] maximum count time [ms] internal count clock f xx = 16 mhz f xx = 20 mhz f xx = 16 mhz f xx = 20 mhz f xx 0.0625 0.050 4.10 3.28 f xx /2 0.125 0.100 8.19 6.55 f xx /4 0.250 0.200 16.38 13.11 f xx /8 0.500 0.400 32.77 26.21 f xx /16 1.000 0.800 65.54 52.43 f xx /32 2.000 1.600 131.11 104.86 f xx /64 4.000 3.200 262.14 209.72 f xx /128 8.000 6.400 524.29 419.43 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 390 (2) tmqn timer control register 1 (tqnctl1) the tqnctl1 register is an 8-bit register that controls the operation of timer q. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. (1/2) after reset: 00h r/w address: tq0ctl1: fffff541h, tq1ctl1: fffff611h, tq2ctl1: fffff621h 7 6 5 4 3 2 1 0 tqnctl1 tqnsye tqnest tqneee 0 0 tqnmd2 tqnmd1 tqnmd0 (n = 0 to 2) tqnsye tuned operation mode enable 0 independent operation mode (asynchronous operation mode) 1 tuned operation mode (specification of slave operation) in this mode, timer q can operate in synchronization with a master timer. master timer slave timer tmp2 tmp3 tmq0 tmq1 tmq2 ? for the tuned operation mode, refer to 8.6 timer synchronized operation function . tqnest software trigger control 0 no operation 1 in one-shot pulse mode: one-shot pulse software trigger in external trigger pulse output mode: pulse output software trigger the tqnest bit functions as a software trigger in the one-shot pulse mode or external trigger pulse output mode (this bit is invalid in any other mode). by setting tqnest to 1 when tqnce = 1, a software trigger is issued. therefore, be sure to set tqnest to 1 when tqnce = 1. the tiqn0 pin is used for an external trigger. t he read value of the tqnest bit is always 0. tqneee selection of count clock 0 internal clock (clock selected by tqncks2 to tqncks0 bits) 1 external event count input (edge of input to tiqn0) the valid edge is specified by the tqnees1 and tqnees0 bits when tqneee = 1 (external event count input: tiqn0). chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 391 (2/2) tqnmd2 tqnmd1 tqnmd0 selection of timer mode 0 0 0 interval timer mode 0 0 1 external event count mode 0 1 0 external trigger pulse output mode 0 1 1 one-shot pulse mode 1 0 0 pwm mode 1 0 1 free-running mode 1 1 0 pulse width measurement mode 1 1 1 triangular wave pwm mode cautions 1. set the tqneee and tqnmd2 to tqnmd0 bits when tqnce = 0 (the same value can be written when tqnce = 1). if these bits are rewritten when tqnce = 1, the operation cannot be guaranteed. if these bits are rewritten by mistake , clear tqnce to 0 and then set them again. 2. the external event count input is selected regardless of the value of the tqneee bit at an external event count mode. 3. be sure to clear bits 3 and 4 to 0. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 392 (3) tmqn timer dedicated i/o control register 0 (tqnioc0) the tqnioc0 register is an 8-bit regi ster that controls the timer outputs. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tq0ioc0: fffff542h, tq1ioc0: fffff612h, tq2ioc0: fffff622h 7 6 5 4 3 2 1 0 tqnioc0 tqnol3 tqnoe3 tqnol2 tqnoe2 tqnol1 tqnoe1 tqnol0 tqnoe0 (n = 0 to 2) tqnolm setting of toqnm output level (m = 0 to 3) 0 normal output 1 inverted output tqnoem setting of toqnm output (m = 0 to 3) 0 disable timer output (toqnm pin outputs low level when tqnolm = 0, and high level when tqnolm = 1). 1 enable timer output (toqnm pin outputs pulses). cautions 1. rewrite the tqnol1, tqnoe1, tqnol0, and tqnoe0 bits when tqnce = 0 (the same value can be wr itten when tqnce = 1). if these bits are rewritten by mistake, cl ear tqnce to 0 and then set them again. 2. to enable the timer output, be sure to set the corresponding alternate-function pins tqnis7 to tqnis0 of the tqnioc1 register to ?detect no edge? and invalidate the capture operation. then set the corresponding alternate-function port to output mode. 3. the output level of the toqnm pin changes into the state of tqnce=0 and tqnoem=0 if the tq nolm bit is operated when the pin is assumed to be a control output mode. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 393 (4) tmqn timer dedicated i/o control register 1 (tqnioc1) the tqnioc1 register is an 8-bit regist er that controls the valid edge of the external input signals (tiqn0 to tiqn3). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. (1/2) after reset: 00h r/w address: tq0ioc1: fffff543h, tq1ioc1: fffff613h, tq2ioc1: fffff623h 7 6 5 4 3 2 1 0 tqnioc1 tqnis7 tqnis6 tqnis5 tqnis4 tqnis3 tqnis2 tqnis1 tqnis0 (n = 0 to 2) tqnis7 tqnis6 setting of valid edge of capture input (tiqn3) 0 0 detect no edge (capture operation is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. tqnis5 tqnis4 setting of valid edge of capture input (tiqn2) 0 0 detect no edge (capture operation is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. tqnis3 tqnis2 setting of valid edge of capture input (tiqn1) 0 0 detect no edge (capture operation is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. tqnis1 tqnis0 setting of valid edge of capture input (tiqn0) 0 0 detect no edge (capture operation is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. remark: refer to the next page for the cautions . chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 394 (2/2) cautions 1. rewrite the tqnis7 to tqnis0 bits when tqnce0 = 0 (the same value can be written when tqnce = 1). if these bits are rewritten by mistake, clear tqnce to 0 and then set them again. 2. the tqnis7 to tqnis0 bits are va lid only in the free-running mode and pulse width measurement mode . a capture operation is not performed in any other mode. 3. to use the capture input, be sure to set the corresponding alternate-function pins tqnoe3 to tqnoe0 of the tqnioc register to "timer output prohibit" and be sure to set variable edge of capture input. then, set the corresponding alternate-function port to input mode. 4. to use the external event count mode (tqnctl1.tq0eee bit=1), be sure to set tiqn0 capture input to "no edge detection" (tqnis1, 0 bit=00b). chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 395 (5) tmqn timer dedicated i/o control register 2 (tqnioc2) the tqnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tiqn0) and external trigger input signal (tiqn0). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tq0ioc2: fffff544h, tq1ioc2: fffff614h, tq2ioc2: fffff624h 7 6 5 4 3 2 1 0 tqnioc2 0 0 0 0 tqnees1 tqnees0 tqnets1 tqnets0 (n = 0 to 2) tqnees1 tqnees0 setting of valid edge of external event count input (tiqn0) 0 0 detect no edge (external event count is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. tqnets1 tqnets0 setting of valid edge of external trigger input (tiqn0) 0 0 detect no edge (external trigger is invalid). 0 1 detect rising edge. 1 0 detect falling edge. 1 1 detect both the edges. cautions 1. rewrite the tqnees1, tqn ees0, tqnets1 and tqnets0 bits when tqnce = 0 (the same value can be wr itten when tqnce = 1). if these bits are rewritten by mistake, cl ear tqnce to 0 and then set them again. 2. the tqnees1 and tqnees0 bits are valid when tqneee = 1 or when the external event count m ode is set (tqnmd2 to tqnmd0 of tiqnctl1 register = 001). 3. when setting of the external trigger pulse output mode (tqnctl1.tqnmd2-0=010b) or the one-shot pulse output mode (tqnctl1.tqnmd2=011b) only, tqnets1, tqnets0 bits are variable. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 396 (6) tmqn timer option register 0 (tqnopt0) the tqnopt0 register is an 8-bit register that selects a capture or compare operation, and detects an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: tq0opt0: fffff545h, tq1opt0: fffff615h, tq2opt0: fffff625h 7 6 5 4 3 2 1 0 tqnopt0 tqnccs3 tqnccs2 tqnccs1 tqnccs0 0 0 tqncuf tqnovf (n = 0 to 2) tqnccsm selection of capture or compare operation of tqnccrm register (m = 0 to 3) 0 compare register 1 capture register the set value of the tqnccsm bit is valid only in the free-running mode. tqncuf timer q down count flag 0 tmqn counting up 1 tmqn counting down tqnucf bit is valid in the triangular wave pwm mode. this is read-only; a value wri tten to this flag is invalid. tqnovf detection of overflow of timer q set (1) overflow occurred reset (0) 0 written to tqnovf bit or tqnce = 0 ? the tqnovf bit is set when the 16-bit counter overflows from ffffh to 0000h in the free- running mode and pulse width measurement mode. ? as soon as the tqnovf bit has been set to 1, an interrupt request signal (inttqnov) is generated. the inttqnov signal is not generated in any mode other than the free-running mode and pulse width measurement mode. ? the tqnovf bit is not cleared even if the tqnovf bit and tqnopt0 register are read when tqnovf = 1. ? the tqnovf bit can be read and written, but 1 can not be written to the tqnovf bit. writing 1 to this bit does not affect the operation of timer q. cautions 1. rewrite the tqnccs1 and tqnccs0 bits when tqnce0 = 0 (the same value can be written when tqnce = 1). if these bits are rewritten by mistake, clear tqnce to 0 and then set them again. 2. be sure to clear bits 2 and 3 to 0. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 397 (7) tiqnm pin noise elimination control register n (qnmnfc) the qnmnfc register is an 8-bit regist er that sets the digital noise filter of the timer q input pin for noise elimination. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: q00nfc: fffffb50h (tiq00 pin) q01nfc: fffffb54h (tiq01 pin) q02nfc: fffffb58h (tiq02 pin) q03nfc: fffffb5ch (tiq03 pin) q10nfc: fffffb60h (tiq10 pin) q11nfc: fffffb64h (tiq11 pin) q12nfc: fffffb68h (tiq12 pin) q13nfc: fffffb6ch (tiq13 pin) q20nfc: fffffb70h (tiq20 pin) q21nfc: fffffb74h (tiq21 pin) q22nfc: fffffb78h (tiq22 pin) q23nfc: fffffb7ch (tiq23 pin) 7 6 5 4 3 2 1 0 qnmnfc 0 nfsts 0 0 0 nfc2 nfc1 nfc0 nfsts setting of number of times of sampling by digital noise filter 0 3 times 1 2 times nfc2 nfc1 nfc0 sampling clock 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /16 1 0 0 f xx /32 1 0 1 f xx /64 other than above setting prohibited cautions 1. be sure to clear bits 3 to 5 and 7 to 0. 2. a signal input to the timer input pin (tiqnm) before the qnmnfc register is set is output wi th digital noise eliminated. therefore, set the sampling clock (nfc2 to nfc0) and the number of times of sampling (nfsts) by using the qnmnfc register, wait for initialization time = (sampling clock) (number of times of sampling), and enable the timer operation. remarks 1. the width of the noise that can be accurately eliminated is (sampling clock) (number of times of sampling ? 1). even noise with a width narrower than this may cause a miscount if it is synchronized with the sampling clock. 2. n: number of timer channels (0 to 2) m: number of input pins (0 to 3) chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 398 8.5 operation timer q performs the following operations. operation tqnest (software trigger bit) tiqn0 (external trigger input) capture/compare selection compare write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid valid compare only anytime write external trigger pulse output mode note 2 valid valid compare only reload one-shot pulse output mode note 2 valid valid compare only anytime write pwm mode invalid invalid compare only reload free-running mode invalid invalid capture/compare selectable anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable triangular wave pwm mode invalid invalid compare only reload notes 1. to use the external event counter input function, specif y that the input edge of t he tiqn0 pin is not detected (by clearing the tqnis1 and tqnis0 bi ts of the tqnioc1 register to 00). 2. to use the external trigger pulse output mode, one- shot pulse mode, or pulse width measurement mode, select a count clock (by clearing the tqne ee bit of the tqnctl1 register to 0). 8.5.1 anytime write and reload timer q allows rewriting of the tqnccr0 to tqnccr3 regi sters while the timer is operating (tqnce = 1). these registers are written differently (anytime write or reload) depending on the mode. (1) anytime write when data is written to the tqnccr0 to tqnccr3 regist ers during timer operation, it is transferred at any time to the ccr0 to ccr3 buffer register and is compared with the val ue of the 16-bit counter. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 399 figure 8-2. flowchart of basic operation of anytime write start inttqncc occurs enable timer operation (tqnce = 1) transfer values of tqnccr0 to ccr0 buffer register rewrite tqnccr0 transfer to ccr0 buffer register rewrite tqnccr1 transfer to ccr1 buffer register rewrite tqnccr2 transfer to ccr2 buffer register rewrite tqnccr3 transfer to ccr3 buffer register initial setting ? ccr0 buffer register matches 16- bit counter. ? clear and start 16-bit counter. remarks 1. this is an example in the interval timer mode. 2. n = 0 to 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 400 figure 8-3. timing chart of anytime write tqnce = 1 16-bit counter tqnccr0 tqnccr1 tqnccr2 tqnccr3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 d 31 remarks 1. d 01 , d 02 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 : set value of tqnccr3 register (0000h to ffffh) 2. this is an example in the interval timer mode. 3. n = 0 to 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 401 (2) reload when data is written to the tqnccrm register during time r operation, it is compared with the value of the 16- bit counter via the ccrm buffer register. the value of the tqnccrm register c an be rewritten when tqnce = 1. so that the set values of the tq nccrm register is compared with the value of the 16-bit counter (the set values are reloaded to the ccrm buffer register), the value of the tqnccr0, tqnccr2 and tqnccr3 register must be rewritten and then a value must be wri tten to the tqnccr1 register before the value of the 16-bit counter matches the value of the ccr0 buffer register. when the value of the ccr0 buffer register matches t he value of the 16-bit counter, the value of the tqnccrm register is reloaded to the ccrm buffer register. whether the next reload timing is made valid or not is controlled by writing to the tqnccr1 register. therefore, when rewriting value of tqnccr0, tqnccr2 or tqnccr3 regi sters, be sure to write tqnccr1 register to same value (set same value of tqnccr1 register). figure 8-4. flowchart of basic operation of reload start reload is enabled enable timer operation (tqnce = 1) transfer value of tqnccr0 to ccr0 buffer register rewrite tqnccr0. rewrite tqnccr2. rewrite tqnccr3. rewrite tqnccr1. inttqncc0 occurs initial setting ? tqnccr0 matches 16-bit counter. ? clear and start 16-bit counter. ? value of tqnccrm is reloaded to ccrm buffer register. caution writing the tqnccr1 register includes an operation to enable reload. therefore, when rewriting one of tqnccr0, tqnccr2 or tqnccr3 registers, tqnccr1 register needs to write same value enable the next reload. then rewrite the tqnccr1 register after rewriting other tqnccr registers. remarks 1. this is an example in the pwm mode. 2. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 402 figure 8-5. timing chart of reload tqnce = 1 16-bit counter tqnccr0 tqnccr1 tqnccr2 tqnccr3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 03 0000h d 11 0000h d 21 d 12 d 21 d 12 0000h d 31 d 32 d 33 d 31 d 32 d 33 d 01 d 02 d 03 d 11 d 12 d 12 d 21 d 31 d 11 d 01 d 21 d 21 d 12 d 12 d 12 d 12 d 32 d 32 d 32 d 02 d 02 d 03 d 21 d 21 note note note same value write note the value is not reloaded because the tqnccr1 register is not written. remarks 1. d 01 , d 02 , d 03 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 , d 32 , d 33 : set value of tqnccr3 register (0000h to ffffh) 2. this is an example in the pwm mode. 3. n = 0 to 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 403 8.5.2 interval timer mode (tqnmd2 to tqnmd0 = 000) in the interval timer mode, an interrupt request signal (inttqncc0) is generated when the set value of the tqnccr0 register matches the value of the 16-bit counter, and the 16-bit counter is cleared. rewriting the tqnccrm register is enabled when tqnce = 1. when a value is set to the tqnccrm register, it is transferred to the ccrm buffer register by means of anytime write, and is compared with the value of the 16-bit counter. the 16-bit counter is not cleared by using the tqnccrk register. however, the set value of the tqnccrk register is trans ferred to the ccrk buffer register and compared with the value of the 16-bit counter. as a result, an interrupt request (inttqncck) is generated. the value can also be output from the toqn m pin by setting the tqnoem bit to 1. when the tqnccrk register is not used, it is re commended to set the tqn ccrk register to ffffh. remarks 1. for the rewriting tqnccr0 to tqnccr3 duri ng timer operation (tqnce=1), refer to 8. 5. 1 anytime write . 2. n = 0 to 2, m = 0 to 3, k = to 3 figure 8-6. flowchart of basic op eration in interval timer mode start inttqncc0 occurs enable timer operation (tqnce = 1) transfer value of tqnccrm to ccrm buffer register 16-bit counter and ccr0 buffer register match. clear and start 16-bit counter. 16-bit counter matches ccrk buffer register note . inttqncck occurs initial setting ? select clock (tqnctl0: tqncks2 to tqncks0). ? set interval timer mode (tqnctl0: tqnmd2 to tqnmd0 = 000). ? set compare register (tqnccrm). note the 16-bit counter is not cleared when its value matches the value of tqnccrk. remark n = 0 to 2, m = 0 to 3, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 404 figure 8-7. timing of basic operat ion in interval timer mode (1/2) (a) when only tqnccr0 register value is rewritten and toqnm is not output (tqnoem = 0, tqnolm = 0) tqnce = 1 16-bit counter tqnccr0 ffffh tqnccr1 tqnccr2 tqnccr3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 0000h d 11 0000h d 21 0000h d 31 d 11 d 21 d 31 d 02 d 01 d 31 d 31 d 31 d 11 d 11 d 21 d 11 d 01 d 01 d 02 d 02 remarks 1. d 01 , d 02 : set value of tqnccr0 register (0000h to ffffh) d 11 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 : set value of tqnccr3 register (0000h to ffffh) 2. interval time = (d0n + 1) (count clock cycle) 3. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 405 figure 8-7. timing of basic operat ion in interval timer mode (2/2) (b) when d 01 = d 31 , only tqnccr1 register value is rewritten, and toqnm is output (tqnoem = 1, tqnolm = 0) tqnce = 1 16-bit counter tqnccr0 ffffh tqnccr1 tqnccr2 tqnccr3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 toqn1 toqn0 toqn2 toqn3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 01 d 31 0000h d 11 d 12 d 11 d 12 0000h d 21 d 21 d 21 d 21 d 11 d 11 d 12 d 01 = d 31 d 01 = d 31 d 31 d 21 0000h remarks 1. d 01 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 : set value of tqnccr3 register (0000h to ffffh) 2. interval time = (d0n + 1) (count clock cycle) 3. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 406 8.5.3 external event count mode (tqnmd2 to tqnmd0 = 001) in the external event count mode, the external event c ount input (tiqn0 pin input) is used as a count-up signal. regardless of the setting of the tqneee bit of the tqnctl0 register, 16-bit timer/event counter q counts up the external event count input (tiqn0 pin input) when it is set in the external event count mode. in the external event count mode, an interrupt req uest (inttqncc0) is generated when the set value of the tqnccr0 register matches the value of the 16-bit co unter, and the value of the 16-bit counter is cleared. when a value is set to the tqnccrm register, it is transfe rred to the ccrm buffer register by means of anytime write, and is compared with the value of the 16-bit counter. the 16-bit counter cannot be cleared by using the tqnccrk register. however, the set value of the tqnccrk register is transferred to the ccrk buffer register and is compared with the value of the 16-bit counter. as a result, an interrupt request (inttqncck) is generated. by setting the tqnoek bit to 1, a si gnal can be output from the toqnk pin. toqn pin can not to use. when the tqnccrk register is not used, it is recommended to set tqnccrk to ffffh. remarks 1. for the rewriting tqnccr0 to tqnccr3 du ring timer operation (tqnce=1), refer to 8. 5. 1 anytime write . 2. n = 0 to 2, m = 0 to 3, k = to 3 caution 1. toqn0 pin output in an external event count mode cannot be u sed. set to tqneee = 1by interval timer mode (tqnmd2 to 0 = 000b) wh en toqn0 pin output in an external event count mode is used. 2. in external event count mode, when tqnccrm register value is set to 0000h the interrupt occurs after the overflow of the timer (ffffh to 0000h) chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 407 figure 8-8. flowchart of basic operation in external event count mode start inttqncc0 occurs enable timer operation (tqnce = 1) transfer value of tqnccrm to ccrm buffer register 16-bit counter matches ccr0 buffer register. clear and start 16-bit counter. 16-bit counter matches ccrk buffer register note 2 . inttqncck occurs initial setting ? set external event count mode (tqnctl0: tqnmd2 to tqnmd0 = 001) note 1 ? set valid edge (tqnioc2: tqnees1, tqnees0). ? set compare register (tqnccrm). notes 1. selecting the tqneee bit has no effect. 2. the 16-bit counter is not cleared when it matches the ccrk buffer register. remark n = 0 to 2, m = 0 to 3, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 408 figure 8-9. timing of basic operation in external event count mode (1/2) (a) when only tqnccr0 register value is rewritten and toqnm is not output (tqnoem = 0, tqnolm = 0) tqnce = 1 16-bit counter tqnccr0 ffffh tqnccr1 tqnccr2 tqnccr3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 0000h d 11 0000h d 21 0000h d 31 d 11 d 21 d 31 d 02 d 01 d 31 d 31 d 31 d 11 d 11 d 21 d 11 d 01 d 01 d 02 d 02 remarks 1. d 01 , d 02 : set value of tqnccr0 register (0000h to ffffh) d 11 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 : set value of tqnccr3 register (0000h to ffffh) 2. a compare match interrupt is generated each time (the value set to tqnccrm register +1) is detected. 3. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 409 figure 8-9. timing of basic operation in external event count mode (2/2) (b) when d 01 = d 31 , only tqnccr1 register is re written, and toqnm is output (tqnoe0 = 0, tqnoek = 1, tqnol0 = 0, tqnolk = 0) tqnce = 1 16-bit counter tqnccr0 ffffh tqnccr1 tqnccr2 tqnccr3 inttqncc0 inttqncc1 inttqncc2 inttqncc3 toqn1 toqn2 toqn3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 01 d 31 0000h d 11 d 12 d 11 d 12 0000h d 21 d 21 d 21 d 21 d 11 d 11 d 12 d 01 = d 31 d 01 = d 31 d 31 d 21 0000h remarks 1. d 01 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 : set value of tqnccr3 register (0000h to ffffh) 2. a compare match interrupt is generated each time (the value set to tqnccrm register +1) is detected. 3. n = 0 to 2, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 410 8.5.4 external trigger pulse output mode (tqnmd2 to tqnmd0 = 010) when tqnce = 1 in the external trig ger pulse output mode, the 16-bit counter stops at ffffh and waits for input of an external trigger (tiqn0 pin input). when the counter detects t he edge of the external trigger (tiqn0 pin input), it starts counting up. the duty factor of the signal output from the toqnk pin is set by a rel oad register (tqnccrk) and the period is set by a compare register (tqnccr0). rewriting the tqnccrm register is enabled when tqnce = 1. to stop timer q, clear tqnce to 0. if the edge of the exte rnal trigger (tiqn0 pin input) is detected more than once in the external trigger pulse output mode, the 16-bit count er is cleared at the point of edge detection, and resumes counting up. at the same time, toqn0 pin is initialized. to realize the same function as the external trigger pulse output mode by using a software trigger instead of the exter nal trigger input (tiqn0 pin input) (software trigger pulse output mode), a software trigger is generated by setting the tq nest bit of the tqnctl1 regi ster to 1. the waveform of the external trigger pulse is output from toqnk. in the external trigger pulse output mode, the capture function of the tq nccrm register cannot be used because this register can be used only as a compare register. caution in the external trigger pul se output mode, select th e internal clock (tqneee of tqnctl1 register = 0) as the count clock. remarks 1. for the rewriting tqnccr0 to tqnccr3 during timer operation (tqnce=1), refer to 8.5.1 (2) reload. 2. n = 0 to 2, m = 0 to 3, k = to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 411 figure 8-10. flowchart of basic operation in external trigger pulse output mode start inttqncc0 occurs enable timer operation (tqnce = 1) transfer value of tqnccrm to ccrm buffer register 16-bit counter matches tqnccr0. clear and start 16-bit counter. 16-bit counter matches tqnccrk note 2 . external trigger (tiqn0 pin) input or tqnest = 1 note 1 16-bit counter starts counting inttqncck occurs initial setting external trigger (tiqn0 pin) input clear and start 16-bit counter. ? select clock. (tqnctl1: tqneee = 0) (tqnctl0: tqncks2 to tqncks0) ? set external trigger pulse output mode. (tqnctl1: tqnmd2 to tqnmd0 = 010) ? set compare register. (tqnccrm) notes 1. only tqnest bit of tqnct register can be rewritten during timer operation (tqnce = 1). 2. the 16-bit counter is not cleared when it matches the ccrk buffer register. remark n = 0 to 2, m = 0 to 3, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 412 figure 8-11. timing of basic operation in external trigger pulse output mode (tqnoe0 = 0, tqnoek = 1, tqnol0 = 0, tqnolk = 0) tqnce = 1 16-bit counter tqnccr0 ffffh tqnccr1 tqnccr2 tqnccr3 toqn1 toqn2 toqn3 ccr0 buffer register external trigger (toqn0 pin) ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 01 d 02 0000h d 11 d 12 d 11 d 12 d 31 d 32 d 31 d 32 0000h d 21 d 21 d 31 d 31 d 11 d 21 d 21 d 01 d 12 d 02 d 12 d 32 0000h remarks 1. d 01 , d 02 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 , d 32 : set value of tqnccr3 register (0000h to ffffh) 2. duty of toqnk output = (set value of tqnccr k register) / (set value of tqnccr0 register) cycle of toqnk output = (set value of tqnccr0 register +1) (count clock cycle) 3. n = 0 to 2, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 413 8.5.5 one-shot pulse mode (tqnmd2 to tqnmd0 = 011) when tqnce is set to 1 in the one-shot pulse mode, the 16 -bit counter waits for the setting of the tqnest bit (to 1) or a trigger that is input when t he edge of the tiqn0 pin is detected, while holding ffffh. when the trigger is inputted, the 16-bit counter starts c ounting up. when the value of the 16-bit counter matches the value of the ccrk buffer register that has been transferr ed from the tqnccr0 register, toqnk goes high. when the value of the 16-bit counter matches the value of the ccr0 bu ffer register that has been transferred from the tqnccr0 register, toqnk goes low, and the 16-bit counter is cleared to 0000h and stops . input of a second or subsequent trigger is ignored while the 16-bit counter is operating. be sure to input a second trigger while the 16-bit counter is stopped at 0000h. in the one-shot pulse mode, rewriting t he tqnccrm register is enabled when tqnc e = 1. if the value is set to the tqnccrm register, it is transferred to the ccrm buffer register by anytime write and it becomes an object of comparison value with 16 bit counter value. the waveform of the one-shot pulse is output from the toqnk pin. the toqnm pin produces an active level until counting by timer counter. active level is set by tqnol0 bit. cautions 1. select the internal cl ock (tqneee of the tqnctl1 register = 0) as the count clock in the one- shot pulse mode. 2. in the one-shot pulse mode, the tqnccrm regist er is used only as a compare register. it cannot be used as a capture register. 3. when the set value of tqnccrk is larger th an the set value of tqn ccr0 in the one-shot pulse mode, in the one-shot pulse is not output. remarks 1. for the rewriting tqnccr0 to tqnccr3 during timer operation (tqnce=1), refer to 8. 5. 1 anytime write. 2. n = 0 to 2, m = 0 to 3, k = 1 to 3. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 414 figure 8-12. flowchart of basic op eration in one-shot pulse mode start 16-bit counter matches ccr0 buffer register. clear 16-bit counter. input external trigger (tiqn0 pin) or tqnest = 1 note 1 16-bit counter starts counting inttqncc0 occurs enable timer operation (tqnce = 1) transfer values of tqnccr0 to ccr0 buffer register 16-bit counter matches ccrk buffer register note 2 . wait for trigger. 16-bit counter stands by at ffffh. wait for trigger. 16-bit counter stands by at 0000h. inttqncck occurs initial setting ? select clock. (tqnctl1: tqneee = 0) (tqnctl0: tqncks2 to tqncks0) ? set one-shot pulse mode. (tqnctl1: tqnmd2 to tqnmd0 = 011) ? set compare register. (tqnccrm) notes 1. only tqnest bit of tqnct register can be rewritten during timer operation (tqnce = 1). 2. the 16-bit counter is not cleared when it matches the ccrk buffer register. caution the 16-bit counter is not cleared even if the trigger is input while the counter is counting up, and the trigger input is ignored. remar k n= 0 to 2, m = 0 to 3, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 415 figure 8-13. timing of basic oper ation in one-shot pulse mode (tqnoe0 = 0, tqnoek = 1, tqnol0 = 0, tqnolk = 0) d 01 d 31 d 31 d 32 d 11 d 11 d 11 d 21 d 21 d 21 d 01 d 01 d 01 d 01 0000h d 11 d 11 0000h d 21 d 21 0000h d 31 d 32 d 31 d 32 0000h note tqnce = 1 tqnest = 1 ffffh 16-bit counter external trigger (toqn0 pin) tqnccr0 inttqncc0 tqnccr1 tqnccr2 inttqncc1 inttqncc2 inttqncc3 toqn1 toqn2 toqn3 ccr0 buffer register ccr1 buffer register ccr2 buffer register tqnccr3 ccr3 buffer register note the 16-bit counter starts counting up either when tq nest = 1 or when an external trigger (toqn0 pin) is input. remarks 1. d 01 : set value of tqnccr0 register (0000h to ffffh) d 11 : set value of tqnccr1 register (0000h to ffffh) d 21 : set value of tqnccr2 register (0000h to ffffh) d 31 , d 32 : set value of tqnccr3 register (0000h to ffffh) 2. n = 0 to 2, k = 1 to 3 3. output delay time = (set value of tq nccrk register) (count clock cycle) active level width = (set value of tqnccr0 regist er - set value of tqnccrk register +1) (count clock cycle) chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 416 8.5.6 pwm mode (tqnmd2 to tqnmd0 = 100) in the pwm mode, tmqn capture/compare register k (tqnccrk) is used to set the duty factor and tmqn capture/compare register 0 (tqn ccr0) is used to set the cycle. by using these two registers and operati ng the timer, variable-duty pwm is output. rewriting the tqnccrm register is enabled when tqnce = 1. to stop timer q, clear tqnce to 0. the waveform of pwm is output from the toqnk pin. the toqn0 pin produces a half pulse output of pwm cycle when the 16 -bit counter matches the tqnccr0 register. remarks 1. for the rewriting tqnccr0 to tqnccr3 during timer operation (tqnce = 1), refer to 8.5.1 (2) reload . 2. n = 0 to 2, m = 0 to 3, k = 1 to 3 caution: in the pwm mode, the tqnccrm register is u sed only as a compare regist er. it cannot be used as a capture register. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 417 (1) operation flow of pwm mode figure 8-14. flowchart of basic operation in pwm mode (1/2) (a) when values of tqnccrm register is not rewritten during timer operation start inttqncc0 occurs enable timer operation (tqnce = 1) transfer value of tqnccrm register to ccrm buffer register 16-bit counter matches ccrk buffer register. toqnk outputs low level. 16-bit counter matches ccr0 buffer register. clear and start 16-bit counter. toqnk outputs high level. toqn0 reverses inttqncck occurs initial setting ? select clock. (tqnctl0: tqncks2 to tqncks0) ? set pwm mode. (tqnctl1: tqnmd2 to tqnmd0 = 100) ? set compare register. (tqnccrm) remark n = 0 to 2, m = 0 to 3, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 418 figure 8-14. flowchart of basic operation in pwm mode (2/2) (b) when value of tqnccrm register is rewritten dur ing timer operation start inttqncc0 occurs 16-bit counter matches ccrk buffer register. toqnk outputs low level. enable timer operation (tqnce = 1) transfer value of tqnccrm register to ccrn buffer register 16-bit counter matches tqnccrk. toqnk outputs low level. rewrite other than tqnccr1 (tqnccr0, tqnccr2, tqnccr3). rewrite tqnccr1. 16-bit counter matches tqnccr0. clear and start 16-bit counter. toqnk outputs high level. toqn0 reverses inttqncck occurs reload is enabled note <1> <2> <3> inttqncc0 occurs inttqncck occurs initial setting ? select clock. (tqnctl0: tqncks2 to tqncks0) ? set pwm mode. (tqnctl1: tqnmd2 to tqnmd0 = 100) ? set compare register. (tqnccrm) ? ccr0 buffer register matches 16-bit counter. ? clear and start 16-bit counter. ? value of tqnccrm is reloaded to ccrm buffer register. ? toqnk outputs high level. ? toqn0 reverses note the timing of <2> may differ depending on the rewrit e timing of <1> and <3> and the value of tqnccrk, but make sure that <3> comes after <1>. remark n = 0 to 2, m = 0 to 3, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 419 (2) pwm output mode operation timing (a) change of pulse width during operation when change of pwm waveform during operation, please write to tq0ccr1 register at last. after write to tq0ccr1 register, when write to tpnccr0 register ag ain, please rewrite after detection of inttq0cc1 signal. figure 8-15. timing of basic operation in pwm mode (1/2) (a) when rewriting values of tqnccr1 to tqnccr3 registers (tqnoe0 = 1, tqnoek = 1, tqnol0 = 0, tqnolk = 0) tqnce = 1 ffffh 16-bit counter tqnccr0 tqnccr1 tqnccr2 tqnccr3 toqn1 toqn2 toqn3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register d 11 d 31 d 32 d 32 d 21 d 21 d 01 d 01 d 01 d 12 d 22 d 12 same value write toqn0 0000h d 01 d 01 0000h d 11 d 12 d 12 d 31 d 32 d 33 0000h d 21 d 22 d 13 0000h d 31 d 32 d 33 d 11 d 12 d 12 d 21 d 22 d 13 remarks 1 . d 01 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 , d 13 : set value of tqnccr1 register (0000h to ffffh) d 21 , d 22 : set value of tqnccr2 register (0000h to ffffh) d 31 , d 32 , d 33 : set value of tqnccr3 register (0000h to ffffh) 2. duty of toqnk output = (set value of tqnccrk r egister) / (set value of tqnccr0 register + 1) cycle of toqnk output = (set value of tqnccr0 register) (count clock cycle) toggle width of toqn0 output = (set value of tqnccr0 register + 1) (count clock cycle) 3. n = 0 to 2, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 420 figure 8-15. timing of basic operation in pwm mode (2/2) (b) when rewriting values of tqnccr0 to tqnccr3 registers (tqnoe0 = 1, tqnoek = 1, tqnol0 = 0, tqnolk = 0) tqnce = 1 ffffh 16-bit counter tqnccr0 tqnccr1 tqnccr2 tqnccr3 toqn1 toqn2 toqn3 ccr0 buffer register ccr1 buffer register cc2 buffer register ccr3 buffer register d 11 d 11 d 31 d 32 d 33 d 21 d 21 d 01 d 01 d 02 d 31 d 12 d 22 d 22 same value write toqn0 0000h d 01 d 02 d 01 d 02 0000h d 11 d 12 d 31 d 32 d 33 0000h d 21 d 22 d 12 0000h d 31 d 32 d 33 d 11 d 12 d 21 d 22 d 12 note note no value is reloaded because the tq nccr1 register is not rewritten. remarks 1. d 01 , d 02 : set value of tqnccr0 register (0000h to ffffh) d 11 , d 12 : set value of tqnccr1 register (0000h to ffffh) d 21 , d 22 : set value of tqnccr2 register (0000h to ffffh) d 31 , d 32 , d 33 : set value of tqnccr3 register (0000h to ffffh) 2. duty of toqnk output = (set value of tqnccrk r egister) / (set value of tqnccr0 register + 1) cycle of toqnk output = (set value of tqnccr0 register) (count clock cycle) toggle width of toqn0 output = (set value of tqnccr0 register + 1) (count clock cycle) 3. n = 0 to 2, k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 421 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrk register to 0000h. if the set value of the tq0ccr0 register is ffffh, the inttq0cck signal is generated periodically. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3 to output a 100% waveform, set a value of (set value of tq0ccr0 register + 1) to the tq0ccrk register. if the set value of the tq0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 422 8.5.7 free-running mode (tqnmd2 to tqnmd0 = 101) in the free-running mode, the 16-bit counter free-runs, and the bit that selects the c apture or compare register function can be by the setting of the tq nccs3 to tqnccs0 bits, so that an interval function and a capture function can be realized. setting of the tqnccs3 to tqnccs0 bi ts of the tqnopt0 register is va lid only in the free-running mode. caution: in the free-running mode, counter clear can be operated by matc hed compare register. tqnccsm operation 0 tqnccrm register is used as compare register. 1 tqnccrm register is used as capture register. ? when tqnccrm register is used as compare register when the value of the 16-bit counter ma tches the value of the ccrm buffer register in the free-running mode, an interrupt is generated. tqnccrm register is enabled for write operation when tpnce=1. any data is set to tpnccr1 register by anytime write, data is translated to ccrm buffer regi ster, and data become comparison value with value of the 16 bit counter. caution: external event count input as count cloc k (tqnctl.tqneee=1) , tqnccr0 register can not to use as capture register. if timer output (toqnm) is enabled, toqnm produces a toggle output when the valu e of the 16-bit counter matches the value of the ccrm buffer register. ? when tqnccrm register is used as capture register the value of the 16-bit counter is st ored in the tqnccrm register when the edge of the tiqnm pin is detected. remarks 1. for the rewritten tqnccr0 to tqnccr3 during timer operation, refer to 8.5.1 (1) anytime write . 2. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 423 figure 8-16. flowchart of basic operation in free-running mode start set tqnccsm. initial setting enable timer operation (tqnce = 1) transfer value of tqnccrm to ccrm buffer register ccrm buffer register matches 16-bit counter. 16-bit counter overflows. edge of tiqnm is detected. value of 16-bit counter is captured to tqnccrm. 16-bit counter overflows. enable timer operation (tqnce = 1) set detection of edge of tiqnm (tqnioc1 register note ). tqnccsm = 0 (compare) tqnccsm = 1 (capture) ? select clock. (tqnctl0: tqncks2 to tqncks0) ? set free-running mode. (tqnctl1: tqnmd2 to tqnmd0 = 101) note tqnccr0 edge detection: tqnis1, tqnis0 bits tqnccr1 edge detection: tqnis3, tqnis2 bits tqnccr2 edge detection: tqnis5, tqnis4 bits tqnccr3 edge detection: tqnis7, tqnis6 bits remark n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 424 (1) when tqnccsm = 0 (compare function) when tqnce is set to 1, the 16-bit counter counts from 0000h to ffffh, and contin ues counting up in the free-running mode until tqnce is cleared to 0. if a value is written to the tqnccrm register in this mode, it is transferred to the ccrm buffer registers (anytime write). even if a one-shot pulse trigger is input in this mode, a one-shot pulse is not generated. if tqnoem is set to 1, toqnm produces a toggle output when the value of the 16-bit counter matches the value of the ccrm buffer register. (2) when tqnccsm = 1 (capture function) when tqnce is set to 1, the 16-bit counter counts from 0000h to ffffh, and contin ues counting up in the free-running mode until tqnce is cleared to 0. the va lue captured by a capture trigger is written to the tqnccrm registers. capturing before and after overflow (ffffh) is judged using the overflow flag (tqnovf). however, if the interval of the capture trigger is such t hat the overflow occurs two times (two periods of more of free-running), the tqnovf flag cannot be used for judgment. remark n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 425 figure 8-17. timing of basic oper ation in free-running mode (1/4) (a) tqnccs3 = 0, tqnccs2 = 0, tqnccs1 = 0, tqnccs0 = 0 (tqnoem = 1, tqnolm = 0) tqnce = 1 ffffh 0000h d 00 d 00 d 00 d 00 d 20 d 20 d 20 d 30 d 30 d 10 d 11 d 11 d 31 d 01 d 01 d 01 0000h d 30 d 30 d 31 d 31 0000h d 20 d 20 0000h d 10 d 10 d 11 d 11 16-bit counter tqnccr0 inttqncc0 match interrupt inttqncc1 match interrupt toqn0 toqn1 toqn2 toqn3 inttqncc2 match interrupt inttqncc3 match interrupt tqnccr1 tqnccr2 tqnccr3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register remarks 1. d 00 , d 01 : set value of tqnccr0 register (0000h to ffffh) d 10 , d 11 : set value of tqnccr1 register (0000h to ffffh) d 20 : set value of tqnccr2 register (0000h to ffffh) d 30 , d 31 : set value of tqnccr3 register (0000h to ffffh) 2. toqnm output goes high when counting is started. 3. n = 0 to 2,m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 426 figure 8-17. timing of basic oper ation in free-running mode (2/4) (b) tqnccs3 = 1, tqnccs2 = 1, tqnccs1 = 1, tqnccs0 = 1 (tqnoem = 0, tqnolm = 0) 0000h d 20 d 21 d 22 0000h d 30 d 31 d 32 0000h d 10 d 11 d 12 d 20 d 30 d 00 d 10 d 01 d 21 d 31 d 22 d 11 d 02 d 12 d 32 tqnce = 1 ffffh 16-bit counter tiqn0 inttqncc0 capture interrupt inttqncc1 capture interrupt inttqncc2 capture interrupt inttqncc3 capture interrupt tiqn1 tiqn2 tiqn3 tqnccr0 tqnccr1 tqnccr2 tqnccr3 0000h d 01 d 00 d 02 remarks 1. d 00 , d 01 , d 02 : value captured to tqnccr 0 register (0000h to ffffh) d 10 , d 11 , d 12 : value captured to tqnccr 1 register (0000h to ffffh) d 20 , d 21 , d 22 : value captured to tqnccr 2 register (0000h to ffffh) d 30 , d 31 , d 32 : value captured to tqnccr 3 register (0000h to ffffh) 2. tiqn0: detection of rising ed ge (tqnis1, tqnis0 = 01) is set. tiqn1: detection of falling ed ge (tqnis3, tqnis2 = 10) is set. tiqn2: detection of falling ed ge (tqnis5, tqnis4 = 10) is set. tiqn3: detection of both rising and fa lling edges (tqnis7, tqnis6 = 11) is set. 3. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 427 figure 8-17. timing of basic oper ation in free-running mode (3/4) (c) tqnccs3 = 0, tqnccs2 = 0, tqnccs1 = 1, tqnccs0 = 1 (tqnoem = 0, tqnolm = 0) 0000h d 20 d 21 d 20 d 21 0000h d 30 d 30 0000h d 10 d 11 d 12 d 13 d 30 d 30 d 30 d 00 d 01 d 21 d 11 d 20 d 20 d 02 d 03 d 13 d 10 tqnce = 1 ffffh 16-bit counter tiqn0 inttqncc0 capture interrupt inttqncc1 capture interrupt inttqncc2 match interrupt inttqncc3 match interrupt tiqn1 tqnccr2 tqnccr3 inttqncc0 tqnccr1 0000h d 00 d 01 d 02 d 03 d 12 ccr2 buffer register ccr3 buffer register remarks 1. d 00 , d 01 , d 02 , d 03 : value captured to tqnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : value captured to tqnccr1 register (0000h to ffffh) d 20 , d 21 : value captured to tqnccr2 register (0000h to ffffh) d 30 : value captured to tqnccr3 register (0000h to ffffh) 2. tiqn0: detection of rising ed ge (tqnis1, tqnis0 = 01) is set. tiqn1: detection of falling ed ge (tqnis3, tqnis2 = 10) is set. 3. n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 428 figure 8-17. timing of basic oper ation in free-running mode (4/4) (d) tqnccs3 = 0, tqnccs2 = 1, tqnccs1 = 0, tqnccs0 = 1 (tqnoem = 0, tqnolm = 0) 0000h d 20 d 21 0000h 0000h d 30 d 31 d 30 d 31 d 10 d 11 d 12 d 11 d 10 d 12 d 30 d 20 d 10 d 11 d 01 d 11 d 12 d 03 d 31 d 21 d 31 d 00 tqnce = 1 ffffh 16-bit counter tiqn0 inttqncc0 capture interrupt inttqncc1 match interrupt inttqncc2 capture interrupt inttqncc3 match interrupt tqnccr1 tqnccr2 tiqn2 tqnccr3 tqnccr0 0000h d 00 d 01 d 02 d 03 ccr1 buffer register ccr3 buffer register d 02 remarks 1. d 00 , d 01 , d 02 , d 03 : value captured to tqnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : value captured to tqnccr1 register (0000h to ffffh) d 20 , d 21 : value captured to tqnccr2 register (0000h to ffffh) d 30 , d 31 : value captured to tqnccr3 register (0000h to ffffh) 2. tiqn0: detection of rising ed ge (tqnis1, tqnis0 = 10) is set. tiqn2: detection of falling ed ge (tqnis5, tqnis4 = 10) is set. 3. n = 0 to 2, m = 0 to 3 (3) overflow flag when the counter overflows from ffffh to 0000h in the fr ee-running mode, the overflow flag (tqnovf) is set to 1, and an overflow interrupt (inttqnov) is generated. the overflow flag is cleared by the cpu by writing 0 to it. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 429 8.5.8 pulse width measurement m ode (tqnmd2 to tqnmd0 = 110) in the pulse width measurement mode, free-running counting is performed. the value of the 16-bit counter is captured to capture register m (tqnccrm) when both the rising and fal ling edges of the tiqnm pin are detected, and the 16-bit counter is cleared to 0000h. in this way, the external input pulse width can be measured. to measure a long pulse width that exceeds the overflow of the 16-bit counter, use the overflow flag for detection. for measurement a pulse width that causes overflow to occur twice or more, please count the overflow number with the overflow interrupt. caution in the pulse width measurement mode, select the internal cl ock (tqneee of the tqnctl1 register = 0) as the count clock. figure 8-18 flowchart of basic operati on in pulse width measurement mode start set edge detection of tiqnm note . (tqnis3 to tqnis0) input rising edge of pulse to tiqnm. capture value to tqnccrm. clear and start 16-bit counter. input falling edge of pulse to tiqnm. capture value to tqnccrm. clear and start 16-bit counter. enable timer operation (tqnce = 1). initial setting ? select clock. (tqnctl0: tqncks2 to tqncks0) ? set pulse width measurement mode. (tqnctl1: tqnmd2 to tqnmd0 = 110) ? set compare register. (tqnopt0: tqnccs3 to tqnccs0) note an external pulse can be input from any of tiqn0 to t iqn3. only one of them can be used. specify that both the rising and falling edges are detect ed. specify that the input edge of an external pulse input that is not used is not detected. remark n = 0 to 2, m = 0 to 3 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 430 figure 8-19. timing of basic operati on in pulse width measurement mode tqnce = 1 0000h d 01 d 00 d 00 d 01 d 02 d 03 d 02 d 03 ffffh 16-bit counter tiqn0 inttqncc0 tqnovf inttqnov tqnccr0 ffffh cleared by writing 0 from cpu remarks 1. d 00 , d 01 , d 02 , d 03 : value captured to tqnccr0 register (0000h to ffffh) 2. tiqn0: both the rising an d falling edges are detected. 3. n = 0 to 2 4. pulse width = captured value count clock cycle if the valid edge is not input even when the 16-b it counter counted up to ffffh, an overflow interrupt request signal (inttqnov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow fl ag (tqnopt0.tqnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pulse width can be calculated as follows. pulse width = (10000h tqnovf bit set (1) count + captured value) count clock cycle chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 431 8.5.9 triangular wave pwm mode (tqnmd2 to tqnmd0 = 111) in the triangular wave pwm mode, tmqn capture/compar e register k (tqnccrk) is used to set the duty factor, and tmqn capture/compare register 0 (tqnccr0) is used to set the cycle. by using these four registers and operating the timer, triangular wave pwm with a variable cycle is output. the value of the tqnccrm register can be rewritten when tqnce = 1. whether the next reload timing is made valid or not is cont rolled by writing to the tqnccr1 register. therefore, write the same value to the tqnccr1 register when it is nec essary to rewrite the value of only the tqnccr0 register. reload is invalid when only the tqnccr0 register is rewritten. to stop timer q, clear tqnce to 0. the waveform of pwm is output from the toqnk pin. the toqn0 pin produces a toggle output when the value of the 16-bit counter matches the value of the tqnccr0 register and when the counter underflows. remarks: 1. for the rewriting tqnccr0 to tqnccr3 during timer operation (tqnce=1), refer to 8. 5. 1 (2) reload . 2. n = 0 to 2, m = 0 to 3, k = 1 to 3 caution: in the pwm mode, the tqnccrm register is u sed only as a compare regist er. it cannot be used as a capture register. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 432 figure 8-20. timing of basic operation in triangular wave pwm mode (tqnoe0 = 1, tqnoe1 = 1, tqnoe2 = 1, tqnoe3 = 1, tqnol0 = 0, tqnol1 = 0, tqnol2 = 0, tqnol3 = 0) tqnce = 1 ffffh 16-bit counter toqn0 toqn1 inttqnov inttqncc0 match interrupt inttqncc1 match interrupt tqnccr0 toqn2 toqn3 inttqncc2 match interrupt inttqncc3 match interrupt 0000h d 00 d 00 d 30 d 30 d 20 d 20 d 10 d 10 tqnccr1 0000h d 10 tqnccr2 0000h d 20 tqnccr3 0000h d 30 d 00 d 30 d 30 d 20 d 20 d 10 d 00 d 30 d 30 d 20 d 20 remark n = 0 to 2 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 433 8.6 timer synchronized operation function timer p and timer q have a timer synchroniz ed operation function (tuned operation mode). the timers that can be synchronized are listed in table 8-4. table 8-4. tuned operation mode of timers master timer slave timer tmp0 tmp1 ? tmp2 tmp3 tmq0 tmq1 tmq2 ? cautions 1. the tuned oper ation mode is enabled or disabled by the tpmsye bit of the tpmctl1 register and tqnsye bit of the tqnctl1 re gister. for tmq2, either or both tmq3 and tmq0 can be specified as slaves. 2. set the tuned operation mode usin g the following procedure. <1> set the tpmsye bit of the tpmctl1 regi ster and the tqnsye bit of the tqnctl1 register of the slave timer to enable the tuned operation. set the tpmmd2 to tpmmd0 bits of the tp mctl1 register and tqnm d2 to tqnmd0 bits of the tqnctl1 register of the slave timer to the free-running mode <2> set the timer mode by using the tpnmd2 to tpnmd0 bits of the tpnctl1 register and the tpnmd2 to tpnmd0 bits of the tqnctl1 register. at this time, do not set the tpnsye bit of the tpnctl1 register and the tqnsye bit of the tqnctl1 register of the master timer. <3> set the compare register value of the master and slave timers. <4> set the tpmce bit of the tpmctl0 register and the tqnce bit of the tqnctl0 register of the slave timer to enable operati on on the internal operating clock. <5> set the tpnce bit of the tpnctl0 register and the tqnce bit of the tqnctl0 register of the master timer to enable operati on on the internal operating clock. remark n = 0, 2, m = 1, 3 tables 8-5 and 8-6 show the timer modes that can be used in the tuned operation mode ( : settable, : not settable). table 8-5. timer modes usable in tuned operation mode master timer free-running mode pwm mode triangular wave pwm mode tmp0 tmp2 tmq1 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 434 table 8-6. timer output functions (1/2) free-running mode pwm mode triangular wave pwm mode tuned channel timer pin tuning off tuning on tuning off tuning on tuning off tuning on top00 ppg toggle n/a tmp0 (master) top01 ppg pwm n/a top10 ppg toggle pwm n/a ch0 tmp1 (slave) top11 ppg pwm n/a top20 ppg toggle n/a tmp2 (master) top21 ppg pwm n/a top30 ppg toggle pwm n/a ch1 tmp3 (slave) top31 ppg pwm n/a table 8-7. timer output functions (2/2) free-running mode pwm mode triangular wave pwm mode tuned channel timer pin tuning off tuning on tuning off tuning on tuning off tuning on toq00 ppg toggle pwm toggle n/a ch1 tmq0 (slave) toq01 to toq03 ppg pwm triangular wave pwm n/a toq10 ppg toggle toggle tmq1 (master) toq11 to toq13 ppg pwm triangular wave pwm toq20 ppg toggle pwm toggle triangular wave pwm ch2 tmq2 (slave) toq21 to toq23 ppg pwm triangular wave pwm remark the timing of transmitting data from the compare register of the master timer to the compare register of the slave timer is as follows. ppg: cpu write timing toggle, pwm, triangular wave pwm: timing at wh ich timer counter and compare register match topn0 and toqm0 (n = 0 to 3, m = 0 to 2) chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 435 figure 8-21. tuned operation image (tmp2, tmp3, tmq0) tmp2 top21 (pwm output) 16-bit timer/counter unit operation tmp2 (master ) + tmp3 (slave) + tmq0 (slave) tuned operation five pwm outputs are available when pwm is operated as a single unit. 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare tmp3 top31 (pwm output) tmq0 toq01 (pwm output) toq02 (pwm output) toq03 (pwm output) top21 (pwm output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top30 (pwm output) 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare top31 (pwm output) toq01 (pwm output) toq00 (pwm output) toq02 (pwm output) toq03 (pwm output) seven pwm outputs are available when pwm is operated in tuned operation mode. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 436 figure 8-22. basic operation timing of tuned pwm function (tmp2, tmp3, tmq0) top20 top21 top30 toq00 toq01 toq02 toq03 top31 tp2ccr0 tp2ce inttp2cc0 match interrupt inttp2cc1 match interrupt inttp3cc0 match interrupt inttp3cc1 match interrupt inttq0cc0 match interrupt inttq0cc1 match interrupt inttq0cc2 match interrupt inttq0cc3 match interrupt tp3ce tq0ce ffffh 0000h tmp2 16-bit counter d 00 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 d 00 d 70 d 60 d 50 d 40 d 30 d 20 d 10 tp2ccr1 d 10 tp3ccr0 d 20 tp3ccr1 d 30 tq0ccr0 d 40 tq0ccr1 d 50 tq0ccr2 d 60 tq0ccr3 d 70 chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 437 8.7 cautions (1) capture operation when the capture signal occurs before the count clock is available and the selected count clock is slower than the internal sampling signal, the value in the capture register is ffffh (instead of 0000h). (a)free running timer mode count clock 0000h ffffh tqnce bit tqnccr0 register ffffh 0002h 0000h tiqn0 pin input capture trigger 16 bit counter sampling clock capture trigger input (b)pulse mode count clock 0000h ffffh tqnce bit tqnccr0 register ffffh 0001h 0000h tiqn0 pin input capture trigger 16 bit counter sumpling clock caputure torigger input chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 438 (2) notes on rewriting the tq0ccr0 register to change the value of the tq0ccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tq0ccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttq0cc0 signal is generated. therefore, the inttq0cc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 8 16-bit timer/event counter q user?s manual u17830ee1v0um00 439 (3) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tq0o vf bit to 0 with the clr instruction and by writing 8- bit data (bit 0 is 0) to the tq0opt0 r egister. to accurately detect an overflow, read the tq0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tq0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tq0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tq0ovf bit) overflow flag (tq0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. user?s manual u17830ee1v0um00 440 chapter 9 16-bit interval timer m the v850es/fx2 include a 16-bit interval timer m (tmm0). table 9-1. number of channels of timer m product number of channels v850es/fe2 v850es/ff2 v850es/fg2 v850es/fj2 1 channel (tmm) 9.1 features timer m (tmm) supports only a clear & start mode. it does not support a free-running mode. to use timer m in a manner equivalent to in the free-running mode, set the co mpare register to ffffh and start the 16-bit counter. a match interrupt will occur when the timer overflows. ? interval function ? clock selection 8 ? simple counter 1 (the simple counter is a counter that does not use a c ounter read buffer. this counter cannot be read during timer count operation.) ? simple compare 1 (the simple compare register is a regi ster that does not use a compare write buffer. no data can be written to this compare register during timer count operation.) ? compare match interrupt 1 chapter 9 16-bit interval timer m user?s manual u17830ee1v0um00 441 9.2 configuration tmm consists of the following hardware. table 9-2. configuration of tmm item configuration timer register 16-bit counter register tmm compare register 0 (tm0cmp0) control register tmm0 control register (tm0ctl0) figure 9-1. block diagram of timer m tm0ctl0 internal bus f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt controller 16-bit counter match clear inttm0eq0 tm0cmp0 tm0ce tm0cks2 tm0cks1tm0cks0 selector remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency intwt: watch timer interrupt request signal chapter 9 16-bit interval timer m user?s manual u17830ee1v0um00 442 (1) 16-bit counter this is a 16-bit counter that counts the internal clock. the 16-bit counter cannot be read or written. (2) tmm0 compare register 0 (tm0cmp0) the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. the same value can always be written to the tm0cmp0 register by software. after reset: 0000h r/w address: tm0cmp0: fffff694h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tm0cmp0 caution: rewriting the tm0cmp0 register is prohibited while the timer is working (tm0ce = 1). but the same value can be rewritten. chapter 9 16-bit interval timer m user?s manual u17830ee1v0um00 443 9.3 control register (1) tmm0 control register 0 (tm0ctl0) the tm0ctl0 register is an 8-bit register that controls the operation of tmm. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. rewriting the tm0ctl0 register is prohibited while t he timer is working. only the tm0ce bit can always be rewritten. (1/2) after reset: 00h r/w address: tm0ctl0: fffff690h 7 6 5 4 3 2 1 0 tm0ctl0 tm0ce 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 tm0ce control of operation of timer m0 0 disable internal operating clock o peration (asynchronously reset tmm0). 1 enable internal operating clock operation. the tm0ce bit controls the internal operating cl ock and asynchronously resets tmm0. when this bit is cleared to 0, the internal operating clock of tmm is stopped (fixed to the low level), and tmm0 is asynchronously reset. when the tm0ce bit is set to 1, the internal operat ing clock is enabled within two input clocks, and the timer counts up. tm0cks2 tm0cks1 tm0cks0 selection of internal count clock 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /64 1 0 0 f xx /512 1 0 1 intwt 1 1 0 f r /8 1 1 1 f xt cautions: 1. set tm0cks2 to tm0cks0 bits at tm0ce = 0. when the tm0ce bit is set from 0 to 1, the tm0cks2 to tm 0cks0 bits can be set at the same time. 2. set bit 6-3 to 0. remark f xx : main system clock frequency f r : ring-osc clock frequency f xt : subclock frequency chapter 9 16-bit interval timer m user?s manual u17830ee1v0um00 444 (2/2) resolution and maximum number of counts resolution [ s] maximum count time [ms] internal count clock f xx = 16 mhz f xx = 20 mhz f xx = 16 mhz f xx = 20 mhz f xx 0.0625 0.050 4.10 3.28 f xx /2 0.125 0.100 8.19 6.55 f xx /4 0.250 0.200 16.38 13.11 f xx /64 4.000 3.200 262.14 209.72 f xx /512 32.000 25.600 2097.15 1677.72 resolution [ s] maximum count time [ms] internal count clock f r = 100 khz (min.) f r = 200 khz (typ.) f r = 400 khz (max.) f r = 100 khz (min.) f r = 200 khz (typ.) f r = 400 khz (max.) f r /8 80.0 40.0 20.0 5242.88 2621.44 1310.72 resolution [ s] maximum count time [ms] internal count clock f xt = 32.768 khz f xt = 32.768 khz f xt 30.52 2000.00 chapter 9 16-bit interval timer m user?s manual u17830ee1v0um00 445 9.4 operation 9.4.1 interval timer mode in the interval timer mode, a match interrupt signal (in ttm0eq0) is output when the value of the 16-bit counter matches the value of tmm0 compare regi ster 0 (tm0cmp0). at the same time, the counter is cleared to 0000h and starts counting up. figure 9-2. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d d interval (d + 1) interval (d + 1) interval (d + 1) interval (d + 1) figure 9-3. timing of operation in interval timer mode count clock 16-bit counter m ? 2 m ? 1 m m 0000h 0001h tm0cmp0 inttm0eq0 caution to set m clocks as the interval peri od, set the tm0cmp0 register to m ? 1. when ffffh is set to the tm0cmp0 register, timer m perfor ms an operation similar to that in the free-running mode. chapter 9 16-bit interval timer m user?s manual u17830ee1v0um00 446 9. 5 cautions (1) clock generator and clock enable timing it takes the 16-bit counter up to the following time to st art counting after the tm0ctl0.tm0ce bit is set to 1, depending on the count clock selected. selected count clock maximum time before counting start f xx 2/f xx f xx /2 6/f xx f xx /4 24/f xx f xx /64 128/f xx f xx /512 1024/f xx intwt second rising edge of intwt signal f r /8 16/f r f xt 2/f xt figure 9-4. count operation start timing clock for counting count clock clock enable signal (internal signal) tm0ce bit (2) rewriting the tm0cmp0 and tm0ctl0 regist ers is prohibited while tmm0 is operating. if these registers are rewritten while the tm0ce bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tm0c tl0.tm0ce bit to 0, and re-set the registers. user?s manual u17830ee1v0um00 447 chapter 10 watch timer functions 10.1 functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. figure 10-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f x f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler prescaler 3 note clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 selector selector selector selector reset note for details of prescaler 3, see figure 10-2 block di agram of prescaler 3 . remark f brg : prescaler 3 output frequency f x : main clock oscillation frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt intwti: interval timer interrupt chapter 10 watch timer functions user?s manual u17830ee1v0um00 448 figure 10-2. block di agram of prescaler 3 f x f x /8 f x /4 f x /2 f x bgcs00 bgcs01 bgce0 3-bit prescaler 8-bit counter output control match f bgcs f brg prescaler mode register 0 (prsm0) prescaler compare register0 (prscm0) 2 selector remark f bgcs : prescaler 3 count clock frequency f brg : prescaler 3 output frequency f x : oscillation frequency (1) watch timer the watch timer generates an interrupt re quest (intwt) at time intervals of 0.5 or 0.25 seconds by using the subclock (f xt = 32.768 khz). caution when using a clock obtained by dividing th e main clock as the watch timer count clock, set the prsm0 and prscm0 registers according to th e main clock frequency that is used so as to obtain a divided clock frequency of 32.768 khz. if 32.768 khz cannot be generated, correcti on using software is n ecessary to realize the watch function. (2) interval timer the watch timer generates an interrupt request (intwti) at time intervals specified in advance. table 10-1. interval time of interval timer interval time operation at f w = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.2 ms 2 11 1/f w 62.5 ms remark f w : watch timer clock frequency chapter 10 watch timer functions user?s manual u17830ee1v0um00 449 10.2 configuration the watch timer consists of the following hardware. table 10-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm) chapter 10 watch timer functions user?s manual u17830ee1v0um00 450 10.3 control registers the watch timer operation mode register (wtm) controls the watch timer. be fore operating the watch timer, set the count clock and the interval time. (1) watch timer operation mode register (wtm) the wtm register enables or di sables the count clock and operation of t he watch timer, sets the interval time of the prescaler, controls the operat ion of the 5-bit counter, and sets the set time of the watch flag. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. (1/2) wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.90 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.2 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of watch timer interrupt time wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h remarks 1. f w : watch timer clock frequency f xt : subclock frequency f brg : prescaler 3 output frequency 2. values in parentheses apply to operation with f w = 32.768 khz chapter 10 watch timer functions user?s manual u17830ee1v0um00 451 (2/2) 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency f xt : subclock frequency f brg : prescaler 3 output frequency 2. values in parentheses apply to operation with f w = 32.768 khz chapter 10 watch timer functions user?s manual u17830ee1v0um00 452 10.4 operation 10.4.1 operation as watch timer the watch timer generates an interrupt request at fixed ti me intervals. the watch timer operates using time intervals of 0.5 or 0.25 second s with the subclock (32.768 khz). the count operation starts when the wtm1 and wtm0 bits of the wtm register are set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit c ounter are cleared and the count operation stops. the time of the watch timer can be adjusted by clearing the wtm1 bit to 0 and then the 5-bit counter. at this time, an error of up to 15.6 ms may occur. the interval timer may be cleared by clearing the wtm0 bit to 0. however, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (intwt). 10.4.2 operation as in terval timer the watch timer can also be used as an interval timer that repeatedly generates an inte rrupt at intervals specified by a preset count value. the interval time can be selected by the wt m4 to wtm7 bits of the wtm register. table 10-3. interval time of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency f xt : subclock frequency f brg : prescaler 3 output frequency chapter 10 watch timer functions user?s manual u17830ee1v0um00 453 figure 10-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remark f w : watch timer clock frequency values in parentheses apply to operation with count clock f w = 32.768 khz. n: number of interval timer operations 10.4.3 cautions the following time is required before the first watch ti mer interrupt request signal (intwt) is generated after operation is enabled (wtm1 and wtm0 bits of wtm register = 1). figure 10-4. example of generation of watc h timer interrupt request signal (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt signal to be generated (2 9 1/32768 = 0.015625 s longer). the intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt chapter 10 watch timer functions user?s manual u17830ee1v0um00 454 10.5 prescaler 3 prescaler 3 has the following function. ? generation of watch timer count clock (s ource clock: main oscillation clock) 10.5.1 control registers (1) prescaler mode register 0 (prsm0) the prsm0 register controls the generat ion of the watch timer count clock. this register can be read or written in 8-bit units. reset input clears this register to 00h. f x = 4 mhz 250 ns 500 ns 1 s 2 s 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled (fixed to 0) enabled bgce0 0 1 prescaler output f x f x /2 f x /4 f x /8 f x = 5 mhz 200 ns 400 ns 800 ns 1.6 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of prescaler 3 clock (f bgcs ) after reset: 00h r/w address: fffff8b0h cautions 1. do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. 2. set the prsm0 register befo re setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. chapter 10 watch timer functions user?s manual u17830ee1v0um00 455 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset input clears this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register during watc h timer operation. 2. set the prscm0 register before setting th e bgce0 bit of the prsm0 register to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. 10.5.2 generation of watch timer count clock the clock input to the watch timer (f brg ) can be corrected to approximate 32.768 khz. the relationship between the main clock (f x ), prescaler 3 clock selection bi t bgcsn setting value (m), prscm0 register setting value (n) and output clock (f brg ) is as follows. f brg = example: when f x = 4.00 mhz, m = 0 (bgcs01 bit = bgcs00 bit = 0), and n = 3dh f brg = 32.787 khz remark f brg : watch timer count clock n: prscm0 register se tting value (1 to ffh) in the case of a prscm0 register setting value of 00h, n = 256 m: bgcsn bit setting value (0 to 3) n = 00, 01 f x 2 m n 2 user?s manual u17830ee1v0um00 456 chapter 11 functions of watchdog timer 2 11.1 functions watchdog timer 2 has the following functions. ? default-start watchdog timer reset mode: reset operation upon overflow of wa tchdog timer 2 (generation of wdt2res signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note ? input selectable from main clock and ring-osc as the source clock note restoring using the reti instruction following non-maskable interrupt servicing due to a non- maskable interrupt request signal (intwdt2) is not possible. therefore, following completion of interrupt servicing, perform a system reset. figure 11-1. block diag ram of watchdog timer 2 f x /2 7 wdt2res (internal reset signal) wdcs22 intwdt2 wdcs21 wdcs20 wdcs23 wdcs24 0 wdm21 wdm20 f x /2 16 to f xx /2 23 , f r /2 12 to f r /2 19 3 clear 3 2 run2 f r /2 3 clock input controller output controller selector internal bus 16-bit counter watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) remark f x : oscillation frequency f r : ring-osc clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdt2res: watchdog timer 2 reset signal chapter 11 functions of watchdog timer 2 user?s manual u17830ee1v0um00 457 11.2 configuration watchdog timer 2 consists of the following hardware. table 11-1. configuration of watchdog timer 2 item configuration control registers oscillation stabilization time select register (osts) watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 11.3 control registers (1) oscillation stabilization time select register (osts) the osts register selects the oscillation stabilizati on time following reset or release of the stop mode. this register can be read or written in 8-bit units. reset input sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 setting prohibited after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x note the oscillation stabilization time and se tup time are required when the software stop mode and idle mode are released, respectively. chapter 11 functions of watchdog timer 2 user?s manual u17830ee1v0um00 458 (2) watchdog timer mode register 2 (wdtm2) this register is a special register. this regist er can be written only by a specific sequence. the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. this register can be read any number of times, but it can be written only once following reset release. reset input sets this register to 67h. 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. for details of the wdcs20 to w dcs24 bits, see table 11-2 watchdog timer 2 clock selection. 2. if the wdtm2 register is rewritten twice after reset, an overflow signal is forcibly generated. but, the overflow signal does not o ccur, even if the wdtm 2 register is written twice after the watch do g timer is suspended. 3. to stop the operation of watchdog timer 2 set the rstp bit of the rcm register to 1 (to stop ring-osc) and the wdtm2 register to 1fh. chapter 11 functions of watchdog timer 2 user?s manual u17830ee1v0um00 459 table 11-2. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs 20 selected clock 100 khz (min.) 200 khz (typ.) 400 khz (max.) 0 0 0 0 0 2 12 /f r 41.0 ms 20.5 ms 10.2 ms 0 0 0 0 1 2 13 /f r 81.9 ms 41.0 ms 20.5 ms 0 0 0 1 0 2 14 /f r 163.8 ms 81.9 ms 41.0 ms 0 0 0 1 1 2 15 /f r 327.7 ms 163.8 ms 81.9 ms 0 0 1 0 0 2 16 /f r 655.4 ms 327.7 ms 163.8 ms 0 0 1 0 1 2 17 /f r 1,310.7 ms 655.4 ms 327.7 ms 0 0 1 1 0 2 18 /f r 2,621.4 ms 1,310.7 ms 655.4 ms 0 0 1 1 1 2 19 /f r (default) 5,242.9 ms 2,621.47 ms 1,310.7 ms f x = 4 mhz f x = 5 mhz 0 1 0 0 0 2 16 /f x 16.4 ms 13.1 ms 0 1 0 0 1 2 17 f x 32.8 ms 26.2 ms 0 1 0 1 0 2 18 /f x 65.5 ms 52.4 ms 0 1 0 1 1 2 19 /f x 131.1 ms 104.9 ms 0 1 1 0 0 2 20 /f x 262.1 ms 209.7 ms 0 1 1 0 1 2 21 /f x 524.3 ms 419.4 ms 0 1 1 1 0 2 22 /f x 1,048.6 ms 838.9 ms 0 1 1 1 1 2 23 /f x 2,097.2 ms 1,677.7 ms 1 1 1 1 1 stop chapter 11 functions of watchdog timer 2 user?s manual u17830ee1v0um00 460 (3) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cleared and counting restarted by wr iting ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. reset input sets this register to 9ah. wdte run2 run2 0 1 after reset: 9ah r/w address: fffff6d1h run2 selection of watchdog timer operation mode note counting stopped counter cleared and counting started note once run2 is set to 1 it cannot be cleared to 0 by software. therefore, count ing can be stopped only by reset input after counting is started. cautions 1. when a value other than ?ach? is writ ten to the wdte register , an overflow signal is forcibly output. 2. when a 1-bit memory mani pulation instruction is execute d for the wdte register, an overflow signal is forcibly output (an error results in the assembler). 3. the read value of the wdte register is ?9ah? (which differs from written value ?ach?). user?s manual u17830ee1v0um00 461 chapter 12 a/d converter remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. the description focus on the v850es/fj2 12.1 overview this product features an a/d converte r. the number of channels varies depending on the product as shown below. product name number of channels v850es/fe2 10 v850es/ff2 12 v850es/fg2 16 v850es/fj2 24 12.2 functions the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle up to 24 analog input signal channels (ani0 to anin). remark n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) the a/d converter has the following features. { 10-bit resolution { 10, 12, 16 or 24 channels { successive approximation method { operating voltage: av ref0 = 4.0 to 5.5 v { analog input voltage: 0 v to av ref0 { the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot scan mode { the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode { power-fail monitor function (conversion result compare function) chapter 12 a/d converter user?s manual u17830ee1v0um00 462 the block diagram of the a/d converter is shown below. figure 12-1. block diagram of a/d converter ani0 : : ani1 ani2 ani13 ani14 ani15 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm voltage comparator ada0cr0 ada0cr1 : : ada0cr2 ada0cr22 ada0cr23 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit tap selector ada0ets0 bit inttp2cc0 inttp2cc1 ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar chapter 12 a/d converter user?s manual u17830ee1v0um00 463 12.3 configuration the a/d converter includes the following hardware. table 12-1. configuration of a/d converter item configuration analog inputs 10 channels for v850es/fe2 (ani0 to ani9 pins) 12 channels for v850es/ff2 (ani0 to ani11 pins) 16 channels for v850es/fg2 (ani0 to ani15 pins) 24 channels for v850es/fj2 (ani0 to ani23 pins) registers successive approximation register (sar) a/d conversion result registers 0 to 9 for v850es/fe2 (ada0cr0 to ada0cr9) 0 to 11 for v850es/ff2 (ada0cr0 to ada0cr11) 0 to 15 for v850es/fg2 (ada0cr0 to ada0cr15) 0 to 23 for v850es/fj2 (ada0cr0 to ada0cr23) a/d conversion result registers high where only higher 8 bits can be read 0h to 9h for v850es/fe2 (ada0cr0h to ada0cr9h) 0h to 11h for v850es/ff2 (ada0cr0h to ada0cr11h) 0h to 15h for v850es/fg2 (ada0cr0h to ada0cr15h) 0h to 23h for v850es/fj2 (ada0cr0h to ada0cr23h) control registers a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register 0 (ada0s) power-fail compare mode register (ada0pfm) power-fail compare threshold value register (ada0pft) (1) successive approximation register (sar) the sar register compares the voltag e value of the analog input signal wit h the voltage tap (compare voltage) value from the d/a converter, and holds the comparison re sult starting from the most significant bit (msb). when the comparison result has been held down to the le ast significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar register are transferred to the ada0crn register. remark n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) (2) sample & hold circuit the sample & hold circuit samples each of the analog in put signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (3) voltage comparator the voltage comparator compares a voltage value t hat has been sampled and held with the voltage value of the d/a converter. (4) d/a converter this d/a converter is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. chapter 12 a/d converter user?s manual u17830ee1v0um00 464 (5) anin pins these are analog input pins for the a/d converter channels and are used to input analog signals to be converted into digital signals. pins other than the on e selected as the analog input by the ada0s register can be used as input port pins. remark n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) cautions 1. make sure that the voltages input to the ani0 to ani23 pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. 2. the analog input pins (ani0 to ani23) f unction alternately as input port pins (p70 to p79, p710 to p715, p120 to p127). if any of ani0 to ani23 is selected and a/d converted, do not execute an input instruction to ports 7 and 12 during conversion. if executed, the conversion resolution may be degraded. (6) av ref0 pin this is the pin used to input the reference voltage of the a/d converter. the signals input to the ani0 to ani23 pins are converted to digital signals based on the voltage applied between the av ref0 and av ss pins. (7) av ss pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used. 12.4 control registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft) remark n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) chapter 12 a/d converter user?s manual u17830ee1v0um00 465 (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that specif ies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, bit 0 is read-only. reset input clears this register to 00h. ada0ce ada0ce 0 1 stops conversion enables conversion a/d conversion control ada0m0 0 ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode specification ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display ada0md1 0 0 1 ada0md0 0 1 1 continuous select mode continuous scan mode one-shot scan mode setting prohibited specification of a/d converter operation mode ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge after reset: 00h r/w address: fffff200h other than above cautions 1. if bit 0 is wr itten, this is ignored. 2. changing the ada0fr2 to ada0 fr0 bits of the ada0m1 register during conversion (ada0ce0 bit = 1) is prohibited. 3. when not using the a/d converter, stop the operation by setting the ada0ce bit to 0 to reduce the current consumption. 4. the resolution of the first input terminal immediately after a/d conversion can be decreased. for deta ils, refer to 12. 6. (7) avref0 pin. 5. when the subclock is operati ng and the main clock is stopped, accessing the ada0m0 register is disabled. for details, see 3.4.10 (2). chapter 12 a/d converter user?s manual u17830ee1v0um00 466 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit register that controls the conversion time specification. this register can be read or written in 8-bit or 1-bit units. reset input clears this bit to 00h. after reset: 00h r/w address: fffff201h 7 6 5 4 3 2 1 0 ada0m1 ada0hs1 ada0hs0 0 0 ada0fr3 ada0fr2 ada0fr1 ada0fr0 caution be sure to clear bits 5 and 4 to 0. remark for a/d conversion time setting examples, see table 12-2 . table 12-2. conversion mode setting example ada0hs ada0fr3 to ada0fr0 a/d conversion time including sample time 1 0 3 2 1 0 a/d conversion time a/d sampling time f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz a/d stabilization time note 0 0 0 0 31/f xx 8/f xx setting prohibited setting prohibited 7.75 s 16/f xx 0 0 0 1 62/f xx 16/f xx 3.10 s 3.88 s 15.50 s 31/f xx 0 0 1 0 93/f xx 24/f xx 4.65 s 5.81 s setting prohibited 47/f xx 0 0 1 1 124/f xx 32/f xx 6.20 s 7.75 s setting prohibited 50/f xx 0 1 0 0 155/f xx 40/f xx 7.75 s 9.69 s setting prohibited 50/f xx 0 1 0 1 186/f xx 48/f xx 9.30 s 11.63 s setting prohibited 50/f xx 0 1 1 0 217/f xx 56/f xx 10.85 s 13.56 s setting prohibited 50/f xx 0 1 1 1 248/f xx 64/f xx 12.40 s 15.50 s setting prohibited 50/f xx 1 0 0 0 279/f xx 72/f xx 13.95 s setting prohibited setting prohibited 50/f xx 1 0 0 1 310/f xx 80/f xx 15.50 s setting prohibited setting prohibited 50/f xx 1 0 1 0 341/f xx 88/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 0 1 1 372/f xx 96/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 0 0 403/f xx 104/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 0 1 434/f xx 112/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 1 1 0 465/f xx 120/f xx setting prohibited setting prohibited setting prohibited 50/f xx 1 x 1 1 1 1 496/f xx 128/f xx setting prohibited setting prohibited setting prohibited 50/f xx note when the ada0ce bit of the ada0m0 register is changed from 0 to 1 to secure the a/d converter stabilization time, the first a/d conversion starts after one of the above clock values is input. chapter 12 a/d converter user?s manual u17830ee1v0um00 467 (3) a/d converter mode register (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge detected) timer trigger mode 0 (when inttp2cc0 interrupt request generated) timer trigger mode 1 (when inttp2cc1 interrupt request generated) setting prohibited after reset: 00h r/w address: fffff203h 6543210 7 caution be sure to clear bits 7 to 2 to 0. chapter 12 a/d converter user?s manual u17830ee1v0um00 468 (4) a/d converter channel specification register 0 (ada0s) the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff202h 7 6 5 4 3 2 1 0 ada0s 0 0 0 ada0s4 ada0s3 ada0s2 ada0s1 ada0s0 ada0s4 ada0s3 ada0s2 ada0s1 ada0s0 select mode scan mode 0 0 0 0 0 ani0 ani0 0 0 0 0 1 ani1 ani0, ani1 0 0 0 1 0 ani2 ani0 to ani2 0 0 0 1 1 ani3 ani0 to ani3 0 0 1 0 0 ani4 ani0 to ani4 0 0 1 0 1 ani5 ani0 to ani5 0 0 1 1 0 ani6 ani0 to ani6 0 0 1 1 1 ani7 ani0 to ani7 0 1 0 0 0 ani8 ani0 to ani8 0 1 0 0 1 ani9 ani0 to ani9 0 1 0 1 0 ani10 ani0 to ani10 0 1 0 1 1 ani11 ani0 to ani11 0 1 1 0 0 ani12 ani0 to ani12 0 1 1 0 1 ani13 ani0 to ani13 0 1 1 1 0 ani14 ani0 to ani14 0 1 1 1 1 ani15 ani0 to ani15 1 0 0 0 0 ani16 ani0 to ani16 1 0 0 0 1 ani17 ani0 to ani17 1 0 0 1 0 ani18 ani0 to ani18 1 0 0 1 1 ani19 ani0 to ani19 1 0 1 0 0 ani20 ani0 to ani20 1 0 1 0 1 ani21 ani0 to ani21 1 0 1 1 0 ani22 ani0 to ani22 1 0 1 1 1 ani23 ani0 to ani23 other than above setting prohibited remark ani0 to ani9 (v850es/fe2) ani0 to ani12 (v850es/ff2) ani0 to ani15 (v850es/fg2) ani0 to ani23 (v850es/fj2) chapter 12 a/d converter user?s manual u17830ee1v0um00 469 (5) a/d conversion result regist ers n, nh (ada0crn, ada0crnh) the ada0crn register is a 16-bit register that stor es the a/d conversion result. ada0crn consist of n registers. the ada0crn and ada0crnh registers are read-only, in 16-bit or 8-bit units. however, specify the ada0crn register for 16-bit access and the ada0crnh r egister for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the ada0crn register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion resu lt are read from the ada0crnh register. after reset: 00h r address: ada0cr0 fffff210h, ada0cr1 fffff212h ada0cr2 fffff214h, ada0cr3 fffff216h ada0cr4 fffff218h, ada0cr5 fffff21ah ada0cr6 fffff21ch, ada0cr7 fffff21eh ada0cr8 fffff220h, ada0cr9 fffff222h ada0cr10 fffff224h, ada0cr11 fffff226h ada0cr12 fffff228h, ada0cr13 fffff22ah ada0cr14 fffff22ch, ada0cr15 fffff22eh ada0cr16 fffff230h, ada0cr17 fffff232h ada0cr18 fffff234h, ada0cr19 fffff236h ada0cr20 fffff238h, ada0cr21 fffff23ah ada0cr22 fffff23ch, ada0cr23 fffff23eh 15 14 13 12 11 10 9 8 ada0crn ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 7 6 5 4 3 2 1 0 ad1 ad0 0 0 0 0 0 0 after reset: 00h r address: ada0cr0h fffff211h, ada0cr1h fffff213h ada0cr2h fffff215h, ada0cr3h fffff217h ada0cr4h fffff219h, ada0cr5h fffff21bh ada0cr6h fffff21dh, ada0cr7h fffff21fh ada0cr8h fffff221h, ada0cr9h fffff223h ada0cr10h fffff225h, ada0cr11h fffff227h ada0cr12h fffff229h, ada0cr13h fffff22bh ada0cr14h fffff22dh, ada0cr15h fffff22fh ada0cr16h fffff231h, ada0cr17h fffff233h ada0cr18h fffff235h, ada0cr19h fffff237h ada0cr20h fffff239h, ada0cr21h fffff23bh ada0cr22h fffff23dh, ada0cr23h fffff23fh 7 6 5 4 3 2 1 0 ada0crnh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 remark n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) chapter 12 a/d converter user?s manual u17830ee1v0um00 470 cautions 1. a write operation to the ada0m0 a nd ada0s registers may cause the contents of the ada0crn register to become undefined. after the conversion, read the conversion result before writing to the ada0m0 and ada0s regi sters. correct conversion results may not be read if a sequence other than the above is used. 2. when the subclock is operating and the main clock is stopped, accessing the ada0crn and ada0crnh registers is disabled. for details, see 3.4.10 (2). the relationship between the analog volta ge input to the analog input pins (ani0 to ani11) and the a/d conversion result (of a/d conversion result register n (ada0crn)) is as follows. 0.5) 1,024 av v ( int ada0cr ref0 in + = or, 1,024 av 0.5) (ada0cr v 1,024 av 0.5) (ada0cr ref0 in ref0 + < ? int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of a/d conversion result register n (ada0crn) figure 12-2 shows the relationship between the ana log input voltage and the a/d conversion results. chapter 12 a/d converter user?s manual u17830ee1v0um00 471 figure 12-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results (ada0crn) remark n = 0 to 11 chapter 12 a/d converter user?s manual u17830ee1v0um00 472 (6) power-fail compare m ode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. ada0pfe power-fail compare disabled power-fail compare enabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generates an interrupt request signal (intad) when ada0crn ada0pft generates an interrupt request signal (intad) when ada0crn < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h 76 54 321 0 cautions 1. in the select mode, the 8-bit data set to the ada0pft regist er is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specified by the ada0pfc bit, the conversion result is stored in the ada0crn register and the intad signal is ge nerated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if the result matches the c ondition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison r esult, the scan operati on is continued and the conversion result is st ored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after th e scan operation has been completed. (7) power-fail compare thres hold value register (ada0pft) the ada0pft register sets a threshold value that is co mpared with the value of a/d conversion result register nh (ada0crnh). the 8-bit data set to the ada0pft regi ster is compared with the higher 8 bits of the a/d conversion result register (ada0crnh). the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. ada0pft after reset: 00h r/w address: fffff205h 76 54 321 0 chapter 12 a/d converter user?s manual u17830ee1v0um00 473 12.5 operation 12.5.1 basic operation <1> set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter waits for a trigger in the external or timer trigger mode. <2> when a/d conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when the sample & hold circuit samples the input chan nel for a specific time, it enters the hold status, and holds the input analog voltage until a/d conversion is complete. <4> set bit 9 of the successive approximation register ( sar). the voltage of the d/a converter is (1/2) avref0. <5> the voltage difference between t he voltage of the d/a converter and the an alog input voltage is compared by the voltage comparator. if the analog input voltage is higher than (1/2) av ref0 , the msb of the sar register remains set. if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar register is automatically se t and the next comparison is started. depending on the value of bit 9, to which a result has been already se t, <6>, the voltage of the d/a converter is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this voltage of the d/a converter and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. ? analog input voltage R voltage of the d/a converter ? analog input voltage Q voltage of the d/a converter <7> this comparison is continued to bit 0 of the sar register. <8> when comparison of the 10 bits is complete, the valid di gital result is stored in the sar register, which is then transferred to and stored in the ada0crn register. at the same time, an a/d co nversion end inte rrupt request signal (intad) is generated. chapter 12 a/d converter user?s manual u17830ee1v0um00 474 figure 12-3. a/d converter basic operation sar ada0crn intad conversion time sampling time sampling a/d converter operation a/d conversion undefined conversion result conversion result chapter 12 a/d converter user?s manual u17830ee1v0um00 475 12.5.2 trigger mode the timing of starting the conversion oper ation is specified by setting a trigger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardwa re trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0tmd bit of the ada0m0 register is used to set the trigger mode. the hardware trigger modes are set by the ada0tmd1 and ada0tmd0 bits of the ada0m2 register. (1) software trigger mode when the ada0ce bit of the ada0m0 register is set to 1, the signal of the analog input pin (ani0 to ani23 pin) specified by the ada0s register is converted. when conversion is complete, the result is stored in the ada0crn register. at the same time, the a/d conversi on end interrupt request signal (intad) is generated. if the operation mode specified by the ada0md1 and ada0md 0 bits of the ada0m0 register is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during conversion, the conversion is aborted and started again from the beginning. (2) external trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani23) specified by the ada0s register is started when an external trigger is input (to the adtrg pin). which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both ri sing and falling edges) can be specified by using the ada0ets1 and ata0ets0 bits of the ada0m0 register. when the ada0ce bit of the ada0m0 register set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the result of conversion is stored in the ada0crn register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conver sion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during the conversion operation, the conversion is not aborted, and the a/d converter waits for the trigger again. chapter 12 a/d converter user?s manual u17830ee1v0um00 476 (3) timer trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani23) specified by the ada0s register is started by the compare match interrupt request signal (inttp2cc0 or inttp2cc1) of the capture/compare register connected to the timer. the timer com pare match interrupt request signal (inttp2cc0 or inttp2cc1) is selected by the ada0tmd1 and ada0tmd0 bits of the ada0m2 register, and conversion is started at the rising edge of the spec ified compare match interrupt request signal. when the ada0ce bit of the ada0m0 register is set to 1, the a/d converter wait s for a trigger, and starts conversion when the compare match interrupt signal of the timer is input. when conversion is completed, the result of the conversi on is stored in the ada0crn register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conver sion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again. chapter 12 a/d converter user?s manual u17830ee1v0um00 477 12.5.3 operation mode three operation modes are available as t he modes in which to set the ani0 to ani23 pins: continuous select mode continuous scan mode and one-shot scan mode. the operation mode is selected by the ada0md1 and ada0md0 bits of the ada0m0 register. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an ada0crn register on a one-to-one basis. each time a/d conversion is completed, the a/d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is started, unless the ada0 ce bit of the ada0m0 regist er is cleared to 0 (n = 0 to 23). figure 12-4. timing example of continuous select mode operation (ada0s = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 chapter 12 a/d converter user?s manual u17830ee1v0um00 478 (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. the result of each conversion is stored in the ada0crn register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the a/d conversion end interrupt request signal (intad) is generated, and a/d co nversion is started again from the ani0 pin, unless the ada0ce bit of the ada0m0 regist er is cleared to 0 (n = 0 to 23). chapter 12 a/d converter user?s manual u17830ee1v0um00 479 figure 12-5. timing example of continuous s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . . . . . chapter 12 a/d converter user?s manual u17830ee1v0um00 480 (3) one-shot scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital va lues. the result of each conversion is stored in the ada0crn register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the a/d conversion en d interrupt request signal (i ntad) is generated, and a/d conversion is stopped. figure 12-6. timing example of one-shot s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 transformation completion ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . . . . . chapter 12 a/d converter user?s manual u17830ee1v0um00 481 12.5.4 power-fail compare mode the a/d conversion end interrupt r equest signal (intad) can be controlle d as follows by the ada0pfm and ada0pft registers. ? when the ada0pfe bit = 0, the intad signal is generat ed each time conversion is completed (normal use of the a/d converter). ? when the ada0pfe bit = 1 and when the ada0pfc bit = 0, the value of the ada0cr nh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0cr0h ada0pft. ? when the ada0pfe bit = 1 and when the ada0pfc bit = 1, the value of the ada0cr nh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0cr0h < ada0pft. remark n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) in the power-fail compare mode, two modes are available as modes in which to set the ani0 to ani23 pins: continuous select mode an d continuous scan mode. chapter 12 a/d converter user?s manual u17830ee1v0um00 482 (1) continuous select mode in this mode, the result of converting the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conver sion result is stored in the ada0crn register, and the intad signal is not generated. after completion of the fi rst conversion, the next conversion is started, unless the ada0ce bit of the ada0m0 regist er is cleared to 0 (n = 0 to 23). figure 12-7. timing example of continuous select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 ( ani1) data 7 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 2 ( ani1) data 3 ( ani1) data 4 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, the results of converting the voltages of the analog input pins sequent ially selected from the ani0 pin to the pin specified by the ada0s register are st ored, and the set value of the ada0cr0h register of channel 0 is compared with the value of the ada0pft regi ster. if the result of power-fail comparison matches the condition set by the ada0pfc bit of the ada0pfm r egister, the conversion result is stored in the ada0cr0 register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register, and the intad signal is not generated. after the result of the first conver sion has been stored in the ada0cr0 r egister, the results of sequentially converting the voltages on the analog input pins up to t he pin specified by the ada0 s register are continuously stored. after completion of conversion, the next conv ersion is started from the ani0 pin again, unless the ada0ce bit of the ada0m0 r egister is cleared to 0. chapter 12 a/d converter user?s manual u17830ee1v0um00 483 figure 12-8. timing example of continuous scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) data 7 ( ani2) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . . . . . chapter 12 a/d converter user?s manual u17830ee1v0um00 484 (3) one-shot scan mode in this mode, the results of converting the voltages of the analog input pins sequent ially selected from the ani0 pin to the pin specified by the ada0s register are st ored, and the set value of the ada0cr0h register of channel 0 is compared with the value of the ada0pft r egister. if the result of power-fail comparison matches the condition set by the ada0pfc bit of the ada0pfm r egister, the conversion result is stored in the ada0cr0 register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register, and the intad signal is not generated. after the result of the first conversion has been stor ed in the ada0cr0 register, the results of sequentially converting the voltages on the analog input pins up to t he pin specified by the ada0 s register are continuously stored. after completion of conversion, a/d conversion is stop ped. the 1st conversion result after a/d conversion has to be ignored, because it is not good. chapter 12 a/d converter user?s manual u17830ee1v0um00 485 figure 12-9. timing example of on e-shot scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 conversion completion (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani21 ani22 ani23 ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr21 ada0cr22 ada0cr23 . . . . . . . chapter 12 a/d converter user?s manual u17830ee1v0um00 486 12.6 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumpt ion can be reduced by clearing the ada0ce bit of the ada0m0 register to 0. (2) input range of ani0 to ani23 pins input the voltage within the specified range to the ani0 to ani23 pins . if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, th e ani0 to ani23 pins must be effe ctively protected from noise. the influence of noise increases as the output impedance of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 12-10 is recommended. figure 12-10. processing of analog input pin av ref0 v dd gnd0 av ss c = 100 to 1,000 pf (4) alternate i/o the analog input pins (ani0 to ani23) function alternately as port pins. when selecting one of the ani0 to ani23 pins to execute a/d conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop. also the conversion resolution may drop at the pins set as output port pins during a/d conversion if the output current fluctuates due to the ef fect of the external circuit connected to the port pins. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the a/d conversion value may not be as expected due to the in fluence of coupling noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion. chapter 12 a/d converter user?s manual u17830ee1v0um00 487 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if t he contents of the ada0s regi ster are changed. if the analog input pin is changed during a/d co nversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, clear the adif flag before resuming conversion. figure 12-11. generation timing of a/d conversion end interrupt request ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion ada0crn intad anin anin anim anim anim anin anin anim remark n = 0 to 23 m = 0 to 23 chapter 12 a/d converter user?s manual u17830ee1v0um00 488 (6) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 13-14. internal equi valent circuit of anin pin anin c in r in product name r in c in v850es/fe2, ff2, fg2 5.9 k ? 7.0 pf v850es/fj2 6.0 k ? 8.3 pf remarks 1. the above valu es are reference values. 2. n = 0 to 9 (v850es/fe2) n = 0 to 11 (v850es/ff2) n = 0 to 15 (v850es/fg2) n = 0 to 23 (v850es/fj2) chapter 12 a/d converter user?s manual u17830ee1v0um00 489 (7) av ref0 pin (a) the av ref0 pin is used as the power supply pin of th e a/d converter and also supplies power to the alternate-function ports. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 12-10. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power su pply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation as shown in figure 12-12. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 12-12. av ref0 pin processing example av ref0 note av ss main power supply note parasitic inductance (8) reading ada0crn register when the ada0m0 to ada0m2 or ada0s register is writ ten, the contents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before writing to the ada0m0 to ada0m2 and ada0s registers. the correct conversion re sult may not be read at a timing different from the above. (9) standby mode because the a/d converter stops operating in the stop mode, conversion results are invalid, so power consumption can be reduced. operations are resume d after the stop mode is released, but the a/d conversion results after the stop mode is released are invalid. when using the a/d converter after the stop mode is released, before setting the stop mode or releasing the stop mode, clear the ada0m0.ada0ce bit to 0 then set the ada0ce bit to 1 after releasing the stop mode. in the idle1, idle2, or subclock operation mode, oper ation continues. to lower the power consumption, therefore, clear the ada0m0.ada0ce bit to 0. in the idle1 and idle2 modes, since the analog input voltage value cannot be retained, the a/d conversion results a fter the idle1 and idle2 modes are released are invalid. the results of conversions before the id le1 and idle2 modes were set are valid. chapter 12 a/d converter user?s manual u17830ee1v0um00 490 (10) about a/d conversion result the illegal conversion result sometimes occur by noise , in the case that the analogue input pin and also reference voltage input pin receive the influence of noi se. the software processing is necessary; to avoid that exerts bad influence to the system by this illegal conversi on result. next the example of software processing is shown. ? please use the mean value of a/d conversion result of the plural time as the result of a/d conversion. ? in the case that does a/d conversion of the plural ti me continuously and the specific conversion result was obtained, please use the conversion result that is excluded this value. ? please do abnormal processing after abnormal occurrence is confirmed once again, without doing abnormal processing right away, in the case that a/d conversion result that is judged that abnormality occurred to the system was obtained. (11) a/d conversion result hysteresis characteristics the successive comparison type a/d converter holds the a nalog input voltage in the internal sample & holds capacitor and then performs a/d conversi on. after the a/d conversion ha s finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if t he voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the co nversion result is affected by the previous value. thus, even if t he conversion is performed at the same potential, the result may vary. ? when switching the analog input channel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is perfo rmed at the same potential, the result may vary. chapter 12 a/d converter user?s manual u17830ee1v0um00 491 12.7 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that c an be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). t he ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics ta ble does not include the quantization error. figure 12-13. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output chapter 12 a/d converter user?s manual u17830ee1v0um00 492 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 12-14. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input volt age and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 12-15. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error chapter 12 a/d converter user?s manual u17830ee1v0um00 493 (5) full-scale error this is the difference between the actually measured analog input volt age and its theoretical value when the digital output changes from 1?110 to 0?111 (full scale ? 3/2 lsb). figure 12-16. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 12-17. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output chapter 12 a/d converter user?s manual u17830ee1v0um00 494 (7) integral linearity error this error indicates the extent to which the conversion char acteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between the actually measured valu e and its theoretical value where the zero-scale error and full-scale error are 0. figure 12-18. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after an analog input voltage has been assigned. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 12-19. sampling time sampling time conversion time a/d conversion start a/d conversion end user?s manual u17830ee1v0um00 495 chapter 13 asynchronous serial interface a (uarta) remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. the v850es/fx2 includes asynchronous serial interface a (uarta). the number of channels differs depending on the product. table 13-1 shows the number of channels of each product. table 13-1. number of channels of asynchronous serial interface a product name (part number) number of channels v850es/fe2 v850es/ff2 2 (uarta0 to uarta1) v850es/fg2 3 (uarta0 to uarta2) pd70f3237 3 (uarta0 to uarta2) v850es/fj2 pd70f3238 pd70f3239 4 (uarta0 to uarta3) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 496 13.1 features ? transfer rate 300 bps to 312.5 kbps (using in ternal system clock of 20 mhz and dedicated baud rate generator) ? full-duplex communication uarta receive data register n (uanrx) uarta transmit data register n (uantx) ? 2-pin configuration txdan: output pin of transmit data rxdan: input pin of receive data ? reception error detection function ? parity error ? framing error ? overrun error ? interrupt sources: 2 types ? reception complete interrupt (intuanr): an interrupt is generated in the recepti on enabled status by oring three types of reception errors. it is also generated wh en receive data is transferred from the shift register to receive buffer register n after completion of serial transfer. ? transmission enable interrupt (intua nt): generated when transmit data is transferred from the transmit buffer register to the shift register in the transmission enabled status. ? character length: 7 or 8 bits ? parity function: odd, even, 0, none ? transmission stop bit: 1 or 2 bits ? dedicated baud rate generator ? msb/lsb first transfer selectable ? transmit/receive data reversible ? 13 to 20 bits selectable for sbf (sync break field) transmission in lin (local interconnect network) communication format ? 11 or more bits recognizable for sbf reception in lin communication format ? sbf reception flag remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 497 13.2 configuration uarta consists of the following hard ware table 13-2. configuration of uarta0 to uarta2 item configuration register uartan reception shift register uartan reception data register (uanrx) uartan transmit shift register uartan transmit data register (uantx) reception data input pd70f3237: 3 (rxdan) pd70f3239: 4 transmit data output pd70f3237: 3 (txdan) pd70f3239: 4 baud rate note clock input 1 (ascka0) control register uartan control register (uanctl0 to uanctl3) uartan option control register (uanopt0) uartan status register (uanstr) note in the baud rate clock input which is supported only for uarta0 remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) the pins of asynchronous serial interface a (uarta) function alternately as port pins. for how to select the alternate functions, refer to the description of registers in chapter 4 port functions . table 13-3. list of pins of asynchronous serial interface a pin name alternate-function pin i/o function rxda0 p31/intp7 serial receive data input (uarta0) rxda1 p91/kr7 serial receive data input (uarta1) rxda2 p39/intp8 serial receive data input (uarta2) rxda3 p80/intp14 input serial receive data input (uarta3) txda0 p30 serial transmit data output (uarta0) txda1 p90/kr6 serial transmit data output (uarta1) txda2 p38 serial transmit data output (uarta2) txda3 p81 output serial transmit data output (uarta3) ascka0 p32/tip00/top00 input baud rate clock input of uarta0 remark the number of channels differs depending on the product. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 498 figure 13-1. block diagram of asynchronous serial interface a internal bus uanotp0 uanctl0 uanstr uanctl1 uanctl2 receive shift register uanrx filter selector uantx transmission controller reception controller baud rate generator intuanr intuant txdan rxdan ascka0 f xx to f xx /2 10 reception unit transmission unit transmit shift register baud rate generator selector internal bus clock selector remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) note: uarta0 only. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 499 13.2.1 control registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that specifies the operation of the asynchronous serial interface a. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the input clock of the asynchronous serial interface a. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that controls the baud rate of the asynchronous serial interface a. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit regi ster that controls serial transfer by the asynchronous serial interface a. (5) uartan status register (uanstr) the uanstr register is a collection of flags that indicate the contents of the error when a reception error occurs. the corresponding reception error flag is set to 1 when a reception error occurs, and is reset to 0 when the uanstr register is read. (6) uartan receive shift register this shift register converts the serial data input to t he rxdan pin into parallel data. when data of 1 byte is received and then a stop bit is detected, the rece ive data is transferred to the uanrx register. this register cannot be directly manipulated. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer register that holds receive data. when seven characters are received, 0 is stored in the higher bit (in lsb-first reception). while reception is enabled, receive data is transferred from the uartan receive shift register to the uanrx register in synchronization with completion of shift-in processing of one frame. when the data has been transferred to t he uanrx register, a reception complete interrupt request signal (intuanr) is generated. (8) uartan transmit shift register the transmit shift register converts the parallel data tr ansferred from the uantx register into serial data. when data of 1 byte is transferred from the uantx regist er, the data of the shift r egister is output from the txdan pin. this register cannot be directly manipulated. (9) uartan transmit data register (uantx) the uantx register is an 8-bit buffer for transmit data. by writing transmit data to the uantx register, a transmission operation is started. when data can be wr itten to the uantx register (when data of one frame is transferred from the uantx register to the uartan tran smit shift register), a transmission enable interrupt request signal (intuant) is generated. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 500 13.3 control registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that controls the serial transfer operation of uartan. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 10h. (1/2) after reset: 10h r/w address: ua0ctl0: fffffa00h, ua1ctl0: fffffa10h, ua2ctl0: fffffa20h, ua3ctl0: fffffa30h 7 6 5 4 3 2 1 0 uanctl0 uanpwr uantxe uanrxe uandir uanps1 uanps0 uancl uansl n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) uanpwr control of operation of uartan 0 disable clock operation (a synchronously reset uartan). 1 enable clock operation. the uanpwr bit controls the operating clock and asynchronously resets uartan. when this bit is cleared to 0, the output of the txdan pin is fixed to the high level. uantxe transmission operation enable 0 stop transmission operation. 1 enable transmission operation. when the uantdl bit is cleared to 0, then the uant xe bit is cleared to 0, the output of the txdan pin is fixed to the high level. when the uantdl bit is set to 1, then the uantxe bit is set to 0, the output of the txdan pin is fixed to the low level. this bit is synchronized with the operating clock. when the transmission unit is initialized, therefore, set the uantxe bit from 0 to 1. the transmission operation will be enabled two clocks later. a value written to the uantxe bit is ignored when the uanpwr bit = 0. uanrxe reception operation enable 0 stop reception operation. 1 enable reception operation. when the uanrxe bit is cleared to 0, the reception operation is stopped. consequently, even if specified data is transferred, the reception complete interrupt is not output, and the uanrx register is not updated. the uanrxe bit is synchronized with the operating clock. when the reception unit is initialized, therefore, set the uanrxe bit from 0 to 1. the reception operation will be enabled two clocks later. a value written to the uanrxe bit is ignored when the uanpwr bit = 0. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 501 (2/2) uandir selection of transfer direction mode (msb/lsb) 0 msb first 1 lsb first this bit can be rewritten only when the uanpwr bit = 0 or when uantxe bit = uanrxe bit = 0. ? set the ua0dir bits to "1" to execute transmission/reception in lin format. uanps1 uanps0 selection of parity for transmission selection of parity for reception 0 0 no parity output reception without parity 0 1 output 0 parity reception with 0 parity 1 0 output odd parity identified as odd parity 1 1 output even parity identified as even parity ? this bit can be rewritten only when the uanpwr bit = 0 or when the uantxe bit = uanrxe bit = 0. ? if ?reception with 0 parity? is selected for reception, the parity is not identified. consequently, the uanpe bit of the uanstr register is not set, and an error interrupt is not generated even if a parity error occurs. ? clear the uanps1 and uanps0 bits to ?00? to execute transmission/reception in lin format. uancl specification of data character leng th of one frame of transmit/receive data. 0 7 bits 1 8 bits this bit can be rewritten only when the uanpwr bit = 0 or when the uantxe bit = uanrxe bit = 0. ? set the ua0cl bits to "1" to execute transmission/reception in lin format. uansl specification of stop bit length of transmit data. 0 1 bit 1 2 bits this bit can be rewritten only when the uanpwr bit = 0 or when the uantxe bit = uanrxe bit = 0. remark for details of the parity, refer to 13.5.9 types and operation of parity . chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 502 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the clock of uartan. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: ua0ctl1: fffffa01h, ua1ctl1: fffffa11h, ua2ctl1: fffffa21h, ua3ctl1: fffffa31h 7 6 5 4 3 2 1 0 uanctl1 0 0 0 0 uancks3 uancks2 uancks1 uancks0 n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) uancks3 uancks2 uancks1 uancks0 selection of base clock (f xclk ) 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1024 1 0 1 1 external clock note (ascka0 pin) other than above setting prohibited note the ascka0 pin can be used only when uarta0 is used. setting this bit is prohibited when uarta1 to uarta3 are used. caution this register can be rewritten only when the uanpwr bit of the uanctl0 register = 0. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 503 (3) uartan control register 2 (uanctl2) the uanctl2 register is used to select the baud rate (serial transfer rate) clock of uartan. this register can be read or written in 8-bit units. reset input sets this register to ffh. after reset: ffh r/w address: ua0ctl2: fffffa02h, ua1ctl2: fffffa12h, ua2ctl2: fffffa22h, ua3ctl2: fffffa32h 7 6 5 4 3 2 1 0 uanctl2 uanbrs7 uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) uanbrs7 uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 rated value (k) serial clock 0 0 0 0 0 0 setting prohibited 0 0 0 0 0 1 0 0 4 f xclk /4 0 0 0 0 0 1 0 1 5 f xclk /5 0 0 0 0 0 1 1 0 6 f xclk /6 : : : : : : : : : : 1 1 1 1 1 1 0 0 252 f xclk /252 1 1 1 1 1 1 0 1 253 f xclk /253 1 1 0 1 1 1 1 0 254 f xclk /254 1 1 1 1 1 1 1 1 255 f xclk /255 remarks: 1. f xclk is the frequency of the base clock selected by the uanctl1 register. 2. refer to table 13.6 about setting samples of fxclk. 3. : don't care cautions 1. this register can be rewritten only when the uanpwr bit of the uanctl0 register = 0 or when the uantxe bit = uanrxe bit = 0. 2. the baud rate is the serial clock divided by two. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 504 (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register that controls the serial transfer operation of uartan. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 14h. after reset: 14h r/w address: ua0opt0: fffffa03h, ua1opt0: fffffa13h, ua2opt0: fffffa23h, ua3opt0: fffffa33h 7 6 5 4 3 2 1 0 uanopt0 uansfr uansrt uanstt uansls2 uansls1 uansls0 uantdl uanrdl n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) uansfr sbf reception flag 0 when uanctl0 register?s uanpwr bit = uanrxe bit = 0. or, on normal completion of sbf reception 1 sbf reception in progress ? this bit indicates that sbf (sync brake field) is received in lin communication. ? in case of an sbf reception error, the uansrf bit is hold to 1, and then sbf reception is started again. ? the uansfr bit can only be read. uansrt sbf reception trigger 0 D 1 sbf reception trigger ? this is the reception trigger bit of sbf in lin co mmunication. it is always 0 when read. to receive sbf, set the uansrt bit to 1 to enable sbf reception. ? set the uanpwr bit and uanrxe bit of the uanc tl0 register to 1 and then set the uansrt bit. uanstt sbf transmission trigger 0 D 1 sbf transmission trigger ? this is the transmission trigger bit of sbf in lin communication. it is always 0 when read. ? set the uanpwr bit and uantxe bit of the uanc tl0 register to 1 and then set the uanstt bit. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 505 (2/2) uansls2 uansls1 uansls0 sbf length selection 1 0 1 outputs 13 bits (reset value). 1 1 0 outputs 14 bits. 1 1 1 outputs 15 bits. 0 0 0 outputs 16 bits. 0 0 1 outputs 17 bits. 0 1 0 outputs 18 bits. 0 1 1 outputs 19 bits. 1 0 0 outputs 20 bits. this bit can be set when the uanpwr bit of the uanctl0 register = 0 or when the uantxe bit of the uanctl0 register = 0. uantdl transmit data level bit 0 normal output of transfer data 1 inverted output of transfer data ? the value of the txdan bit can be inverted by the uantdl bit. ? this bit can be set when the uanpwr bit of the uanctl0 register = 0 or when the uantxe bit of the uanctl0 register = 0. uanrdl receive data level bit 0 normal input of transfer data 1 inverted input of transfer data ? the value of the rxdan pin can be inverted by the uanrdl bit. ? this bit can be set when the uanpwr bit of the uanctl0 register = 0 or when the uanrxe bit of the uanctl0 register = 0. remark for details of the parity, refer to 13.5.9 types and operation of parity . (5) uartan status register (uanstr) the uanstr register is an 8-bit regi ster that indicates the transfer stat us of uartan and the contents of a reception error. this bit can be read or written in 8-bit or 1-bit units, but the uantsf bit can only be read. the uanpe, uanfe, and uanove bits can be read or written, but they can only be cleared by writing 0 to them, and cannot be set by writing 1 (if 1 is written to these bits, they hold the current status). the following table shows the initialization conditions of these bits. register/bit initialization conditions uanstr register ? reset input ? uanpwr bit of uanctl0 register = 0 uantsf bit ? uantxe bit of uanctl0 register = 0 uanpe, uanfe, uanove bits ? writing of 0 ? uanrxe bit of uanctl0 register = 0 chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 506 after reset: 00h r/w address: ua0str: fffffa04h, ua1str: fffffa14h, ua2str: fffffa24h, ua3str: fffffa34h 7 6 5 4 3 2 1 0 uanstr uantsf 0 0 0 0 uanpe uanfe uanove n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) uantsf transfer status flag 0 ? when uanpwr bit of uanctl0 register = 0 or when uantxe bit of uanctl0 register = 0 ? if next transfer data is not in uantx after completion of transfer 1 writing to uantx register the uantsf bit is always 1 when transmission is executed continuo usly. before initializing the transmission unit, check that the uantsf bit = 0. if the transmission unit is initialized while the uantsf bit = 1, the transmit data cannot be guaranteed. uanpe parity error flag 0 ? when uanpwr bit of uanctl0 register = 0 or when uanrxe bit of uanctl0 register = 0 ? when 0 is written to this bit 1 when the parity of the received data does not match the parity bit ? the operation of the uanpe bit differs depending on how the uanps1 and uanps0 bits of the uanctl0 register are set. ? although the uanpe bit can be read or written, it can only be cleared by writing 0, and cannot be set by writing 1. it holds the current status when 1 is written. uanfe framing error flag 0 ? when uanpwr bit of uanctl0 register = 0 or when uanrxe bit of uanctl0 register = 0 ? when 0 is written 1 when a stop bit is not detected on reception ? only the first bit of the receive data is checked as a stop bit, regardless of the value of the uansl bit of the uanctl0 register. ? although the uanfe bit can be read or written, it can only be cleared by writing 0, and cannot be set by writing 1. it holds the current status when 1 is written. uanove overrun error flag 0 ? when uanpwr bit of uanctl0 register = 0 or when uanrxe bit of uanctl0 register = 0 ? when 0 is written 1 when receive data is set to the uanrx register and the next reception operation is completed before that data is read ? if an overrun error occurs, the next receive data is not written to the receive buffer but discarded. ? although the uanove bit can be read or written, it can only be cleared by writing 0, and cannot be set by writing 1. it holds the current status when 1 is written. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 507 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer re gister that stores the parallel data converted by the receive shift register. on completion of reception of 1 byte of data, the data stored in the receive shift register is transferred to the uanrx register. if the data length is specified to be 7 bits and when data is received with the lsb first, the receive data is transferred to bits 6 to 0 of the uanrx register, and the msb is always 0. if data is received with the msb first, the receive data is transferred to bits 7 to 1 of the uanrx register, and the lsb is always 0. if an overrun error (uanove) occurs, the receive data at that time is not transferred to the uanrx register. the uanrx register is read-only, in 8-bit units. reset input and setting the uanpwr bit of the uanc tl0 register to 0 set this register to ffh. after reset: ffh r address: ua0rx: fffffa06h, ua1rx: fffffa16h, ua2rx: fffffa26h, ua3rx: fffffa36h 7 6 5 4 3 0 1 2 uanrx n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) (7) uartan transmit data register (uantx) the uantx register is an 8-bit register that sets transmit data. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. after reset: ffh r/w address: ua0tx: fffffa07h, ua1tx: fffffa17h, ua2tx: fffffa27h, ua3tx: fffffa37h 7 6 5 4 3 2 1 0 uantx n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 (pd70f3238, pd70f3239) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 508 13.4 interrupt request signals uartan generates the following two types of interrupt request signals. ? reception complete interrupt request signal (intuanr) ? transmission enable interrupt request signal (intuant) of these two interrupt request signals, the reception comple te interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. table 13-4. interrupts and their default priority interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intuanr) when data is shifted in to the receive shift register with reception enabled, and transferred to the uanrx register, the reception complete interrupt request signal is generated. a reception error interrupt can also be generated in this interrupt request signal if a reception error occurs. moreover, read the uanstr register to check t hat the result of reception is not an error. reception complete interrupt request signals are not generated while reception is disabled. (2) transmission enable interr upt request signal (intuant) the transmission enable interrupt request signal is generated when transmit data is transferred from the uantx register to the uartan transmit sh ift register with transmission enabled. remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 509 13.5 operation 13.5.1 data format full-duplex serial data is transmitted or received. the transmit/receive data is in the format shown in figure 13-2, consisting of a start bit, character bits, a parity bit, and 1 or 2 stop bits. the character bit length in one data fr ame, parity, stop bit length, and whether data is transferred with the msb or lsb first, are specified by the uanctl0 register. the uantdl bit of the uanopt0 regist er is used to specify whether the signal output from the txdan pin is inverted or not. ? start bit ? 1 bit ? character bit ? 7 or 8 bits ? parity bit ? even parity, odd parity, 0 parity, or no parity ? stop bit ? 1 or 2 bits figure 13-2. format of transmit/receive data of uarta (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer da ta: 55h, txdan inverted d7 d6 d5 d4 d3 d2 d1 d0 1 data frame start bit parity bit stop bit (d) 7-bit data length, lsb first, odd parity, 2 stop bits, transfer data: 36h d0 d1 d2 d3 d4 d5 d6 1 data frame start bit parity bit stop bit stop bit (e) 8-bit data length, lsb first, no parity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 510 13.5.2 sbf transmission/reception format the v850es/fx2 has an sbf (sync break field) transm ission/reception control function as a lin (local interconnect network) function. remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automot ive network. lin communication is single-master communication, and up to 15 slaves can be connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method a nd is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figure 13-3. outline of tr ansmission operation of lin sleep bus wakeup signal frame sync break field sync field ident field data field data field check sum field intuant interrupt txdan (output) note 3 8 bits note 1 note 2 13 bits 55h transmission data transmission data transmission data transmission data transmission note 4 sbf transmission notes 1. the interval between each field is controlled by software. 2. sbf is output by hardware. the out put width is the bit length specified by the uansbl2 to uansbl0 bits of the uanopt0 register. if the output width must be adjusted more finely, the uanbrst7 to uanbrs0 bits of the uanctln register can be used. 3. the wakeup signal frame is substituted by 80h transfer in the 8-bit mode. 4. a transmission enable interrupt request signal (intuant ) is output each time transmission is started. the intuant signal is also output when sbf transmission is started. remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 511 figure 13-4. outline of reception operation of lin reception interrupt (intuanr) edge detection capture timer disable disable enable rxdan (intput) enable note 2 13 bits note 5 data reception sbf reception note 3 note 4 note 1 sf reception id reception sleep bus wakeup signal frame sync break field sync field ident field data field data field check sum field data reception data reception notes 1. the wakeup signal is detected by the edge detector of the pin, and enables uartan and places it in the sbf reception mode. 2. reception is performed until the stop bit is detect ed. when sbf reception of 11 bits or more is detected, it is assumed that normal sbf reception has been completed, and the interrupt signal is output. if sbf reception of less than 11 bits is detected, it is assumed that an sbf reception error has occurred. no interrupt signal is output and uartan returns to the sbf reception mode. 3. when sbf reception is completed normally, the interrupt signal is output. the sbf reception complete interrupt enables a timer. error detection by the uanove, uanpe, and uanfe bits of the uanstr register is suppressed. consequently, neither e rror detection processing of uart communication nor data transfer from the uartan receive shift register to uanrx register is executed. the uartan receive shift register holds the default value ffh. 4. the rxdan pin is connected to ti (capture input) of the timer and the tr ansfer rate and baud rate error are calculated. after sf reception, uartan is no lo nger enabled. the value with the baud rate error corrected is set to the uanctl2 register to enable reception. 5. the checksum field is distinguished by software. af ter csf reception, uartan is initialized and the sbf mode is set again by software. remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 512 13.5.3 sbf transmission transmission is enabled when the uanpwr bit and uantxe bit of the uanctl0 register are set to 1, and sbf transmission is started by setting the sbf transmission trigger (uanstt bit of the uanopt0 register) to 1. after that, a 13-bit to 20-bit low level, as specified by the uansls2 to uansls0 bits of the uanopt0 register, is output. a transmission enable interrupt request signal (intua nt) is generated when sbf transmission is started. after sbf transmission is completed, the uanstt bit is automatically cleared, and the uart transmission mode is restored. the transmission operation is stopped until the data to be tr ansmitted next is written to the uantx register or the sbf transmission trigger (uanstt bit) is set. cautions 1. this macro becomes er ror when sbf is transmitted with data reception because it doesn't assume the thing that sbf is tr ansmitted while receiving data. 2. set (1) neither sb f reception trigger bit uansrt nor sbf transmission trigger bit (uanstt) while receiving sbf (uansrf = 1). figure 13-5. sbf transmission intuant interrupt 12345678910111213 stop bit uanstt bit is set. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 513 13.5.4 sbf reception when the uanpwr bit of the uanctl0 register is set to 1 and then the uanrx bit of the uanctl0 register is set to 1, uarta waits for reception. when the sbf reception trigger (uansrt bi t of the uanopt0 register) is set to 1, uarta waits for sbf reception. in the sbf reception waiting status, t he rxdan pin is monitored and the start bi t is detected, in the same manner as in the reception wait status of uart. when the start bit is detected, recepti on is started, and the internal counter counts up at the selected baud rate. when the stop bit is received, a reception complete inte rrupt request signal (intuanr) is generated as normal processing, if the width of sbf is 11 bi ts or longer. the uansrf bit of the ua nopt0 register is aut omatically cleared, and sbf reception is completed. error detection by the ua nove, uanpe, and uanfe bits of the uanstr register is suppressed, and error detection processing of uart co mmunication is not performed. moreover, data is not transferred from the uartan receive shift register to t he uanrx register, and the uanrx register holds the default value ffh. if the width of sbf is 10 bi ts or less, the interrupt does not occu r, reception is completed, and the sbf reception mode is restored again, as error processi ng. at this time, the uansrf bit is not cleared. figure 13-6. sbf reception (a) normal sbf reception (stop bit is de tected when sbf wid th exceeds 10.5 bits) uansrf 123456 11.5 7 8 9 10 11 intuanr interrupt (b) sbf reception error (stop bit is detect ed when sbf width is 10.5 bits or less) ua0srf 123456 10.5 78910 intuanr interrupt chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 514 13.5.5 uart transmission when the uanpwr bit of the uanctl0 register is set to 1, the txdan pin outputs a high level. if the uantxe bit of the uanctl0 regist er is subsequently set to 1, transmission is enabled. transmission is started by writing transmit data to the uantx register. a start bit, parity bi t, and stop bit are automatically appended to the transmit data. when transmission is started, the data in the uantx register is transferred to the uartan transmit shift register. as soon as the data of the uantx r egister has been transferred to the uartan transmit shift register, a transmission enable interrupt request signal (intuant) is generated. then the uartan transmit shift register sequentially outputs the data to the txdan pin, starting from the lsb. w hen the intuant signal is generated, writing the next transfer data to t he uantx register is enabled. by writing the data to be transmitted ne xt to the uantx register during transfe r, transmission can be continuously executed. figure 13-7. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuant chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 515 13.5.6 procedure of continuous transmission with uartan, the next transmit data can be written to the uantx register as soon as the uartan transmit shift register has started its shift operation. the timing at which data is transferred to the uartan transmit shift register can be identified by the transmission enable interrupt request signal (intuant). the intuant signal enables continuous transmission even while an interrupt is bei ng serviced after transmission of 1 data frame, so that an efficient communication rate can be realized. during continuous transmission, do not wr ite the next transmit data to the ua ntx register before a transmit request interrupt signal (intuant) is generated after transmit data is written to the uantx r egister and transferred to the uartan transmit shift register. if a value is written to t he uantx register before a transm it request interrupt signal is generated, the previously set transmit data is overwritten by the latest transmit data. caution continuous transmission op erating (uantsf bit is 1), can not change register. while continuous transmission is being executed, ex ecute initialization after checking that the uantsf bit is 0. if initialization is executed while the uantsf bit is 1, the transmit da ta cannot be guaranteed. the communication rate from the stop bit to the following start bit expands more than usually for two clocks of the operation clock at a continuous transmission. figure 13-8. processing flow of continuous transfer start set registers. write uantx. yes yes no no transmission interrupt occurred? necessary number of data written? end chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 516 figure 13-9. timing of continuous transmission operation (a) start of transfer start data (1) data (1) txdan uantx transmit shift register intuant uantsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) end of transfer start data (n-1) data (n-1) data (n-1) data (n) ff data (n) uattxd uantx transmit shift register intuant uantsf uanpwr or uantxe parity stop stop start data (n) parity parity stop chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 517 13.5.7 uart reception when the uanpwr bit of the uanctl0 register is set to 1 and then the uanrx bit of the uanctl0 register is set to 1, uarta waits for reception. in the reception wait st atus, the rxdan pin is monitor ed and the start bit is detected. to recognize the start bit, a two- stage detection routine is used. first the falling edge of the rxdan pin is detected and sampling is started. the start bit is recognized if the rxdan pin is low level at the start bit sampling point. when the star t bit is recognized, reception is started, and serial data is sequentially stored in the uartan receive shift register at the selected baud rate. when the stop bit is received, a reception complete inte rrupt request signal (intuanr) is generated and, at the same time, the data of the uartan receive shift register is written to the uanrx register. if an overrun error occurs (indicated by the uanove bit of the uanstr register), the receive data is not wri tten to the uanrx register. even if a parity error (indicated by the uanpe bit of the ua nstr register) or framing error (indicated by the uanfe bit of the uanstr register) occurs in the middle of recept ion, reception continues to th e reception position of the stop bit. the intuanr signal is generated when reception is completed. figure 13-10. uart reception d0 d1 d2 d3 d4 d5 d6 d7 intuanr uanrx start bit parity bit stop bit cautions 1. be sure to read the uanrx register even when a recept ion error occurs. unless the uanrx register is read, an overrun error occurs when the next data is received, and the reception error status persists. 2. it is always assumed that the number of stop bits is 1 du ring reception. a second stop bit is ignored. 3. when reception is completed, read the uanr x register after the reception complete interrupt request signal (intuanr) has been generated, a nd clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 befo re the ntuanr signal is generated, the read value of the uanrx register cannot be guaranteed. 4. if receive completion processing (intuanr si gnal generation) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intuanr si gnal may be generated in spite of these being no data stored in the uanrx register. to co mplete reception without waiting intuanr signal generation, be sure to clear (0) the interrupt request flag (uanrif) of the uanric register, after setting (1) the interrupt mask flag (uanrmk) of the interrupt control register (uanric) and then set (1) the uanpwr bit = 0 or uanrxe bit = 0. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 518 13.5.8 reception errors reception errors are classified into three types: parity e rrors, framing errors, and overrun errors. as a result of receiving data, an error flag is set in the uanstr r egister, and a reception complete interrupt request signal (intuanr) is generated. by reading the contents of the uanstr re gister in the reception error interrupt servicing, which error has occurred during reception can be checked. the reception error flag is cleared by writing 0 to it. ? receive data read flow figure 13-11. receive data read flow start no intuanr signal generated? error occurs? end yes no yes error processing read uanrx register read uanstr register caution when an intuanr signal is generated, the ua nstr register must be read to check for errors. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 519 ? reception error causes table 13-5. reception error causes error flag reception error cause uanpe parity error received parity bit does not match setting. uanfe framing error stop bit is not detected. uanove overrun error next data reception is completed before data is read from receive buffer. when reception errors occur, perform the followin g procedures depending upon the kind of error. ? parity error if false data is received due to problems such as noi se in the reception line, discard the received data and retransmit. ? framing error a baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing each other, and then start the communication again. ? overrun error since the next reception is completed before reading receiv e data, 1 frame of data is discarded. if this data was needed, do a retransmission. caution if a receive error interrupt occurs during cont inuous reception, read the contents of the uanstr register must be read before the next recepti on is completed, and then perform error processing. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 520 13.5.9 types and operation of parity caution when using the lin function, fix the uanps1 and uanps0 bits of the uanctl0 register to ?00?. the parity bit is used to detect a bit error in communication data. usually, the same type of parity bit is used on both the transmission side and reception side. even parity and odd parity can be used to detect a ?1? bit error (odd number). with zero parity and no parity, no errors are detected. (1) even parity (a) during transmission the number of bits that are ?1? in the transmit data, including the parity bit, is controlled to be even. the value of the parity bit is as follows. ? number of bits that are ?1? in transmit data is odd: 1 ? number of bits that are ?1? in transmit data is even: 0 (b) during reception the number of bits that are ?1? in the receive data, including the parity bi t, is counted. if it is odd, a parity error occurs. (2) odd parity (a) during transmission opposite to even parity, the number of bits that are ?1? in the transmit data, including the parity bit, is controlled to be odd. the value of the parity bit is as follows. ? number of bits that are ?1? in transmit data is odd: 0 ? number of bits that are ?1? in transmit data is even: 1 (b) during reception the number of bits that are ?1? in t he receive data, including the parity bit, is counted. if it is even, a parity error occurs. (3) 0 parity the parity bit is cleared to 0 during transmi ssion, regardless of the transmit data. the parity bit is not checked during re ception. therefore, a parity error does not occur regardless of whether the parity bit is 0 or 1. (4) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no parity bit. because no par ity bit is used, a parity error does not occur. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 521 13.5.10 noise filter of receive data the rxdan pin is sampled using the uart internal clock (f xclk ). when the same sampling value is read twice, the match det ector output changes and the rxdan signal is sampled as the input data. therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see figure 13-13 ). see 13.6 (1) (a) base clock regarding the base clock. moreover, since the circuit is as shown in figure 13-12, the processing that goes on wit hin the receive operation is delayed by 3 clocks in relation to the external signal status. figure 13-12. noise filter circuit match detector in base clock (f xclk ) rxdan qin ld_en q internal signal c internal signal b in q internal signal a figure 13-13. timing of rxdan signal judged as noise internal signal b base clock rxdan (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 522 13.6 dedicated baud rate generator the dedicated baud rate generator consists of a sour ce clock selector and 8-bit programmable counters, and generates a serial clock for transmission/reception by uartan . the output of the dedicat ed baud rate generator can be selected as the serial clock on a channel by channel basis. 8-bit counters are provided separately for transmission and reception. (1) configuration of baud rate generator figure 13-14. configurati on of baud rate generator clock (f xclk) selector uanpwr 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxen (uanrxe) uanctl1: uancks3 to uancks0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 ascka0 note note the ascka0 pin can be used only for uarta0. it cannot be used for uarta1 to uarta3. remarks 1. n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) 2. f xx : internal system clock 3. f xclk = base clock frequency (a) base clock the clock selected by the uancks3 to uancks0 bits of the uanctl1 register is supplied to the 8-bit counter when the uanpwr bit of the uanctl0 register is 1. this clock is called the base clock, and its frequency is called f xclk . (b) generation of serial clock a serial clock can be generated in accordance with the setting of the uanct l1 and uanctl2 registers the base clock is selected by using the uancks3 to uancks0 bits of the uanctl1 register. the division ratio of the 8-bit counter can be sele cted by using the uanbrs7 to uanbrs0 bits of the uanctl2 register. chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 523 (2) uartan control register 1 (uanctl1) the uanctl1 register is used to select the clock for uartan. for details, refer to 13.3 (2) uartan control register 1 (uanctl1 ). (3) uartan control register 2 (uanctl2) the uanctl2 register is used to select the baud rate (serial transfer rate) clock for uartan. for details, refer to 13.3 (3) uartan control register 2 (uanctl2) . (4) baud rate the baud rate can be calculated by the following expression. baud rate = [bps] f xclk = frequency of base clock selected by uancks 3 to uancks0 bits of uanctl1 register k = value set by uanbrs7 to uanbrs0 bits of uanctl2 register (k = 4, 5, 6, ?, 255) (5) error of baud rate the baud rate error is calculated by the following expression. error (%) = ? 1 100 [%] = ? 1 100 [%] cautions 1. the baud rate error during transmission must be with in the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (7) permissible baud rate range for reception. example : frequency of base clock = 20 mhz = 20,000,000 hz set value of uanbrs7 to uanbrs0 bits of uanctl2 register = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20,000,000/ (2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] f xclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate) f xclk 2 k target baud rate chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 524 (6) example of baud rate setting table 13-6. baud rate generator set data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) 300 09h 41h 0.16 0ah 1ah 0.16 08h 41h 0.16 600 08h 41h 0.16 0ah 0dh 0.16 07h 41h 0.16 1200 07h 41h 0.16 09h 0dh 0.16 06h 41h 0.16 2,400 06h 41h 0.16 08h 0dh 0.16 05h 41h 0.16 4,800 05h 41h 0.16 07h 0dh 0.16 04h 41h 0.16 9,600 04h 41h 0.16 06h 0dh 0.16 03h 41h 0.16 19,200 03h 41h 0.16 05h 0dh 0.16 02h 41h 0.16 31,250 01h a0h 0.00 01h 80h 0.00 00h a0h 0.00 38,400 01h 82h 0.16 00h d0h 0.16 00h 82h 0.16 76,800 00h 82h 0.16 00h 68h 0.16 00h 41h 0.16 153,600 00h 41h 0.16 00h 34h 0.16 00h 21h ? 1.36 312,500 00h 20h 0.00 00h 1ah ? 1.54 00h 10h 0.00 remarks: 1. f xx : internal system clock err: baud rate error [%] 2. n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 525 (7) permissible baud rate range for reception the permissible baud rate error during reception is shown below. caution be sure to set the baud rate error for re ception to within the permissible error range, by using the expressions shown below. figure 13-15. permissible baud rate range for reception fl 1 data frame (11 fl) flmin flmax transfer rate of uartan bit 0 start bit bit 1 bit 7 parity bit permissible minimum transfer rate permissible maximum transfer rate bit 0 start bit bit 1 bit 7 parity bit latch timing bit 0 start bit bit 1 bit 7 parity bit stop bit stop bit stop bit remark n = 0 to 1 (v850es/fe2, v850es/ff2) n = 0 to 2 (v850es/fg2, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) as shown in figure 13-15, the receive data latch timing is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. fl = (brate) ? 1 brate: uartan baud rate (n = 0 to 3) k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 526 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartan and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 13-7. maximum/minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.52% ? 3.61% 20 +4.26% ? 4.30% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.72% remarks 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2 chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 527 (8) transfer rate for continuous transmission the transfer rate from the stop bit to the start bit of the next data is extended two clocks when continuous transmission is executed. however, the timing on the recept ion side is initialized when the start bit is detected, and therefore, the transfer result is not affected. figure 13-16. transfer rate for continuous transmission bit 0 start bit start bit bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit in second byte bit 0 where 1 bit data length is fl, stop bit length is flstp, and base clock frequency is f xclk , the stop bit length can be calculated by the following expression. flstp = fl + 2/f xclk therefore, the transfer rate for continuous transmission is as follows. transfer rate = 11 x fl + 2/f xclk chapter 13 asynchronous serial interface a (uarta) user?s manual u17830ee1v0um00 528 13.7 cautions (1) when the clock supply to uartan is stopped (for exam ple, in idle1, idle2, or stop mode), the operation stops with each register retaining the value it had i mmediately before the clock supply was stopped. the txdan pin output also holds and outputs the value it had immediately before the clock supply was stopped. however, the operation is not guarant eed after the clock supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the uanctl0.uanpwr, uanctl0.uanrxen, and uanctl0.uantxen bits to 000. (2) the rxda1 and kr7 pins must not be used at the same ti me. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) in uartan, the interrupt caused by a communication error does not occur. when performing the transfer of transmit data and receive data using dma transfer, error processing cannot be performed even if errors (parity, overrun, framing) occur during transfer. eit her read the uanstr register after dma transfer has been completed to make sure that there are no errors, or read the uanstr register during communication to check for errors. (4) start up the uartan in the following sequence. <1> set the uanctl0.uanpwr bit to 1. <2> set the ports. <3> set the uanctl0.uantxe bit to 1, uanctl0.uanrxe bit to 1. (5) stop the uartan in the following sequence. <1> set the uanctl0.uantxe bit to 0, uanctl0.uanrxe bit to 0. <2> set the ports and set the uanctl0.uanpwr bit to 0 (it is not a problem if port setting is not changed). (6) in transmit mode (uanctl0.uanpwr bit = 1 and uanctl0.uantxe bit = 1), do not overwrite the same value to the uantx register by software because transmission starts by writing to this register. to transmit the same value continuously, overwrite the same value. (7) in continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks more than usual. however, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. (8) when break command is based and uarta receives data for on-chip debug mode, over run error is occurred. user?s manual u17830ee1v0um00 529 chapter 14 3-wire serial interface (csib) remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. the v850es/fx2 includes a 3-wire serial interface (csib). the number of channels differs dependi ng on the product. following table show s the number of channels of each product. table 14-1. number of channels of 3-wire serial interface b product name (part number) number of channels v850es/fe2 v850es/ff2 v850es/fg2 2 (csib0 to csib1) v850es/fj2 3 (csib0 to csib2) 14.1 features ? master mode and slave mode selectable ? 3-wire serial interface for 8-bit to 16-bit transfer ? interrupt request signals (intcbnt and intcbnr) ? serial clock and data phase selectable ? transfer data length selectable from 8 to 16 bits in 1-bit units ? data transfer with msb- or lsb-first selectable ? 3-wire sobn: serial data output sibn: serial data input sckbn: serial clock i/o ? transmission mode, reception mode, and transmission/reception mode selectable ? transfer rate : 8 mbps - 4.9 kbps (fxx=20 mhz, using internal clock) remark n = 0 to 1 (v850es/fe2, v850es/ff2, v850es/fg2) n = 0 to 2 (v850es/fj2) chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 530 14.2 configuration csibn consists of the following hardware table 14-2. configuration of csibn item configuration register csibn reception data register (cbnrx) csibn transmit data register (cbntx) reception data input sibn transmit data output sobn serial clock i/o sckbn control register csibn control register (cbnctl0 to cbnctl2) csibn status register (cbnstr) remark n = 0 to 1 (v850es/fe2, v850es/ff2, v850es/fg2) n = 0 to 2 (v850es/fj2) the pins of the 3-wire serial interface (csibn) function al ternately as port pins. for how to select the alternate function, refer to the descriptions of the registers in chapter 4 port functions . table 14-3. list of 3-wi re serial interface pins pin name alternate-function pin i/o function sib0 p40 serial receive data input (csib0) sib1 p97/tip20/top20 serial receive data input (csib1) sib2 p910 input serial receive data input (csib2) sob0 p41 serial transmit data input (csib0) sob1 p98 serial transmit data input (csib1) sob2 p911 output serial transmit data input (csib2) sckb0 p42 serial clock i/o (csib0) sckb1 p99 serial clock i/o (csib1) sckb2 p912 i/o serial clock i/o (csib2) remark the number of channels differs depending on the product. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 531 figure 14-1. block diagram of 3-wire serial interface internal bus cbnctl2 cbnctl0 cbnstr controller intcbnr sobn intcbnt cbntx so latch phase control shift register cbnrx cbnctl1 phase control sibn f xx /128 (n = 2) top01 (n = 1) f brg (n = 0) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 sckbn selector remark n = 0 to 1 (v850es/fe2, v850es/ff2, v850es/fg2) n = 0 to 2 (v850es/fj2) chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 532 (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. if reception is enabled, a reception operation is started when the cbnrx register is read. if the transfer data length is 8 bits, the lower 8 bits of the cbnrx register are read-only in 8-bit units as the cbnrxl register. reset input clears this register to 0000h. in addition to reset input, the cbnrx register can be in itialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. after reset: 0000h r address: cb0rx: fffffd04h, cb1rx: fffffd14h, cb2rx: fffffd24h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cbnrx (n = 0 to 2) (2) csibn transmit data register (cbntx) the cbntx register is a 16-bit buffer register to which transfer data of csib is written. this register can be read or written in 16-bit units. if transmission is enabled, a transmission operation is started when the cbntx r egister is written. if the transfer data length is 8 bits, the lower 8 bits of t he cbntx register can be read or written in 8-bit units as the cbntxl register. reset input clears this register to 0000h. after reset: 0000h r/w address: cb0tx: fffffd06h, cb1tx: fffffd16h, cb2tx: fffffd26h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cbntx (n = 0 to 2) remark the communication start conditions are shown below. transmission mode (cbntxe bit = 1, cbnrxe bit = 0): write to cbntx register transmission/reception mode (cbntxe bit = 1, cb nrxe bit = 1): write to cbntx register reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 533 14.3 control registers (1) csibn control register 0 (cbnctl0) this register controls the serial transfer operation of csib. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. (1/2) after reset: 01h r/w address: cb0ctl0: fffffd00h, cb1ctl0: fffffd10h, cb2ctl0: fffffd20h 7 6 5 4 3 2 1 0 cbnctl0 cbnpwr cbntxe note1 cbnrxe note1 cbndir note1 0 0 cbntms note1 cbnsce (n = 0 to 2) cbnpwr specification of csib operation stop or enable 0 stop clock operation (asynchronously reset csibn). 1 enable clock operation. the cbnpwr bit controls the operating clock of csib and resets the internal circuit. cbntxe note1 specification of transmission operation stop or enable 0 stop transmission. 1 enable transmission. when the cbxtxe bit is cleared to 0, the serial output pin sobn is fixed to the low level and communication is stopped. cbnrxe note1 reception operation enable 0 stop reception. 1 enable reception. when the cbnrxe bit is cleared to 0, because re ception is stopped, the reception complete interrupt is not output and the receive data in the cbnrx register is not updated even if the specified data is transferred. cbndir note1 specification of transfer direction mode (msb/lsb) 0 msb first 1 lsb first cbntms note1 specification of transfer mode 0 single transfer mode 1 continuous transfer mode when the cbntms bit = 0, the single transfer mode is set in which continuous transmission/reception is not supported. even wh en only transmission is executed, an interrupt is output on completion of reception transfer. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 534 (2/2) cbnsce specification of start transfer disable or enable 0 disable transfer operation. 1 enable transfer operation. in master mode this bit enables or disables the communication start trigger. (a) in single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode a communication operation can be started only by writing data to the cbntx register when the cbnsce bit is 1. set the cbnsce bit to 1. (b) in single reception mode clear the cbnsce bit to 0 before reading the la st receive data because reception is started by reading the receive data (cbnrx register) note 2 to disable the reception startup. (c) in continuous reception mode clear the cbnsce bit to 0 one communication cl ock before reception of the last data is completed to disable the reception startup after the last data is received note 3 . in slave mode this bit enables or disables the communication start trigger. set the cbnsce bit to 1. [usage of cbnsce bit] in single reception mode <1> when reception of the last data is completed by intcbnr interrupt servicing, clear the cbnsce bit to 0 before reading the cbnrx register. <2> after confirming the cbnstr.cbntsf bit = 0, clear the cbnrxe bit to 0 to disable reception. to continue reception, set the cbnsce bit to 1 to start up the next reception by dummy- reading the cbnrx register. in continuous reception mode <1> clear the cbnsce bit to 0 during the reception of the last data by intcbnr interrupt servicing. <2> read the cbnrx register. <3> read the last reception data by reading the cbnrx register after acknowledging the cbntir interrupt. <4> after confirming the cbnstr.cbntsf bit = 0, clear the cbnrxe bit to 0 to disable reception. to continue reception, set the cbnsce bit to 1 to wait for the next reception by dummy- reading the cbnrx register. notes 1. these bits can only be re written when the cbnpwr bit = 0. however, the cbnpwr can be set to 1 at the same time as these bits are rewritten. 2. if the cbnsce bit is read while it is 1, the next communication operation is started. 3. the cbnsce bit is not cleared to 0 one communi cation clock before the co mpletion of the last data reception, the next communicati on operation is automatically started. caution 1: to forcibly suspend transmission/recep tion, clear the cbnpwr bit instead of the cbnrxe bit and the cbntxe bit to 0. at this time, the clock output is stopped. 2: be sure to clear bits 3 and 2 to 0. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 535 (2) csibn control register 1 (cbnctl1) this is an 8-bit register that selects the trans mission/reception timing and input clock of csibn. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution the cbnctl1 register can be rewritten only when the cbnc tl0.cbnpwr bit = 0 or when the cbntxe and cbnrxe bits are 0. after reset: 00h r/w address: cb0ctl1: fffffd01h, cb1ctl1: fffffd11h, cb2ctl1: fffffd21h 7 6 5 4 3 2 1 0 cbnctl1 0 0 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 (n = 0 to 2) cbnckp cbndap specification of transmission/reception timing of data of sckbn 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) cbncks2 cbncks1 cbncks0 input clock mode n = 0 n = 1 n = 2 0 0 0 f xx /2 master mode 0 0 1 f xx /4 master mode 0 1 0 f xx /8 master mode 0 1 1 f xx /16 master mode 1 0 0 f xx /32 master mode 1 0 1 f xx /64 master mode 1 1 0 f brg note tmp0(top01) f xx /128 master mode 1 1 1 external clock (sckbn) slave mode note f brg : output clock frequency of prescaler 3 for details of the prescaler, refer to 14.8 prescaler 3 . chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 536 (3) csibn control register 2 (cbnctl2) this is an 8-bit register that controls the number of serial transfer bits of csib. it can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution the cbnctl2 register can be rewritten when the cbnpwr bit of the cbn ctl0 register = 0 or when the cb0txe and cb0rxe bits = 0. after reset: 00h r/w address: cb0ctl2: fffffd02h, cb1ctl2: fffffd12h, cb2ctl2: fffffd22h 7 6 5 4 3 2 1 0 cbnctl2 0 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 (n = 0 to 2) cbncl3 cbncl2 cbncl1 cbncl0 bit length of serial register 0 0 0 0 8 bits 0 0 0 1 9 bits 0 0 1 0 10 bits 0 0 1 1 11 bits 0 1 0 0 12 bits 0 1 0 1 13 bits 0 1 1 0 14 bits 0 1 1 1 15 bits 1 x x x 16 bits caution if the number of transfer bits is not 8 or 16, prepare data, justifying it to the least significant bit of the cbntx or cbnrx register. remark. : don?t care chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 537 (4) csibn status register (cbnstr) this is an 8-bit register that indicates the status of csib. although this register can be read or written in 8- bit or 1-bit units, the cbntsf flag is read-only. reset input clears this register to 00h. clearing the cbnpwr bit of the cbnctl0 regist er to 0 also initializes this register. after reset: 00h r/w address: cb0str: fffffd03h, cb1str: fffffd13h, cb2str: fffffd23h 7 6 5 4 3 2 1 0 cbnstr cbntsf 0 0 0 0 0 0 cbnove (n = 0 to 2) cbntsf communication status flag 0 communication stopped 1 communicating this bit is set when data is prepared in the cbntx register for transmission. it is set when dummy data is read from the cbnrx register for reception. it is cleared when the edge of the last clock is completed. cbnove overrun error flag 0 no overrun 1 overrun ? an overrun error occurs when the next recept ion completes without reading the value of the receive buffer by cpu, upon completion of the receive operation. the cbnove flag indicates occurr ence of this overrun error. ? the cbnove bit is valid also in the single transfer mode. therefore, when only using transmission, note the following. do not check the cbnove flag. read this bit even if reading the reception data is not required. ? the obnove flag is cleared when 0 is written to it. it is not set when 1 is written to it. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 538 14.4 transfer data length change function the transfer data length of csib can be changed from 8 to 16 bits in 1-bit units by using the cbncl3 to cbncl0 bits of the cbnctl2 register. if a transfer data length of other than 16 bits is specified, set data in the cbntx or cbnrx register, justifying to the least significant bit, regardless of whether the first transfer bit is the msb or lsb. any data can be set to the higher bits that are not used, but the rece ive data is 0 after serial transfer. figure 14-2. changing transfer data length (a) when transfer bit length = 10 bits, msb first 15 10 9 0 sobn sibn insert 0 (b) when transfer bit length = 12 bits, lsb first 0 sobn 11 12 15 sibn insert 0 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 539 14.5 interrupt request signals csibn can generate the following two types of interrupt request signals. ? reception complete interrupt request signal (intcbnr) ? transmission enable interrupt request signal (intcbnt) of these two interrupt request signals, the reception comple te interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. table 14-4. interrupts and their default priority interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intcbnr) when receive data is transferred to the cbnrx register while reception is enabled, the reception complete interrupt request signal is generated. this interrupt request signal can also be generated if a reception error occurs, instead of a reception error interrupt. when the reception complete interrupt request signal is acknowledged and the data is read, read the cbnstr register to check that the result of reception is not an error. the reception complete interrupt request signal is not generated while reception is disabled. (2) transmission enable interr upt request signal (intcbnt) the transmission enable interrupt request signal is generated when transmit data is transferred from the cbntx register while transmission enabled. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 540 14.6 operation 14.6.1 single transfer mode (master mode, transmission/reception mode) this section shows a case of msb first (cbn ctl0.cbndir bit = 0), communication type 1 (see 14.3 (2) csibn control register 1 (cbnctl1) , and transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). cbntx write (55h) cbnrx read (aah) (aah) (55h) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (transmit data) sckbn pin cbntx register aah 00h cbnrx register shift register intcbnr signal note sibn pin sobn pin 0 0 0 1 0 0 1 0 1 1 cbntsf bit cbnsce bit (1) (5) (6) (8) (7) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of t he cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bi t, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the reception complete interrupt request signal (intcbnr) is output. (7) read the cbnrx register before clearing the cbnpwr bit to 0. (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop operation of csibn (end of transmission/reception). note in single transmission or single transmission/reception mode, the intcbnt signal is not generated. when communication is complete, the intcbnr signal is generated. remark the processing of steps (3) and (4) can be set simultaneously. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 541 14.6.2 single transfer mode (master mode, reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 1 (see 14.3 (2) csibn control register 1 (cbnctl1) , transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (aah) 1 0 1 1 00 1 01h 02h 05h 0ah 15h 2ah 55h aah 00h sckbn pin cbnrx register cbnrx read (dummy read) shift register cbnsce bit cbntsf bit intcbnr signal sibn pin sobn pin 0 l (1) (2) (3) (4) (5) (6) (7) (9) (8) cbnrx read (aah) aah 00h (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) set the cbnsce bit to 0 to set the final receive data status. (8) read the cbnrx register. (9) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the csibn operation (end of reception). remark the processing of steps (3) and (4) can be set simultaneously. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 542 14.6.3 continuous mode (master m ode, transmission/reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 3 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (7) (7) (6) (5) (1) (2) (3) (4) 96h 00h cch 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 55h cbntx register sckbn pin sobn pin sibn pin intcbnt signal intcbnr signal cbntsf bit cbnsce bit shift register so latch cbnrx register 0 0 0 0 aah 96h cch 1 1 1 0 0 0 1 01 0 0 (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of t he cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bi t, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the transmission enable interrupt request signal (int cbnt) is received and transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (8) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). in transmission mode or transmission/reception mode , the communication is not started by reading the cbnrx register. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 543 14.6.4 continuous mode (mast er mode, reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 2 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (6) (6) (7) (5) (1) (2) (3) (4) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn pin cbnsce bit sibn pin intcnr signal cbntsf bit shift register cbnrx register 1 1 0 55h aah aah 00h (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive da ta arrives or before the cbnpwr bit is cleared to 0. (7) set the cbnctl0.cbnsce bit = 0 while the last dat a being received to set the final receive data status. (8) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 544 14.6.5 continuous reception mode (error) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 2 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (9) (10) (7) (6) (5) aah 00h 1 0 0 0 0 0 01 1 1 1 1 sckbn pin sibn pin intcbnr signal cbntsf bit shift register cbnrx register cbnove bit 55h 55h 0 1 0 aah 1 (1) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) if the data could not be read befor e the end of the next transfer, the cbnstr.cbnove flag is set to 1 upon the end of reception and the intcbnr signal is output. (8) overrun error processing is performed after checki ng that the cbnove bit = 1 in the intcbnr interrupt servicing. (9) clear cbnove bit to 0. (10) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation csibn (end of reception). chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 545 14.6.6 continuous mode (slave m ode, transmission/reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 2 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.csncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (8) (7) (7) (6) (5) 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx register sckbn pin sobn pin sibn pin intcbnt signal intcbnr signal shift register so latch cbnrx register 0 0 0 0 0 0 aah 96h cch 1 0 0 0 1 1 cbntsf bit cbnsce bit (1) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable supply of the csibn operation. (5) write the transfer data to the cbntx register. (6) the transmission enable interrupt request signal (int cbnt) is received and the transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. (8) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat st eps (5) to (7) before (8). chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 546 14.6.7 continuous mode (s lave mode, reception mode) this section shows the case using msb first (cbn ctl0.cbndir bit = 0) and communication type 1 (see 14.3 (2) csibn control register 1 (cbnctl1) ), transfer data length = 8 bits (cbnct l2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0). (7) (6) (6) (5) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn pin sibn pin intcbnr signal cbntsf bit cbnsce bit shift register cbnrx register 1 1 55h aah 00h aah 0 (1) (2) (3) (4) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. when reading the last data, clear the cbnctl0.cbnsce bit to 0 before reading the cbnrx register. (7) check that the cbnstr.cbntsf bit = 0 and set t he cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 547 14.6.8 clock timing (1/2) (1) communication type 1 (cbnckp = 0, cbndap = 0) d6 d5 d4 d3 d2 d1 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit d0 d7 (2) communication type 2 (cbnckp = 0, cbndap = 1) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon completion of communication. 2. the intcbnr interrupt occurs if reception is co rrectly completed and receive data is ready in the cbnrx register while reception is enabled, and if an overrun error occurs. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon completion of communication. caution in communication type 2, the cbntsf bit is cleared half a sckbn clock after generation of the intcbnr interrupt request signal. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 548 (2/2) (3) communication type 3 (cbnckp = 1, cbndap = 0) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit (4) communication type 4 (cbnckp = 1, cbndap = 1) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. in the single transmission or single transmission/receptio n modes, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon completion of communication. 2. the intcbnr interrupt occurs if reception is co rrectly completed and receive data is ready in the cbnrx register while reception is enabled, and if an overrun error occurs. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon completion of communication. caution in communication type 4, the cbntsf bit is cleared half a sckbn clock after generation of the intcbnr interrupt request signal. chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 549 14.7 output pins (1) sckbn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. cbncks2 cbncks1 cbncks0 cbnckp sckbn pin output 1 1 1 high impedance 0 fixed to high level other than above 1 fixed to low level remarks 1. the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. 2. n = 0 to 2 3. : don?t care (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. cbntxe cbndap cbndir sobn pin output 0 fixed to low level 0 sobn latch value (low level) 0 cbntx register value (msb) 1 1 1 cbntx register value (lsb) remarks 1. the sobn pin output chan ges when any one of the cbnctl0.cbntxe, cbnctl0.cbndir bits, and cbnctl1.cbndap bit is rewritten. 2. n = 0 to 2 3. : don?t care chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 550 14.8 operation flow (1) single transmission start no yes intcbnr signal is generated? transfer data exists? end yes no initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register (start transfer). cbnpwr bit = 0 (cbnctl0) note set the cbnsce bit to 1 in the initial setting. caution in the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the cbntx register is written. remark n = 0 to 2 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 551 (2) single reception start no intcbnr signal is generated? last data? end yes yes no initial setting (cbnctl0 note , cbnctl1 registers, etc.) cbnrx register dummy read (start reception) cbnsce bit = 0 (cbnctl0) cbnpwr bit = 0 (cbnctl0) cbnrx register read cbnrx register read note set the cbnsce bit to 1 in the initial setting. caution in the single mode, data cannot be correctly received if the next transfer clock is input earlier than the cbnrx register is read. remark n = 0 to 2 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 552 (3) single transmission/reception start initial setting (cbnctl0 note 1 , cbnctl1 registers, etc.) write cbntx register (start transfer). end cbnpwr bit = 0, cbntxe bit = cbnrxe bit = 0 (cbnctl0) no transmission/reception transmission reception intcbnr signal is generated? yes transfer end? write cbntx register note 2 . read cbnrx register. read cbnrx register. no yes transfer end? write cbntx register note 2 . no yes transfer end? write cbntx register note 2 . no yes b b a a notes 1. set the cbnsce bit to 1 in the initial setting. 2. if the next transfer is reception only, dum my data is written to the cbntx register. caution even in the single mode, the cbnstr.cbnove flag is set to 1. if only transmission is used in the transmission/r eception mode, therefore, chec king the cbnove flag is not required. remark n = 0 to 2 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 553 (4) continuous transmission start no yes intcbnt signal is generated? data to be transferred next exists? end yes no initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register (start transfer). cbnpwr bit = 0 (cbnctl0) no cbntsf bit = 1? (cbnstr) yes note set the cbnsce bit to 1 in the initial setting. remark n = 0 to 2 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 554 (5) continuous reception start end no no yes intcbnr signal is generated? cbnove bit = 1? (cbnstr) no yes initial setting (cbnctl0 note , cbnctl1 registers, etc.) cbnrx register dummy read (start reception) cbnrx register read cbnrx register read cbnrx register read cbnrx register read yes is data being received last data? cbnsce bit = 0 (cbnctl0) cbnsce bit = 1 (cbnctl0) no intcbnr signal is generated ? yes cbnove bit clear (cbnstr) note set the cbnsce bit to 1 in the initial setting caution in the master mode, the clock is output wit hout limit when dummy da ta is read from the cbnrx register. to stop the cl ock, execute the flow marked in the above flowchart. in the slave mode, malfunction due to no ise during communication can be prevented by executing the flow marked in the above flowchart. before resuming communication, set the cbn ctl0.cbnsce bit to 1, and read dummy data from the cbnrx register. remark n = 0 to 2 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 555 (6) continuous transmission/reception start end no no intcbnt signal is generated? yes no intcbnt signal is generated ? yes initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register. cbnrx register read yes yes is data completely received last data? no write cbntx register. yes is data being transferred last data? no cbnove bit = 0? (cbnstr) cbnove bit clear (cbnstr) note set the cbnsce bit to 1 in the initial setting. remark n = 0 to 2 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 556 14.9 prescaler 3 prescaler 3 has the following function. ? generation of count clock for watch timer and csib0 (source clock: main oscillation clock) 14.9.1 control registers of prescaler 3 (1) prescaler mode register 0 (prsm0) the prsm0 register is used to control generation of the count clock for the watch timer and csib0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. do not change the values of the bgcs01 and bgcs00 bits while the watch timer is operating. 2. set the prsm0 register befo re setting the bgce0 bit to 1. after reset: 00h r/w address: fffff8b0h 7 6 5 4 3 2 1 0 prsm0 0 0 0 bgce0 0 0 bgcs01 bgcs00 bgce0 prescaler output 0 disabled 1 enabled bgcs01 bgcs00 selection of count clock (f brg ) f x = 4 mhz f x = 5 mhz 0 0 f x 250 ns 200 ns 0 1 f x /2 500 ns 400 ns 1 0 f x /4 1 s 800 ns 1 1 f x /8 2 s 1.6 s chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 557 (2) prescaler compare register 0 (prscm0) this is an 8-bit compare register. it can be read or written in 8-bit units. reset input clears this register to 00h. cautions 1. do not rewrite the prscm0 re gister while the watch timer is operating. 2. set the prscm0 register before setting the bgce0 bit of the pr sm0 register to 1. after reset: 00h r/w address: fffff8b1h 7 6 5 4 3 2 1 0 prscm0 prscm07 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 14.9.2 generation of count clock the clock input to the watch timer or csib0 (f brg ) can be corrected to 32.768 khz. the relationship between the main clock (f x ), set value of count clock selecti on bits bgcsn (m), set value of the prscm0 register (n), and output clock (f bgr ) is as follows. f brg = f x 2 m n 2 example : where f x = 4.00 mhz, m = 0 (bgcs01 bit = bgcs00 bit = 0), and n = 3dh f bgr = 32.787 khz remark f brg : count clock n: set value of prscm0 register (01h to ffh) n = 256 if the set value of the prscm0 register is 00h. m: set value of bgcsn bits (00b to 11b) n = 00, 01 chapter 14 3-wire serial interface (csib) user?s manual u17830ee1v0um00 558 14.10 cautions (1) when transferring transmit data and receive data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cbnstr.cbnove bit after dma transfer has been completed. (2) in regards to registers that are forbidden from bei ng rewritten during operations (cbnctl0.cbnpwr bit is 1), if rewriting has been carried out by mistake during oper ations, set the cbnctl0.cbnpwr bit to 0 once, then initialize csibn. registers to which rewriting during op eration are prohibited are shown below. ? cbnctl0 register: cbntxe, cbnrxe, cbndir, cbntms bits ? cbnctl1 register: cbnckp, cbndap, cbncks2 to cbncks0 bits ? cbnctl2 register: cbncl3 to cbncl0 bits (3) in communication type 2 or 4 (cbnctl1.cbndap bit = 1), the cbnstr.cbntsf bit is cleared half a sckbn clock after occurrence of a reception complete interrupt (intcbnr). in the single transfer mode, writing the next transmit data is ignored during communication (cbntsf bit = 1), and the next communication is not st arted. also if reception-only co mmunication (cbnctl0.cbntxe bit = 0, cbnctl0.cbnrxe bit = 1) is set, the next communication is not started even if the receive data is read during communication (cbntsf bit = 1). therefore, when using the single transfer mode with communication type 2 or 4 (cbndap bit = 1), pay particular attention to the following. ? to start the next transmission, confirm that cbntsf bit = 0 and then write the transmit data to the cbntx register. ? to perform the next reception continuously when re ception-only communication (cbntxe bit = 0, cbnrxe bit = 1) is set, confirm that cbntsf bit = 0 and then read the cbnrx register. or, use the continuous transfer mode inst ead of the single transfer mode. us e of the continuous transfer mode is recommended especially for using dma. remark n = 0 to 2 user?s manual u17830ee1v0um00 559 chapter 15 can controller remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. 15.1 overview this product features an on-chip n-channel can (controlle r area network) controller that complies with the can protocol as standardized in iso 11898. the number of ch annels varies depending on the product as shown below. product name (part number) number of channels v850es/fe2 1 v850es/ff2 1 v850es/fg2 2 pd70f3237 2 v850es/fj2 pd70f3238 pd70f3239 4 15.1.1 features ? compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test) ? standard frame and extended fram e transmission/reception enabled ? transfer rate: 1 mbps max. (can clock input 8 mhz) ? 32 message buffers per each channel ? receive/transmit history list function ? automatic block transmission function ? multi-buffer receive block function ? mask setting of four patterns is possible for each channel chapter 15 can controller user?s manual u17830ee1v0um00 560 15.1.2 overview of functions table 15-1 presents an overview of the can controller functions. table 15-1. overview of functions function details protocol can protocol iso 11898 (standard and extended frame transmission/reception) baud rate maximum 1 mbps (can clock input 8 mhz) data storage storing messages in the can ram number of messages ? 32 message buffers per each channel note ? each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception ? unique id can be set to each message buffer. ? mask setting of four patterns is possible for each channel. ? a receive completion interrupt is generated each time a message is received and stored in a message buffer. ? two or more receive message buffers can be used as a fifo receive buffer (multi-buffer receive block function). ? receive history list function message transmission ? unique id can be set to each message buffer. ? transmit completion interrupt for each message buffer ? message buffer numbers 0 to 7 specified as transmit message buffers can be used for automatic block transfer. message transmis sion interval is programmable (automatic block transmission function (herea fter referred to as ?abt?)). ? transmission history list function remote frame processing remote frame processing by transmit message buffer time stamp function ? the time stamp function can be set for a re ceive message when a 16-bit timer is used in combination. sof or eof in a can message frame can be det ected by using a trigger that selects a time stamp capture. diagnostic function ? readable error counters ? ?valid protocol operation flag? for verification of bus connections ? receive-only mode ? single-shot mode ? can protocol error type decoding ? self-test mode forced release from bus-off state ? default mode can be set while bus is off, so that bus can be forcibly released from bus-off state. power save mode ? can sleep mode (can be woken up by can bus) ? can stop mode (cannot be woken up by can bus) note 4 channels max. chapter 15 can controller user?s manual u17830ee1v0um00 561 15.1.3 configuration the can controller is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec periph eral i/o bus) interface and means of transmitting and receiving signals between the can module and the host cpu. (2) mac (memory access controller) this functional block controls access to the can prot ocol layer and to the can ram within the can module. (3) can protocol layer this functional block is involved in the oper ation of the can protocol and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 15-1. block diagram of can module cantxn canrxn cpu can module can ram npb (nec peripheral i/o bus) mac (memory access controller) npb interface interrupt request intcntrx intcnrec intcnerr intcnwup can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 cnmask1 cnmask2 cnmask3 cnmask4 ... can_hn can_ln can bus chapter 15 can controller user?s manual u17830ee1v0um00 562 15.2 can protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers : a physical layer and a data link layer. in turn, the data link layer includes logical link and medium access control. the composition of these layers is illustrated below. figure 15-2. composition of layers physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/no stuffing) medium access management error detection error report acknowledgement seriated/not seriated higher lower note can controller specification 15.2.1 frame format (1) standard format frame ? the standard format frame uses 11-bit identifiers, wh ich means that it can handle up to 2,048 messages. (2) extended format frame ? the extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of messages that can be handled to 2,048 218 messages. ? an extended format frame is set when ?recessive level? (cmos level of ?1?) is set for both the srr and ide bits in the arbitration field. chapter 15 can controller user?s manual u17830ee1v0um00 563 15.2.2 frame types the following four types of frames are used in the can protocol. table 15-2. frame types frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame (1) bus value the bus values are divided into dominant and recessive. ? dominant level is indicated by logical 0. ? recessive level is indicated by logical 1. ? when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 15.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 15-3. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8> remark d: dominant = 0 r: recessive = 1 chapter 15 can controller user?s manual u17830ee1v0um00 564 (2) remote frame a remote frame is composed of six fields. figure 15-4. remote frame r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> remarks 1. the data field is not transferred even if the cont rol field?s data length code is not ?0000b?. 2. d: dominant = 0 r: recessive = 1 (3) description of fields <1> start of frame (sof) the start of frame field is located at t he start of a data frame or remote frame. figure 15-5. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) remark d: dominant = 0 r: recessive = 1 ? if dominant level is detected in t he bus idle state, a hard-synchroni zation is performed (the current tq is assigned to be the sync segment). ? if dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a sof. if recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbanc e only. no error frame is generated in such case. chapter 15 can controller user?s manual u17830ee1v0um00 565 <2> arbitration field the arbitration field is used to set the priori ty, data frame/remote frame, and frame format. figure 15-6. arbitration field (in standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) cautions 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark d: dominant = 0 r: recessive = 1 figure 15-7. arbitration field (in extended format mode) r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit) cautions 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark d: dominant = 0 r: recessive = 1 table 15-3. rtr frame settings frame type rtr bit data frame 0 (d) remote frame 1 (r) table 15-4. frame format setting (ide bit) and number of identifier (id) bits frame format srr bit ide bit number of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits chapter 15 can controller user?s manual u17830ee1v0um00 566 <3> control field the control field sets ?n? as the number of da ta bytes in the data field (n = 0 to 8). figure 15-8. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) remark d: dominant = 0 r: recessive = 1 in a standard format frame, the control fiel d?s ide bit is the same as the r1 bit. table 15-5. data length setting data length code dlc3 dlc2 dlc1 dlc0 data byte count 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 caution in the remote frame, there is no data field even if the data length code is not 0000b. chapter 15 can controller user?s manual u17830ee1v0um00 567 <4> data field the data field contains the amount of data (byte units) se t by the control field. up to 8 units of data can be set. figure 15-9. data field r d data 0 (8 bits) msb lsb data 7 (8 bits) msb lsb data field (crc field) (control field) remark d: dominant = 0 r: recessive = 1 <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 15-10. crc field r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field) remark d: dominant = 0 r: recessive = 1 ? the polynomial p(x) used to generate the 15-bi t crc sequence is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? transmitting node: transmits the crc sequence calculat ed from the data (before bit stuffing) in the start of frame, arbitration fiel d, control field, and data field. ? receiving node: compares the crc sequence ca lculated using data bits that exclude the stuffing bits in the receive data with the crc sequence in the crc field. if the two crc sequences do not match, the node issues an error frame. chapter 15 can controller user?s manual u17830ee1v0um00 568 <6> ack field the ack field is used to acknowledge normal reception. figure 15-11. ack field r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) remark d: dominant = 0 r: recessive = 1 ? if no crc error is detected, the receiving node sets the ack slot to the dominant level. ? the transmitting node outputs two recessive-level bits. <7> end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 15-12. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) remark d: dominant = 0 r: recessive = 1 chapter 15 can controller user?s manual u17830ee1v0um00 569 <8> interframe space the interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. ? the bus state differs dep ending on the error status. (a) error active node the interframe space consists of a 3-bit intermission field and a bus idle field. figure 15-13. interframe space (error active node) r d interframe space intermission (3 bits) bus idle (0 to bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 (b) error passive node the interframe space consists of an intermission fi eld, a suspend transmission field, and a bus idle field. figure 15-14. interframe space (error passive node) r d interframe space intermission (3 bits) suspend transmission (8 bits) bus idle (0 to bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 re cessive-level bits transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1 usually, the intermission field is 3 bits. if the transmitting node detects a domin ant level at the third bit of the intermission field, ho wever, it executes transmission. chapter 15 can controller user?s manual u17830ee1v0um00 570 ? operation in error status table 15-6. operation in error status error status operation error active a node in this status can transmit immediately after a 3-bit intermission. error passive a node in this status can transmit 8 bits after the intermission. chapter 15 can controller user?s manual u17830ee1v0um00 571 15.2.4 error frame an error frame is output by a node that has detected an error. figure 15-15. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag 2 error flag 1 error bit error frame remark d: dominant = 0 r: recessive = 1 table 15-7. definition of error frame fields no. name bit count definition <1> error flag 1 6 error active node: outputs 6 domi nant-level bits consecutively. error passive node: outputs 6 rece ssive-level bits consecutively. if another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> error flag 2 0 to 6 nodes receiving error flag 1 detect bit stuff errors and issue this error flag. <3> error delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> error bit ? the bit at which the error was detected. the error flag is output from the bit next to the error bit. in the case of a crc error, this bit is output following the ack delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. chapter 15 can controller user?s manual u17830ee1v0um00 572 15.2.5 overload frame an overload frame is transmitted under the following conditions. ? when the receiving node has not co mpleted the reception operation note ? if a dominant level is detected at the first two bits during intermission ? if a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter note the can is internally fast enough to process a ll received frames not generating overload frames. figure 15-16. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) frame overload frame remark d: dominant = 0 r: recessive = 1 node n node m table 15-8. definition of overload frame fields no name bit count definition <1> overload flag 6 outputs 6 domin ant-level bits consecutively. <2> overload flag from other node 0 to 6 the node that received an overload flag in the interframe space outputs an overload flag. <3> overload delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. chapter 15 can controller user?s manual u17830ee1v0um00 573 15.3 functions 15.3.1 determining bus priority (1) when a node starts transmission: ? during bus idle, the node that out put data first transmits the data. (2) when more than one n ode starts transmission: ? the node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recess ive level are simultaneously transmitted, the dominant level is taken as the bus value). ? the transmitting node compares its output arbi tration field and the data level on the bus. table 15-9. determining bus priority level match continuous transmission level mismatch continuous transmission (3) priority of data frame and remote frame ? when a data frame and a remote frame are on the bus, t he data frame has priority because its rtr bit, the last bit in the arbitration field, carries a dominant level. caution if the extended-format data frame and the st andard-format remote frame conflict on the bus (if id28 to id18 of both of them are the same), th e standard-format remote frame takes priority. 15.3.2 bit stuffing bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues for 5 bits, in order to prevent a burst error. table 15-10. bit stuffing transmission during the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 inverted-level bit of data is inserted before the following bit. reception during the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, re ception is continued after deleting the next bit. 15.3.3 multi masters as the bus priority (a node acquiring transmit functions) is determined by the identif ier, any node can be the bus master. 15.3.4 multi cast although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. chapter 15 can controller user?s manual u17830ee1v0um00 574 15.3.5 can sleep mode/can stop mode function the can sleep mode/can stop mode func tion puts the can controller in waiting mode to achieve low power consumption. the controller is woken up from the can sleep mode by bus operation but it is not woken up from the can stop mode by bus operation (the can stop mode is controlled by cpu access). 15.3.6 error control function (1) error types table 15-11. error types description of error detection state type detection method detection condition transmission/ reception field/frame bit error comparison of the output level and level on the bus (except stuff bit) mismatch of levels transmitting/ receiving node bit that is outputting data on the bus at the start of frame to end of frame, error frame and overload frame. stuff error check of the receive data at the stuff bit 6 consecutive bits of the same output level receiving node start of frame to crc sequence crc error comparison of the crc sequence generated from the receive data and the received crc sequence mismatch of crc receiving node crc field form error field/frame check of the fixed format detection of fixed format violation receiving node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmitting node detection of recessive level in ack slot transmitting node ack slot (2) output timing of error frame table 15-12. output timing of error frame type output timing bit error, stuff error, form error, ack error error frame output is started at the timing of the bit following the detected error. cec error error frame output is started at the timing of the bit following the ack delimiter. (3) processing in case of error the transmission node re-transmits the data frame or remo te frame after the error frame. (however, it does not re-transmit the frame in the single-shot mode.) chapter 15 can controller user?s manual u17830ee1v0um00 575 (4) error state (a) types of error states the following three types of error states are defined by the can specification. ? error active ? error passive ? bus-off these types of error states are cl assified by the values of the tec7 to tec0 bits (transmission error counter bits) and the rec6 to rec0 bits (reception er ror counter bits) of the can error counter register as shown in table 15-13. the present error state is indicated by t he can module information register (cninfo). when each error counter value becomes equal to or greater than the error warning level (96), the tecs0 or recs0 bit of the cninfo register is set to 1. in this case, the bus state must be tested because it is considered that the bus has a serious fault. an error counter value of 128 or more indicates an error passive state and the tecs1 or recs1 bit of the cninfo register is set to 1. ? if the value of the transmission error counter is gr eater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the boff bit of the cninfo register is set to 1. ? if only one node is active on the bus at startup (i.e., when the bus is connected only to the local station), ack is not returned even if data is transmitted. consequently, re-t ransmission of the error frame and data is repeated. in the error passive state, howev er, the transmission error c ounter is not incremented and the bus-off state is not reached. remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller user?s manual u17830ee1v0um00 576 table 15-13. types of error states type operation value of error counter indication of cninfo register operation specific to error state transmission 0 to 95 tecs1, tecs0 = 00 reception 0 to 95 recs1, recs0 = 00 transmission 96 to 127 tecs1, tecs0 = 01 error active reception 96 to 127 recs1, recs0 = 01 ? outputs an active error flag (6 consecutive dominant- level bits) on detection of the error. transmission 128 to 255 tecs1, tecs0 = 11 error passive reception 128 or more recs1, recs0 = 11 ? outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. ? transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). bus-off transmission 256 or more (not indicated) note boff = 1, tecs1, tecs0 = 11 ? communication is not possible. <1> tsout toggles. <2> rec is incremented / decremented. <3> valid bit is set. ? if the initialization mode is set and then 11 recessive- level bits are generated 128 times in a row in an operation mode other than the initialization mode, the error counter is reset to 0 and the error active state can be restored. note value of the transmission error counter (tec) is not m eaning when boff bit is set. if an error that increments the value of the transmission error counter by 8 while t he counter value is in a rang e of 248 to 255, the counter is not incremented and the bus-off state is assumed. remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller user?s manual u17830ee1v0um00 577 (b) error counter the error counter counts up when an error has occu rred, and counts down upon successful transmission and reception. the error counter is updated during the first bit of the error delimiter. table 15-14. error counter state transmission error counter (tec7 to tec0) reception error counter (rec6 to rec0) receiving node detects an error (except bit error in the active error flag or overload flag). no change +1 (reps bit = 0) receiving node detects dominant level following error flag of error frame. no change +8 (reps bit = 0) transmitting node transmits an error flag. [as exceptions, the error counter does not change in the following cases.] <1> ack error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> a stuff error is detected in an arbitration field that transmitted a recessive level as stuff bit, but a dominant level is detected. +8 no change bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 no change bit error detection while active error flag or overload flag is being output (error-active receiving node) no change +8 (reps bit = 0) when the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. when the node detects 8 consecutive dominant levels after a passive error flag +8 (transmitting) +8 (receiving, reps bit = 0) when the transmitting node has co mpleted transmission without error ( 0 if error counter = 0) ?1 no change when the receiving node has completed reception without error no change ? ?1 (1 rec6 to rec0 127, reps bit = 0) ? 0 (rec6 to rec0 = 0, reps bit = 0) ? any value of 119 to 127 is set (reps bit = 1) (c) occurrence of bit error in intermission an overload frame is generated. caution if an error occurs, it is controlled according to the cont ents of the transmission error counter and reception error counter before th e error occurred. the value of the error counter is incremented after th e error flag has been output. chapter 15 can controller user?s manual u17830ee1v0um00 578 (5) recovery from bus-off state when the can module is in the bus-off state, the transmission pins (ctxdn) cut off from the can bus always output the recessive level. the can module recovers from the bus-off stat e in the following bus-off recovery sequence. <1> request to enter the can initialization mode <2> request to enter a can operation mode (a) recovery operation through normal recovery sequence (b) forced recovery operation that skips recovery sequence (a) recovery from bus-off state through normal recovery sequence the can module first issues a request to enter the init ialization mode (refer to timing <1> in figure 15-17). this request will be immediately acknowledged, and th e opmode bits of the cnctrl register are cleared to 000b. processing such as analyzing the fa ult that has caused the bus -off state, re-defining the can module and message buffer using application softw are, or stopping the oper ation of the can module can be performed by clearing the gom bit to 0. next, the module requests to change the mode from t he initialization mode to an operation mode (refer to timing <2> in figure 15-17). this starts an operation to recover the can module from the bus-off state. the conditions under which the module can recove r from the bus-off state are defined by the can protocol iso 11898, and it is necessary to detect 11 c onsecutive recessive-level bits 128 times or more. at this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. when the recovery conditions are satisfied (refer to timing <3> in figure 15-17), the can module can enter the oper ation mode it has requested. until the can module enters this operation mode, it stays in the initialization m ode. whether the can modul e has entered the operation mode can be confirmed by reading the op mode bits of the cnctrl register. during the bus-off period and bus-off recovery sequence, the boff bit of the cninfo register stays set (to 1). in the bus-off recovery sequence, the rece ption error counter (rec[6:0]) counts the number of times 11 consecutive recessive-level bits have been det ected on the bus. theref ore, the recovery state can be checked by reading rec[6:0]. caution in the bus-off recovery sequence, rec[6:0] counts up (+1) each time 11 consecutive recessive-level bits have b een detected. even during the bus-off period, the can module can enter the can sleep mode or can st op mode. to be released from the bus- off state, the module must ente r the initialization mode once. if the module is in the can sleep mode or can stop mode, however, it cannot enter the initializati on mode. in this case, release the module from the can sleep or stop mode, and then make a request to place the module in the initialization mode. remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller user?s manual u17830ee1v0um00 579 figure 15-17. recovery from bus-o ff state through normal recovery sequence ?error-passive? 00h 00h 00h 00h 80h tec[7:0] ffh boff bit in cninfo register opmode[2:0] in cnctrl register (written by user) opmode[2:0] in cnctrl register (read by user) tec[7:0] in cnerc register rec[7:0] in cnerc register tec > ffh 00h 00h 00h ffh < tec [7:0] ?bus-off? ?bus-off-recovery-sequence? ?error-active? 00h tec[7:0] < 80h 00h rec[7:0] < 80h 00h rec[7:0] 80h <1> <2> <3> undefined remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) (b) forced recovery operation that skips bus-off recovery sequence the can module can be forcibly released from the bus -off state, regardless of the bus state, by skipping the bus-off recovery sequence. here is the procedure. first, the can module requests to enter the initiali zation mode. for the oper ation and points to be noted at this time, refer to 15.3.6 (5) (a) recovery from bus-off state through normal recovery sequence . next, the module requests to enter an operation mode. at the same time, the ccerc bit of the cnctrl register must be set to 1. as a result, the bus-off recovery sequence defined by the can protocol is o 11898 is skipped, and the module immediately enters the operation mode. in this case, the module is connected to the can bus after it has monitored 11 consecutive recessive-level bits. for details, refer to the processing in figure 15-53. caution this function is not defined by the can pr otocol iso 11898. when using this function, thoroughly evaluate its effe ct on the network system. remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller user?s manual u17830ee1v0um00 580 (6) initializing can module error counter re gister (cnerc) in initialization mode if it is necessary to initialize the can module erro r counter register (cnerc) and can module information register (cninfo) for debugging or evaluating a program, t hey can be initialized to the default value by setting the ccerc bit of the cnctrl register in the initializati on mode. when initialization has been completed, the ccerc bit is automatically cleared to 0. cautions 1. this function is enabled only in the init ialization mode. even if the ccerc bit is set to 1 in a can operation mode, the cnerc and cn info registers are not initialized. 2. the ccerc bit can be set at the same ti me as the request to enter a can operation mode. remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller user?s manual u17830ee1v0um00 581 15.3.7 baud rate control function (1) prescaler the can controller has a prescaler that divides the clock (f can ) supplied to can. this prescaler generates a can protocol layer base clock (f tq ) that is the can module system clock (f canmod ) divided by 1 to 256 (refer to 15.6 (12) can module bit rate prescaler register (cnbrp) ). (2) data bit time (8 to 25 time quanta) one data bit time is defined as figure 14-8. the can controller sets time segment 1, time segment 2, and resynchronization jump width (sjw) as the data bit ti me, as shown in figure 15-18. time segment 1 is equivalent to the total of the prop agation (prop) segment and phase segment 1 that are defined by the can protocol specification. time segment 2 is equivalent to phase segment 2. figure 15-18. segment setting data bit time(dbt) phase segment 1 prop segment sync segment phase segment 2 time segment 1(tseg1) time segment 2 (tseg2) sample point (spt) segment name settable range notes on setting to conform to can specification time segment 1 (tseg1) 2tq to 16tq ? time segment 2 (tseg2) 1tq to 8tq ipt note of the can controller is 0tq. to conform to the can protocol specification, therefore, a length equal to phase segment 1 must be set here. this means that the length of time segment 1 minus 1tq is the settable upper limit of time segment 2. resynchronization jump width (sjw) 1tq to 4tq the length of time segment 1 minus 1tq or 4 tq, whichever is smaller. note ipt: information processing time chapter 15 can controller user?s manual u17830ee1v0um00 582 reference: the can protocol specification defines the segm ents constituting the data bit time as shown in figure 15-19. figure 15-19. reference: configuration of data bit time defined by can specification phase segment 1 prop segment sync segment phase segment 2 sample point (spt) sjw data bit time(dbt) segment name segment length description sync segment (synchronization segment) 1 this segment starts at the edge where the level changes from recessive to dominant when hardware synchronization is established. prop segment (propagation segment) programmable to 1 to 8 or more great phase segment 1 (phase buffer segment 1) programmable to 1 to 8 this segment absorbs the delay of the output buffer, can bus, and input buffer. the length of this segment is set so that ack is returned before the start of phase segment 1. time of prop segment (delay of output buffer) + 2 (delay of can bus) + (delay of input buffer) phase segment 2 (phase buffer segment 2) phase segment 1 or ipt note , whichever greater this segment compensates for an error in the data bit time. the longer this segment, the wider the permissible range but the slower the communication speed. sjw (resynchronization jump width) programmable from 1tq to length of segment 1 or 4tq, whichever is smaller this width sets the upper limit of expansion or contraction of the phase segment during resynchronization. note ipt: information processing time chapter 15 can controller user?s manual u17830ee1v0um00 583 (3) synchronizing data bit ? the receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. ? the transmitting node transmits data in synchroniza tion with the bit timing of the transmitting node. (a) hardware synchronization this synchronization is established when the receiving node detects the start of frame in the interframe space. ? when a falling edge is detected on the bus that tq means the sync segment and the next segment is the prop segment. in this case, synchroni zation is established regardless of sjw. figure 15-20. adjusting synchronization of data bit start of frame interframe space can bus bit timing phase segment 1 prop segment sync segment phase segment 2 chapter 15 can controller user?s manual u17830ee1v0um00 584 (b) resynchronization synchronization is established again if a level change is detected on t he bus during reception (only if a recessive level was sampled previously). ? the phase error of the edge is given by the relati ve position of the detected edge and sync segment. chapter 15 can controller user?s manual u17830ee1v0um00 585 15.4 connection with target system the can module has to be connected to the can bus using an external transceiver. figure 15-22. connection to can bus can module transceiver ctxdn crxdn canl canh remark n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 586 user?s manual u17830ee1v0um00 15.5 internal registers of can controller 15.5.1 can controller configuration table 15-15. list of can controller registers (1/2) item register name can global registers can global control register (cngmctrl) can global clock selection register (cngmcs) can global automatic block transm ission control register (cngmabt) can global automatic block transmissi on delay setting register (cngmabtd) can module registers can module mask 1 register (cnmask1l, cnmask1h) can module mask 2 register (cnmask2l, cnmask2h) can module mask3 register (cnmask3l, cnmask3h) can module mask 4 registers (cnmask4l, cnmask4h) can module control register (cnctrl) can module last error information register (cnlec) can module information register (cninfo) can module error counter register (cnerc) can module interrupt enable register (cnie) can module interrupt status register (cnints) can module bit rate prescaler register (cnbrp) can module bit rate register (cnbtr) can module last in-pointer register (cnlipt) can module receive histor y list register (cnrgpt) can module last out-pointer register (cnlopt) can module transmit histor y list register (cntgpt) can module time stamp register (cnts) remark 1. n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 2. can global registers are identified by cngm chapter 15 can controller 587 user?s manual u17830ee1v0um00 (2/2) item register name message buffer registers can message data byte 01 register m (cnmdata01m) can message data byte 0 register m (cnmdata0m) can message data byte 1 register m (cnmdata1m) can message data byte 23 register m (cnmdata23m) can message data byte 2 register m (cnmdata2m) can message data byte 3 register m (cnmdata3m) can message data byte 45 register m (cnmdata45m) can message data byte 4 register m (cnmdata4m) can message data byte 5 register m (cnmdata5m) can message data byte 67 register m (cnmdata67m) can message data byte 6 register m (cnmdata6m) can message data byte 7 register m (cnmdata7m) can message data length register m (cnmdlcm) can message configuration register m (cnmconfm) can message id register m (cnmidlm, cnmidhm) can message control register m (cnmctrlm) remark 1. n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 2. can global registers are identified by cngm chapter 15 can controller 588 user?s manual u17830ee1v0um00 15.5.2 register access type the peripheral i/o register for the can controller is assigned to 03fec000h - 03fed800h. for details, refer to 3.4.8 programmable peripheral i/o register . table 15-16. register access type (1/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec000h can0 global control register c0gmctrl r/w ? ? 0000h 03fec002h can0 global clock sele ct register c0gmcs r/w ? ? 0fh 03fec006h can0 global block transmissi on control register c0gmabt r/w ? ? 0000h 03fec008h can0 global block transmission delay setting register c0gmabtd r/w ? ? 00h 03fec040h c0mask1l r/w ? ? undefined 03fec042h can0 module mask 1 register c0mask1h 03fec044h c0mask2l r/w ? ? undefined 03fec046h can0 module mask 2 register c0mask2h 03fec048h c0mask3l r/w ? ? undefined 03fec04ah can0 module mask 3 register c0mask3h 03fec04ch c0mask4l r/w ? ? undefined 03fec04eh can0 module mask 4 register c0mask4h 03fec050h can0 module control register c0ctrl r/w ? ? 0000h 03fec052h can0 module last error information register c0lec r/w ? ? 00h 03fec053h can0 module information register c0info r ? ? 00h 03fec054h can0 module error counter register c0erc r ? ? 0000h 03fec056h can0 module interrupt enable register c0ie r/w ? ? 0000h 03fec058h can0 module interrupt status register c0ints r/w ? ? 0000h 03fec05ah can0 module bit rate prescaler register c0brp r/w ? ? ffh 03fec05ch can0 module bit rate register c0btr r/w ? ? 370fh 03fec05eh can0 module last in-pointer register c0lipt r ? ? undefined 03fec060h can0 module receive hist ory list register c0rgpt r/w ? ? xx02h 03fec062h can0 module last out-pointer register c0lopt r ? ? undefined 03fec064h can0 module transmit history list register c0tgpt r/w ? ? xx02h 03fec066h can0 module time stamp register c0ts r/w ? ? 0000h chapter 15 can controller 589 user?s manual u17830ee1v0um00 (2/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec100h can0 message data byte 01 register 00 c0mdata0100 undefined 03fec100h can0 message data byte 0 register 00 c0mdata000 undefined 03fec101h can0 message data byte 1 register 00 c0mdata100 undefined 03fec102h can0 message data byte 23 register 00 c0mdata2300 undefined 03fec102h can0 message data byte 2 register 00 c0mdata200 undefined 03fec103h can0 message data byte 3 register 00 c0mdata300 undefined 03fec104h can0 message data byte 45 register 00 c0mdata4500 undefined 03fec104h can0 message data byte 4 register 00 c0mdata400 undefined 03fec105h can0 message data byte 5 register 00 c0mdata500 undefined 03fec106h can0 message data byte 67 register 00 c0mdata6700 undefined 03fec106h can0 message data byte 6 register 00 c0mdata600 undefined 03fec107h can0 message data byte 7 register 00 c0mdata700 undefined 03fec108h can0 message data length code register 00 c0mdlc00 0000xxxxb 03fec109h can0 message configurat ion register 00 c0mconf00 undefined 03fec10ah c0midl00 undefined 03fec10ch can0 message id register 00 c0midh00 undefined 03fec10eh can0 message control register 00 c0mctrl00 00x00000 000xx000b 03fec120h can0 message data byte 01 register 01 c0mdata0101 undefined 03fec120h can0 message data byte 0 register 01 c0mdata001 undefined 03fec121h can0 message data byte 1 register 01 c0mdata101 undefined 03fec122h can0 message data byte 23 register 01 c0mdata2301 undefined 03fec122h can0 message data byte 2 register 01 c0mdata201 undefined 03fec123h can0 message data byte 3 register 01 c0mdata301 undefined 03fec124h can0 message data byte 45 register 01 c0mdata4501 undefined 03fec124h can0 message data byte 4 register 01 c0mdata401 undefined 03fec125h can0 message data byte 5 register 01 c0mdata501 undefined 03fec126h can0 message data byte 67 register 01 c0mdata6701 undefined 03fec126h can0 message data byte 6 register 01 c0mdata601 undefined 03fec127h can0 message data byte 7 register 01 c0mdata701 undefined 03fec128h can0 message data length code register 01 c0mdlc01 0000xxxxb 03fec129h can0 message configurat ion register 01 c0mconf01 undefined 03fec12ah c0midl01 undefined 03fec12ch can0 message id register 01 c0midh01 undefined 03fec12eh can0 message control register 01 c0mctrl01 r/w 00x00000 000xx000b chapter 15 can controller 590 user?s manual u17830ee1v0um00 (3/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec140h can0 message data byte 01 register 02 c0mdata0102 undefined 03fec140h can0 message data byte 0 register 02 c0mdata002 undefined 03fec141h can0 message data byte 1 register 02 c0mdata102 undefined 03fec142h can0 message data byte 23 register 02 c0mdata2302 undefined 03fec142h can0 message data byte 2 register 02 c0mdata202 undefined 03fec143h can0 message data byte 3 register 02 c0mdata302 undefined 03fec144h can0 message data byte 45 register 02 c0mdata4502 undefined 03fec144h can0 message data byte 4 register 02 c0mdata402 undefined 03fec145h can0 message data byte 5 register 02 c0mdata502 undefined 03fec146h can0 message data byte 67 register 02 c0mdata6702 undefined 03fec146h can0 message data byte 6 register 02 c0mdata602 undefined 03fec147h can0 message data byte 7 register 02 c0mdata702 undefined 03fec148h can0 message data length code register 02 c0mdlc02 0000xxxxb 03fec149h can0 message configurat ion register 02 c0mconf02 undefined 03fec14ah c0midl02 undefined 03fec14ch can0 message id register 02 c0midh02 undefined 03fec14eh can0 message control register 02 c0mctrl02 00x00000 000xx000b 03fec160h can0 message data byte 01 register 03 c0mdata0103 undefined 03fec160h can0 message data byte 0 register 03 c0mdata003 undefined 03fec161h can0 message data byte 1 register 03 c0mdata103 undefined 03fec162h can0 message data byte 23 register 03 c0mdata2303 undefined 03fec162h can0 message data byte 2 register 03 c0mdata203 undefined 03fec163h can0 message data byte 3 register 03 c0mdata303 undefined 03fec164h can0 message data byte 45 register 03 c0mdata4503 undefined 03fec164h can0 message data byte 4 register 03 c0mdata403 undefined 03fec165h can0 message data byte 5 register 03 c0mdata503 undefined 03fec166h can0 message data byte 67 register 03 c0mdata6703 undefined 03fec166h can0 message data byte 6 register 03 c0mdata603 undefined 03fec167h can0 message data byte 7 register 03 c0mdata703 undefined 03fec168h can0 message data length code register 03 c0mdlc03 0000xxxxb 03fec169h can0 message configurat ion register 03 c0mconf03 undefined 03fec16ah c0midl03 undefined 03fec16ch can0 message id register 03 c0midh03 undefined 03fec16eh can0 message control register 03 c0mctrl03 r/w 00x00000 000xx000b chapter 15 can controller 591 user?s manual u17830ee1v0um00 (4/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec180h can0 message data byte 01 register 04 c0mdata0104 undefined 03fec180h can0 message data byte 0 register 04 c0mdata004 undefined 03fec181h can0 message data byte 1 register 04 c0mdata104 undefined 03fec182h can0 message data byte 23 register 04 c0mdata2304 undefined 03fec182h can0 message data byte 2 register 04 c0mdata204 undefined 03fec183h can0 message data byte 3 register 04 c0mdata304 undefined 03fec184h can0 message data byte 45 register 04 c0mdata4504 undefined 03fec184h can0 message data byte 4 register 04 c0mdata404 undefined 03fec185h can0 message data byte 5 register 04 c0mdata504 undefined 03fec186h can0 message data byte 67 register 04 c0mdata6704 undefined 03fec186h can0 message data byte 6 register 04 c0mdata604 undefined 03fec187h can0 message data byte 7 register 04 c0mdata704 undefined 03fec188h can0 message data length code register 04 c0mdlc04 0000xxxxb 03fec189h can0 message configurat ion register 04 c0mconf04 undefined 03fec18ah c0midl04 undefined 03fec18ch can0 message id register 04 c0midh04 undefined 03fec18eh can0 message control register 04 c0mctrl04 00x00000 000xx000b 03fec1a0h can0 message data byte 01 register 05 c0mdata0105 undefined 03fec1a0h can0 message data byte 0 register 05 c0mdata005 undefined 03fec1a1h can0 message data byte 1 register 05 c0mdata105 undefined 03fec1a2h can0 message data byte 23 register 05 c0mdata2305 undefined 03fec1a2h can0 message data byte 2 register 05 c0mdata205 undefined 03fec1a3h can0 message data byte 3 register 05 c0mdata305 undefined 03fec1a4h can0 message data byte 45 register 05 c0mdata4505 undefined 03fec1a4h can0 message data byte 4 register 05 c0mdata405 undefined 03fec1a5h can0 message data byte 5 register 05 c0mdata505 undefined 03fec1a6h can0 message data byte 67 register 05 c0mdata6705 undefined 03fec1a6h can0 message data byte 6 register 05 c0mdata605 undefined 03fec1a7h can0 message data byte 7 register 05 c0mdata705 undefined 03fec1a8h can0 message data length code register 05 c0mdlc05 0000xxxxb 03fec1a9h can0 message configur ation register 05 c0mconf05 undefined 03fec1aah c0midl05 undefined 03fec1ach can0 message id register 05 c0midh05 undefined 03fec1aeh can0 message control register 05 c0mctrl05 r/w 00x00000 000xx000b chapter 15 can controller 592 user?s manual u17830ee1v0um00 (5/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec1c0h can0 message data byte 01 register 06 c0mdata0106 undefined 03fec1c0h can0 message data byte 0 register 06 c0mdata006 undefined 03fec1c1h can0 message data byte 1 register 06 c0mdata106 undefined 03fec1c2h can0 message data byte 23 register 06 c0mdata2306 undefined 03fec1c2h can0 message data byte 2 register 06 c0mdata206 undefined 03fec1c3h can0 message data byte 3 register 06 c0mdata306 undefined 03fec1c4h can0 message data byte 45 register 06 c0mdata4506 undefined 03fec1c4h can0 message data byte 4 register 06 c0mdata406 undefined 03fec1c5h can0 message data byte 5 register 06 c0mdata506 undefined 03fec1c6h can0 message data byte 67 register 06 c0mdata6706 undefined 03fec1c6h can0 message data byte 6 register 06 c0mdata606 undefined 03fec1c7h can0 message data byte 7 register 06 c0mdata706 undefined 03fec1c8h can0 message data length code register 06 c0mdlc06 0000xxxxb 03fec1c9h can0 message configur ation register 06 c0mconf06 undefined 03fec1cah c0midl06 undefined 03fec1cch can0 message id register 06 c0midh06 undefined 03fec1ceh can0 message control register 06 c0mctrl06 00x00000 000xx000b 03fec1e0h can0 message data byte 01 register 07 c0mdata0107 undefined 03fec1e0h can0 message data byte 0 register 07 c0mdata007 undefined 03fec1e1h can0 message data byte 1 register 07 c0mdata107 undefined 03fec1e2h can0 message data byte 23 register 07 c0mdata2307 undefined 03fec1e2h can0 message data byte 2 register 07 c0mdata207 undefined 03fec1e3h can0 message data byte 3 register 07 c0mdata307 undefined 03fec1e4h can0 message data byte 45 register 07 c0mdata4507 undefined 03fec1e4h can0 message data byte 4 register 07 c0mdata407 undefined 03fec1e5h can0 message data byte 5 register 07 c0mdata507 undefined 03fec1e6h can0 message data byte 67 register 07 c0mdata6707 undefined 03fec1e6h can0 message data byte 6 register 07 c0mdata607 undefined 03fec1e7h can0 message data byte 7 register 07 c0mdata707 undefined 03fec1e8h can0 message data length code register 07 c0mdlc07 0000xxxxb 03fec1e9h can0 message configur ation register 07 c0mconf07 undefined 03fec1eah c0midl07 undefined 03fec1ech can0 message id register 07 c0midh07 undefined 03fec1eeh can0 message control register 07 c0mctrl07 r/w 00x00000 000xx000b chapter 15 can controller 593 user?s manual u17830ee1v0um00 (6/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec200h can0 message data byte 01 register 08 c0mdata0108 undefined 03fec200h can0 message data byte 0 register 08 c0mdata008 undefined 03fec201h can0 message data byte 1 register 08 c0mdata108 undefined 03fec202h can0 message data byte 23 register 08 c0mdata2308 undefined 03fec202h can0 message data byte 2 register 08 c0mdata208 undefined 03fec203h can0 message data byte 3 register 08 c0mdata308 undefined 03fec204h can0 message data byte 45 register 08 c0mdata4508 undefined 03fec204h can0 message data byte 4 register 08 c0mdata408 undefined 03fec205h can0 message data byte 5 register 08 c0mdata508 undefined 03fec206h can0 message data byte 67 register 08 c0mdata6708 undefined 03fec206h can0 message data byte 6 register 08 c0mdata608 undefined 03fec207h can0 message data byte 7 register 08 c0mdata708 undefined 03fec208h can0 message data length code register 08 c0mdlc08 0000xxxxb 03fec209h can0 message configurat ion register 08 c0mconf08 undefined 03fec20ah c0midl08 undefined 03fec20ch can0 message id register 08 c0midh08 undefined 03fec20eh can0 message control register 08 c0mctrl08 00x00000 000xx000b 03fec220h can0 message data byte 01 register 09 c0mdata0109 undefined 03fec220h can0 message data byte 0 register 09 c0mdata009 undefined 03fec221h can0 message data byte 1 register 09 c0mdata109 undefined 03fec222h can0 message data byte 23 register 09 c0mdata2309 undefined 03fec222h can0 message data byte 2 register 09 c0mdata209 undefined 03fec223h can0 message data byte 3 register 09 c0mdata309 undefined 03fec224h can0 message data byte 45 register 09 c0mdata4509 undefined 03fec224h can0 message data byte 4 register 09 c0mdata409 undefined 03fec225h can0 message data byte 5 register 09 c0mdata509 undefined 03fec226h can0 message data byte 67 register 09 c0mdata6709 undefined 03fec226h can0 message data byte 6 register 09 c0mdata609 undefined 03fec227h can0 message data byte 7 register 09 c0mdata709 undefined 03fec228h can0 message data length code register 09 c0mdlc09 0000xxxxb 03fec229h can0 message configurat ion register 09 c0mconf09 undefined 03fec22ah c0midl09 undefined 03fec22ch can0 message id register 09 c0midh09 undefined 03fec22eh can0 message control register 09 c0mctrl09 r/w 00x00000 000xx000b chapter 15 can controller 594 user?s manual u17830ee1v0um00 (7/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec240h can0 message data byte 01 register 10 c0mdata0110 undefined 03fec240h can0 message data byte 0 register 10 c0mdata010 undefined 03fec241h can0 message data byte 1 register 10 c0mdata110 undefined 03fec242h can0 message data byte 23 register 10 c0mdata2310 undefined 03fec242h can0 message data byte 2 register 10 c0mdata210 undefined 03fec243h can0 message data byte 3 register 10 c0mdata310 undefined 03fec244h can0 message data byte 45 register 10 c0mdata4510 undefined 03fec244h can0 message data byte 4 register 10 c0mdata410 undefined 03fec245h can0 message data byte 5 register 10 c0mdata510 undefined 03fec246h can0 message data byte 67 register 10 c0mdata6710 undefined 03fec246h can0 message data byte 6 register 10 c0mdata610 undefined 03fec247h can0 message data byte 7 register 10 c0mdata710 undefined 03fec248h can0 message data length code register 10 c0mdlc10 0000xxxxb 03fec249h can0 message configurat ion register 10 c0mconf10 undefined 03fec24ah c0midl10 undefined 03fec24ch can0 message id register 10 c0midh10 undefined 03fec24eh can0 message control register 10 c0mctrl10 00x00000 000xx000b 03fec260h can0 message data byte 01 register 11 c0mdata0111 undefined 03fec260h can0 message data byte 0 register 11 c0mdata011 undefined 03fec261h can0 message data byte 1 register 11 c0mdata111 undefined 03fec262h can0 message data byte 23 register 11 c0mdata2311 undefined 03fec262h can0 message data byte 2 register 11 c0mdata211 undefined 03fec263h can0 message data byte 3 register 11 c0mdata311 undefined 03fec264h can0 message data byte 45 register 11 c0mdata4511 undefined 03fec264h can0 message data byte 4 register 11 c0mdata411 undefined 03fec265h can0 message data byte 5 register 11 c0mdata511 undefined 03fec266h can0 message data byte 67 register 11 c0mdata6711 undefined 03fec266h can0 message data byte 6 register 11 c0mdata611 undefined 03fec267h can0 message data byte 7 register 11 c0mdata711 undefined 03fec268h can0 message data length code register 11 c0mdlc11 0000xxxxb 03fec269h can0 message configurat ion register 11 c0mconf11 undefined 03fec26ah c0midl11 undefined 03fec26ch can0 message id register 11 c0midh11 undefined 03fec26eh can0 message control register 11 c0mctrl11 r/w 00x00000 000xx000b chapter 15 can controller 595 user?s manual u17830ee1v0um00 (8/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec280h can0 message data byte 01 register 12 c0mdata0112 undefined 03fec280h can0 message data byte 0 register 12 c0mdata012 undefined 03fec281h can0 message data byte 1 register 12 c0mdata112 undefined 03fec282h can0 message data byte 23 register 12 c0mdata2312 undefined 03fec282h can0 message data byte 2 register 12 c0mdata212 undefined 03fec283h can0 message data byte 3 register 12 c0mdata312 undefined 03fec284h can0 message data byte 45 register 12 c0mdata4512 undefined 03fec284h can0 message data byte 4 register 12 c0mdata412 undefined 03fec285h can0 message data byte 5 register 12 c0mdata512 undefined 03fec286h can0 message data byte 67 register 12 c0mdata6712 undefined 03fec286h can0 message data byte 6 register 12 c0mdata612 undefined 03fec287h can0 message data byte 7 register 12 c0mdata712 undefined 03fec288h can0 message data length code register 12 c0mdlc12 0000xxxxb 03fec289h can0 message configurat ion register 12 c0mconf12 undefined 03fec28ah c0midl12 undefined 03fec28ch can0 message id register 12 c0midh12 undefined 03fec28eh can0 message control register 12 c0mctrl12 00x00000 000xx000b 03fec2a0h can0 message data byte 01 register 13 c0mdata0113 undefined 03fec2a0h can0 message data byte 0 register 13 c0mdata013 undefined 03fec2a1h can0 message data byte 1 register 13 c0mdata113 undefined 03fec2a2h can0 message data byte 23 register 13 c0mdata2313 undefined 03fec2a2h can0 message data byte 2 register 13 c0mdata213 undefined 03fec2a3h can0 message data byte 3 register 13 c0mdata313 undefined 03fec2a4h can0 message data byte 45 register 13 c0mdata4513 undefined 03fec2a4h can0 message data byte 4 register 13 c0mdata413 undefined 03fec2a5h can0 message data byte 5 register 13 c0mdata513 undefined 03fec2a6h can0 message data byte 67 register 13 c0mdata6713 undefined 03fec2a6h can0 message data byte 6 register 13 c0mdata613 undefined 03fec2a7h can0 message data byte 7 register 13 c0mdata713 undefined 03fec2a8h can0 message data length code register 13 c0mdlc13 0000xxxxb 03fec2a9h can0 message configur ation register 13 c0mconf13 undefined 03fec2aah c0midl13 undefined 03fec2ach can0 message id register 13 c0midh13 undefined 03fec2aeh can0 message control register 13 c0mctrl13 r/w 00x00000 000xx000b chapter 15 can controller 596 user?s manual u17830ee1v0um00 (9/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec2c0h can0 message data byte 01 register 14 c0mdata0114 undefined 03fec2c0h can0 message data byte 0 register 14 c0mdata014 undefined 03fec2c1h can0 message data byte 1 register 14 c0mdata114 undefined 03fec2c2h can0 message data byte 23 register 14 c0mdata2314 undefined 03fec2c2h can0 message data byte 2 register 14 c0mdata214 undefined 03fec2c3h can0 message data byte 3 register 14 c0mdata314 undefined 03fec2c4h can0 message data byte 45 register 14 c0mdata4514 undefined 03fec2c4h can0 message data byte 4 register 14 c0mdata414 undefined 03fec2c5h can0 message data byte 5 register 14 c0mdata514 undefined 03fec2c6h can0 message data byte 67 register 14 c0mdata6714 undefined 03fec2c6h can0 message data byte 6 register 14 c0mdata614 undefined 03fec2c7h can0 message data byte 7 register 14 c0mdata714 undefined 03fec2c8h can0 message data length code register 14 c0mdlc14 0000xxxxb 03fec2c9h can0 message configur ation register 14 c0mconf14 undefined 03fec2cah c0midl14 undefined 03fec2cch can0 message id register 14 c0midh14 undefined 03fec2ceh can0 message control register 14 c0mctrl14 00x00000 000xx000b 03fec2e0h can0 message data byte 01 register 15 c0mdata0115 undefined 03fec2e0h can0 message data byte 0 register 15 c0mdata015 undefined 03fec2e1h can0 message data byte 1 register 15 c0mdata115 undefined 03fec2e2h can0 message data byte 23 register 15 c0mdata2315 undefined 03fec2e2h can0 message data byte 2 register 15 c0mdata215 undefined 03fec2e3h can0 message data byte 3 register 15 c0mdata315 undefined 03fec2e4h can0 message data byte 45 register 15 c0mdata4515 undefined 03fec2e4h can0 message data byte 4 register 15 c0mdata415 undefined 03fec2e5h can0 message data byte 5 register 15 c0mdata515 undefined 03fec2e6h can0 message data byte 67 register 15 c0mdata6715 undefined 03fec2e6h can0 message data byte 6 register 15 c0mdata615 undefined 03fec2e7h can0 message data byte 7 register 15 c0mdata715 undefined 03fec2e8h can0 message data length code register 15 c0mdlc15 0000xxxx 03fec2e9h can0 message configur ation register 15 c0mconf15 undefined 03fec2eah c0midl15 undefined 03fec2ech can0 message id register 15 c0midh15 undefined 03fec2eeh can0 message control register 15 c0mctrl15 r/w 00x00000 000xx000b chapter 15 can controller 597 user?s manual u17830ee1v0um00 (10/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec300h can0 message data byte 01 register 16 c0mdata0116 undefined 03fec300h can0 message data byte 0 register 16 c0mdata016 undefined 03fec301h can0 message data byte 1 register 16 c0mdata116 undefined 03fec302h can0 message data byte 23 register 16 c0mdata2316 undefined 03fec302h can0 message data byte 2 register 16 c0mdata216 undefined 03fec303h can0 message data byte 3 register 16 c0mdata316 undefined 03fec304h can0 message data byte 45 register 16 c0mdata4516 undefined 03fec304h can0 message data byte 4 register 16 c0mdata416 undefined 03fec305h can0 message data byte 5 register 16 c0mdata516 undefined 03fec306h can0 message data byte 67 register 16 c0mdata6716 undefined 03fec306h can0 message data byte 6 register 16 c0mdata616 undefined 03fec307h can0 message data byte 7 register 16 c0mdata716 undefined 03fec308h can0 message data length code register 16 c0mdlc16 0000xxxxb 03fec309h can0 message configurat ion register 16 c0mconf16 undefined 03fec30ah c0midl16 undefined 03fec30ch can0 message id register 16 c0midh16 undefined 03fec30eh can0 message control register 16 c0mctrl16 00x00000 000xx000b 03fec320h can0 message data byte 01 register 17 c0mdata0117 undefined 03fec320h can0 message data byte 0 register 17 c0mdata017 undefined 03fec321h can0 message data byte 1 register 17 c0mdata117 undefined 03fec322h can0 message data byte 23 register 17 c0mdata2317 undefined 03fec322h can0 message data byte 2 register 17 c0mdata217 undefined 03fec323h can0 message data byte 3 register 17 c0mdata317 undefined 03fec324h can0 message data byte 45 register 17 c0mdata4517 undefined 03fec324h can0 message data byte 4 register 17 c0mdata417 undefined 03fec325h can0 message data byte 5 register 17 c0mdata517 undefined 03fec326h can0 message data byte 67 register 17 c0mdata6717 undefined 03fec326h can0 message data byte 6 register 17 c0mdata617 undefined 03fec327h can0 message data byte 7 register 17 c0mdata717 undefined 03fec328h can0 message data length code register 17 c0mdlc17 0000xxxxb 03fec329h can0 message configurat ion register 17 c0mconf17 undefined 03fec32ah c0midl17 undefined 03fec32ch can0 message id register 17 c0midh17 undefined 03fec32eh can0 message control register 17 c0mctrl17 r/w 00x00000 000xx000b chapter 15 can controller 598 user?s manual u17830ee1v0um00 (11/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec340h can0 message data byte 01 register 18 c0mdata0118 undefined 03fec340h can0 message data byte 0 register 18 c0mdata018 undefined 03fec341h can0 message data byte 1 register 18 c0mdata118 undefined 03fec342h can0 message data byte 23 register 18 c0mdata2318 undefined 03fec342h can0 message data byte 2 register 18 c0mdata218 undefined 03fec343h can0 message data byte 3 register 18 c0mdata318 undefined 03fec344h can0 message data byte 45 register 18 c0mdata4518 undefined 03fec344h can0 message data byte 4 register 18 c0mdata418 undefined 03fec345h can0 message data byte 5 register 18 c0mdata518 undefined 03fec346h can0 message data byte 67 register 18 c0mdata6718 undefined 03fec346h can0 message data byte 6 register 18 c0mdata618 undefined 03fec347h can0 message data byte 7 register 18 c0mdata718 undefined 03fec348h can0 message data length code register 18 c0mdlc18 0000xxxxb 03fec349h can0 message configurat ion register 18 c0mconf18 undefined 03fec34ah c0midl18 undefined 03fec34ch can0 message id register 18 c0midh18 undefined 03fec34eh can0 message control register 18 c0mctrl18 00x00000 000xx000b 03fec360h can0 message data byte 01 register 19 c0mdata0119 undefined 03fec360h can0 message data byte 0 register 19 c0mdata019 undefined 03fec361h can0 message data byte 1 register 19 c0mdata119 undefined 03fec362h can0 message data byte 23 register 19 c0mdata2319 undefined 03fec362h can0 message data byte 2 register 19 c0mdata219 undefined 03fec363h can0 message data byte 3 register 19 c0mdata319 undefined 03fec364h can0 message data byte 45 register 19 c0mdata4519 undefined 03fec364h can0 message data byte 4 register 19 c0mdata419 undefined 03fec365h can0 message data byte 5 register 19 c0mdata519 undefined 03fec366h can0 message data byte 67 register 19 c0mdata6719 undefined 03fec366h can0 message data byte 6 register 19 c0mdata619 undefined 03fec367h can0 message data byte 7 register 19 c0mdata719 undefined 03fec368h can0 message data length code register 19 c0mdlc19 0000xxxxb 03fec369h can0 message configurat ion register 19 c0mconf19 undefined 03fec36ah c0midl19 undefined 03fec36ch can0 message id register 19 c0midh19 undefined 03fec36eh can0 message control register 19 c0mctrl19 r/w 00x00000 000xx000b chapter 15 can controller 599 user?s manual u17830ee1v0um00 (12/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec380h can0 message data byte 01 register 20 c0mdata0120 undefined 03fec380h can0 message data byte 0 register 20 c0mdata020 undefined 03fec381h can0 message data byte 1 register 20 c0mdata120 undefined 03fec382h can0 message data byte 23 register 20 c0mdata2320 undefined 03fec382h can0 message data byte 2 register 20 c0mdata220 undefined 03fec383h can0 message data byte 3 register 20 c0mdata320 undefined 03fec384h can0 message data byte 45 register 20 c0mdata4520 undefined 03fec384h can0 message data byte 4 register 20 c0mdata420 undefined 03fec385h can0 message data byte 5 register 20 c0mdata520 undefined 03fec386h can0 message data byte 67 register 20 c0mdata6720 undefined 03fec386h can0 message data byte 6 register 20 c0mdata620 undefined 03fec387h can0 message data byte 7 register 20 c0mdata720 undefined 03fec388h can0 message data length code register 20 c0mdlc20 0000xxxxb 03fec389h can0 message configurat ion register 20 c0mconf20 undefined 03fec38ah c0midl20 undefined 03fec38ch can0 message id register 20 c0midh20 undefined 03fec38eh can0 message control register 20 c0mctrl20 00x00000 000xx000b 03fec3a0h can0 message data byte 01 register 21 c0mdata0121 undefined 03fec3a0h can0 message data byte 0 register 21 c0mdata021 undefined 03fec3a1h can0 message data byte 1 register 21 c0mdata121 undefined 03fec3a2h can0 message data byte 23 register 21 c0mdata2321 undefined 03fec3a2h can0 message data byte 2 register 21 c0mdata221 undefined 03fec3a3h can0 message data byte 3 register 21 c0mdata321 undefined 03fec3a4h can0 message data byte 45 register 21 c0mdata4521 undefined 03fec3a4h can0 message data byte 4 register 21 c0mdata421 undefined 03fec3a5h can0 message data byte 5 register 21 c0mdata521 undefined 03fec3a6h can0 message data byte 67 register 21 c0mdata6721 undefined 03fec3a6h can0 message data byte 6 register 21 c0mdata621 undefined 03fec3a7h can0 message data byte 7 register 21 c0mdata721 undefined 03fec3a8h can0 message data length code register 21 c0mdlc21 0000xxxxb 03fec3a9h can0 message configur ation register 21 c0mconf21 undefined 03fec3aah c0midl21 undefined 03fec3ach can0 message id register 21 c0midh21 undefined 03fec3aeh can0 message control register 21 c0mctrl21 r/w 00x00000 000xx000b chapter 15 can controller 600 user?s manual u17830ee1v0um00 (13/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec3c0h can0 message data byte 01 register 22 c0mdata0122 undefined 03fec3c0h can0 message data byte 0 register 22 c0mdata022 undefined 03fec3c1h can0 message data byte 1 register 22 c0mdata122 undefined 03fec3c2h can0 message data byte 23 register 22 c0mdata2322 undefined 03fec3c2h can0 message data byte 2 register 22 c0mdata222 undefined 03fec3c3h can0 message data byte 3 register 22 c0mdata322 undefined 03fec3c4h can0 message data byte 45 register 22 c0mdata4522 undefined 03fec3c4h can0 message data byte 4 register 22 c0mdata422 undefined 03fec3c5h can0 message data byte 5 register 22 c0mdata522 undefined 03fec3c6h can0 message data byte 67 register 22 c0mdata6722 undefined 03fec3c6h can0 message data byte 6 register 22 c0mdata622 undefined 03fec3c7h can0 message data byte 7 register 22 c0mdata722 undefined 03fec3c8h can0 message data length code register 22 c0mdlc22 0000xxxxb 03fec3c9h can0 message configur ation register 22 c0mconf22 undefined 03fec3cah c0midl22 undefined 03fec3cch can0 message id register 22 c0midh22 undefined 03fec3ceh can0 message control register 22 c0mctrl22 00x00000 000xx000b 03fec3e0h can0 message data byte 01 register 23 c0mdata0123 undefined 03fec3e0h can0 message data byte 0 register 23 c0mdata023 undefined 03fec3e1h can0 message data byte 1 register 23 c0mdata123 undefined 03fec3e2h can0 message data byte 23 register 23 c0mdata2323 undefined 03fec3e2h can0 message data byte 2 register 23 c0mdata223 undefined 03fec3e3h can0 message data byte 3 register 23 c0mdata323 undefined 03fec3e4h can0 message data byte 45 register 23 c0mdata4523 undefined 03fec3e4h can0 message data byte 4 register 23 c0mdata423 undefined 03fec3e5h can0 message data byte 5 register 23 c0mdata523 undefined 03fec3e6h can0 message data byte 67 register 23 c0mdata6723 undefined 03fec3e6h can0 message data byte 6 register 23 c0mdata623 undefined 03fec3e7h can0 message data byte 7 register 23 c0mdata723 undefined 03fec3e8h can0 message data length code register 23 c0mdlc23 0000xxxxb 03fec3e9h can0 message configur ation register 23 c0mconf23 undefined 03fec3eah c0midl23 undefined 03fec3ech can0 message id register 23 c0midh23 undefined 03fec3eeh can0 message control register 23 c0mctrl23 r/w 00x00000 000xx000b chapter 15 can controller 601 user?s manual u17830ee1v0um00 (14/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec400h can0 message data byte 01 register 24 c0mdata0124 undefined 03fec400h can0 message data byte 0 register 24 c0mdata024 undefined 03fec401h can0 message data byte 1 register 24 c0mdata124 undefined 03fec402h can0 message data byte 23 register 24 c0mdata2324 undefined 03fec402h can0 message data byte 2 register 24 c0mdata224 undefined 03fec403h can0 message data byte 3 register 24 c0mdata324 undefined 03fec404h can0 message data byte 45 register 24 c0mdata4524 undefined 03fec404h can0 message data byte 4 register 24 c0mdata424 undefined 03fec405h can0 message data byte 5 register 24 c0mdata524 undefined 03fec406h can0 message data byte 67 register 24 c0mdata6724 undefined 03fec406h can0 message data byte 6 register 24 c0mdata624 undefined 03fec407h can0 message data byte 7 register 24 c0mdata724 undefined 03fec408h can0 message data length code register 24 c0mdlc24 0000xxxxb 03fec409h can0 message configurat ion register 24 c0mconf24 undefined 03fec40ah c0midl24 undefined 03fec40ch can0 message id register 24 c0midh24 undefined 03fec40eh can0 message control register 24 c0mctrl24 00x00000 000xx000b 03fec420h can0 message data byte 01 register 25 c0mdata0125 undefined 03fec420h can0 message data byte 0 register 25 c0mdata025 undefined 03fec421h can0 message data byte 1 register 25 c0mdata125 undefined 03fec422h can0 message data byte 23 register 25 c0mdata2325 undefined 03fec422h can0 message data byte 2 register 25 c0mdata225 undefined 03fec423h can0 message data byte 3 register 25 c0mdata325 undefined 03fec424h can0 message data byte 45 register 25 c0mdata4525 undefined 03fec424h can0 message data byte 4 register 25 c0mdata425 undefined 03fec425h can0 message data byte 5 register 25 c0mdata525 undefined 03fec426h can0 message data byte 67 register 25 c0mdata6725 undefined 03fec426h can0 message data byte 6 register 25 c0mdata625 undefined 03fec427h can0 message data byte 7 register 25 c0mdata725 undefined 03fec428h can0 message data length code register 25 c0mdlc25 0000xxxxb 03fec429h can0 message configurat ion register 25 c0mconf25 undefined 03fec42ah c0midl25 undefined 03fec42ch can0 message id register 25 c0midh25 undefined 03fec42eh can0 message control register 25 c0mctrl25 r/w 00x00000 000xx000b chapter 15 can controller 602 user?s manual u17830ee1v0um00 (15/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec440h can0 message data byte 01 register 26 c0mdata0126 undefined 03fec440h can0 message data byte 0 register 26 c0mdata026 undefined 03fec441h can0 message data byte 1 register 26 c0mdata126 undefined 03fec442h can0 message data byte 23 register 26 c0mdata2326 undefined 03fec442h can0 message data byte 2 register 26 c0mdata226 undefined 03fec443h can0 message data byte 3 register 26 c0mdata326 undefined 03fec444h can0 message data byte 45 register 26 c0mdata4526 undefined 03fec444h can0 message data byte 4 register 26 c0mdata426 undefined 03fec445h can0 message data byte 5 register 26 c0mdata526 undefined 03fec446h can0 message data byte 67 register 26 c0mdata6726 undefined 03fec446h can0 message data byte 6 register 26 c0mdata626 undefined 03fec447h can0 message data byte 7 register 26 c0mdata726 undefined 03fec448h can0 message data length code register 26 c0mdlc26 0000xxxxb 03fec449h can0 message configurat ion register 26 c0mconf26 undefined 03fec44ah c0midl26 undefined 03fec44ch can0 message id register 26 c0midh26 undefined 03fec44eh can0 message control register 26 c0mctrl26 00x00000 000xx000b 03fec460h can0 message data byte 01 register 27 c0mdata0127 undefined 03fec460h can0 message data byte 0 register 27 c0mdata027 undefined 03fec461h can0 message data byte 1 register 27 c0mdata127 undefined 03fec462h can0 message data byte 23 register 27 c0mdata2327 undefined 03fec462h can0 message data byte 2 register 27 c0mdata227 undefined 03fec463h can0 message data byte 3 register 27 c0mdata327 undefined 03fec464h can0 message data byte 45 register 27 c0mdata4527 undefined 03fec464h can0 message data byte 4 register 27 c0mdata427 undefined 03fec465h can0 message data byte 5 register 27 c0mdata527 undefined 03fec466h can0 message data byte 67 register 27 c0mdata6727 undefined 03fec466h can0 message data byte 6 register 27 c0mdata627 undefined 03fec467h can0 message data byte 7 register 27 c0mdata727 undefined 03fec468h can0 message data length code register 27 c0mdlc27 0000xxxxb 03fec469h can0 message configurat ion register 27 c0mconf27 undefined 03fec46ah c0midl27 undefined 03fec46ch can0 message id register 27 c0midh27 undefined 03fec46eh can0 message control register 27 c0mctrl27 r/w 00x00000 000xx000b chapter 15 can controller 603 user?s manual u17830ee1v0um00 (16/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec480h can0 message data byte 01 register 28 c0mdata0128 undefined 03fec480h can0 message data byte 0 register 28 c0mdata028 undefined 03fec481h can0 message data byte 1 register 28 c0mdata128 undefined 03fec482h can0 message data byte 23 register 28 c0mdata2328 undefined 03fec482h can0 message data byte 2 register 28 c0mdata228 undefined 03fec483h can0 message data byte 3 register 28 c0mdata328 undefined 03fec484h can0 message data byte 45 register 28 c0mdata4528 undefined 03fec484h can0 message data byte 4 register 28 c0mdata428 undefined 03fec485h can0 message data byte 5 register 28 c0mdata528 undefined 03fec486h can0 message data byte 67 register 28 c0mdata6728 undefined 03fec486h can0 message data byte 6 register 28 c0mdata628 undefined 03fec487h can0 message data byte 7 register 28 c0mdata728 undefined 03fec488h can0 message data length code register 28 c0mdlc28 0000xxxxb 03fec489h can0 message configurat ion register 28 c0mconf28 undefined 03fec48ah c0midl28 undefined 03fec48ch can0 message id register 28 c0midh28 undefined 03fec48eh can0 message control register 28 c0mctrl28 00x00000 000xx000b 03fec4a0h can0 message data byte 01 register 29 c0mdata0129 undefined 03fec4a0h can0 message data byte 0 register 29 c0mdata029 undefined 03fec4a1h can0 message data byte 1 register 29 c0mdata129 undefined 03fec4a2h can0 message data byte 23 register 29 c0mdata2329 undefined 03fec4a2h can0 message data byte 2 register 29 c0mdata229 undefined 03fec4a3h can0 message data byte 3 register 29 c0mdata329 undefined 03fec4a4h can0 message data byte 45 register 29 c0mdata4529 undefined 03fec4a4h can0 message data byte 4 register 29 c0mdata429 undefined 03fec4a5h can0 message data byte 5 register 29 c0mdata529 undefined 03fec4a6h can0 message data byte 67 register 29 c0mdata6729 undefined 03fec4a6h can0 message data byte 6 register 29 c0mdata629 undefined 03fec4a7h can0 message data byte 7 register 29 c0mdata729 undefined 03fec4a8h can0 message data length code register 29 c0mdlc29 0000xxxxb 03fec4a9h can0 message configur ation register 29 c0mconf29 undefined 03fec4aah c0midl29 undefined 03fec4ach can0 message id register 29 c0midh29 undefined 03fec4aeh can0 message control register 29 c0mctrl29 r/w 00x00000 000xx000b chapter 15 can controller 604 user?s manual u17830ee1v0um00 (17/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec4c0h can0 message data byte 01 register 30 c0mdata0130 undefined 03fec4c0h can0 message data byte 0 register 30 c0mdata030 undefined 03fec4c1h can0 message data byte 1 register 30 c0mdata130 undefined 03fec4c2h can0 message data byte 23 register 30 c0mdata2330 undefined 03fec4c2h can0 message data byte 2 register 30 c0mdata230 undefined 03fec4c3h can0 message data byte 3 register 30 c0mdata330 undefined 03fec4c4h can0 message data byte 45 register 30 c0mdata4530 undefined 03fec4c4h can0 message data byte 4 register 30 c0mdata430 undefined 03fec4c5h can0 message data byte 5 register 30 c0mdata530 undefined 03fec4c6h can0 message data byte 67 register 30 c0mdata6730 undefined 03fec4c6h can0 message data byte 6 register 30 c0mdata630 undefined 03fec4c7h can0 message data byte 7 register 30 c0mdata730 undefined 03fec4c8h can0 message data length code register 30 c0mdlc30 0000xxxxb 03fec4c9h can0 message configur ation register 30 c0mconf30 undefined 03fec4cah c0midl30 undefined 03fec4cch can0 message id register 30 c0midh30 undefined 03fec4ceh can0 message control register 30 c0mctrl30 00x00000 000xx000b 03fec4e0h can0 message data byte 01 register 31 c0mdata0131 undefined 03fec4e0h can0 message data byte 0 register 31 c0mdata031 undefined 03fec4e1h can0 message data byte 1 register 31 c0mdata131 undefined 03fec4e2h can0 message data byte 23 register 31 c0mdata2331 undefined 03fec4e2h can0 message data byte 2 register 31 c0mdata231 undefined 03fec4e3h can0 message data byte 3 register 31 c0mdata331 undefined 03fec4e4h can0 message data byte 45 register 31 c0mdata4531 undefined 03fec4e4h can0 message data byte 4 register 31 c0mdata431 undefined 03fec4e5h can0 message data byte 5 register 31 c0mdata531 undefined 03fec4e6h can0 message data byte 67 register 31 c0mdata6731 undefined 03fec4e6h can0 message data byte 6 register 31 c0mdata631 undefined 03fec4e7h can0 message data byte 7 register 31 c0mdata731 undefined 03fec4e8h can0 message data length code register 31 c0mdlc31 0000xxxx 03fec4e9h can0 message configur ation register 31 c0mconf31 undefined 03fec4eah c0midl31 undefined 03fec4ech can0 message id register 31 c0midh31 undefined 03fec4eeh can0 message control register 31 c0mctrl31 r/w 00x00000 000xx000b chapter 15 can controller 605 user?s manual u17830ee1v0um00 (18/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec600h can1 global control register c1gmctrl r/w ? ? 0000h 03fec602h can1 global clock se lect register c1gmcs r/w ? ? 0fh 03fec606h can1 global blo ck transmission control register c1gmabt r/w ? ? 0000h 03fec608h can1 global block transmission delay setting register c1gmabtd r/w ? ? 00h 03fec640h c1mask1l 03fec642h can1 module mask 1 register c1mask1h r/w ? ? undefined 03fec644h c1mask2l 03fec646h can1 module mask 2 register c1mask2h r/w ? ? undefined 03fec648h c1mask3l 03fec64ah can1 module mask 3 register c1mask3h r/w ? ? undefined 03fec64ch c1mask4l 03fec64eh can1 module mask 4 register c1mask4h r/w ? ? undefined 03fec650h can1 module control register c1ctrl r/w ? ? 0000h 03fec652h can1 module last error information register c1lec r/w ? ? 00h 03fec653h can1 module information register c1info r ? ? 00h 03fec654h can1 module error counter register c1erc r ? ? 0000h 03fec656h can1 module interrupt enable register c1ie r/w ? ? 0000h 03fec658h can1 module interrupt status register c1ints r/w ? ? 0000h 03fec65ah can1 module bit rate prescaler register c1brp r/w ? ? ffh 03fec65ch can1 module bit rate register c1btr r/w ? ? 370fh 03fec65eh can1 module last in-pointer register c1lipt r ? ? undefined 03fec660h can1 module receive hist ory list register c1rgpt r/w ? ? xx02h 03fec662h can1 module last out-pointer register c1lopt r ? ? undefined 03fec664h can1 module transmit history list register c1tgpt r/w ? ? xx02h 03fec666h can1 module time stamp register c1ts r/w ? ? 0000h chapter 15 can controller 606 user?s manual u17830ee1v0um00 (19/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec700h can1 message data byte 01 register 00 c1mdata0100 undefined 03fec700h can1 message data byte 0 register 00 c1mdata000 undefined 03fec701h can1 message data byte 1 register 00 c1mdata100 undefined 03fec702h can1 message data byte 23 register 00 c1mdata2300 undefined 03fec702h can1 message data byte 2 register 00 c1mdata200 undefined 03fec703h can1 message data byte 3 register 00 c1mdata300 undefined 03fec704h can1 message data byte 45 register 00 c1mdata4500 undefined 03fec704h can1 message data byte 4 register 00 c1mdata400 undefined 03fec705h can1 message data byte 5 register 00 c1mdata500 undefined 03fec706h can1 message data byte 67 register 00 c1mdata6700 undefined 03fec706h can1 message data byte 6 register 00 c1mdata600 undefined 03fec707h can1 message data byte 7 register 00 c1mdata700 undefined 03fec708h can1 message data length code register 00 c1mdlc00 0000xxxxb 03fec709h can1 message configurat ion register 00 c1mconf00 undefined 03fec70ah c1midl00 undefined 03fec70ch can1 message id register 00 c1midh00 undefined 03fec70eh can1 message control register 00 c1mctrl00 00x00000 000xx000b 03fec720h can1 message data byte 01 register 01 c1mdata0101 undefined 03fec720h can1 message data byte 0 register 01 c1mdata001 undefined 03fec721h can1 message data byte 1 register 01 c1mdata101 undefined 03fec722h can1 message data byte 23 register 01 c1mdata2301 undefined 03fec722h can1 message data byte 2 register 01 c1mdata201 undefined 03fec723h can1 message data byte 3 register 01 c1mdata301 undefined 03fec724h can1 message data byte 45 register 01 c1mdata4501 undefined 03fec724h can1 message data byte 4 register 01 c1mdata401 undefined 03fec725h can1 message data byte 5 register 01 c1mdata501 undefined 03fec726h can1 message data byte 67 register 01 c1mdata6701 undefined 03fec726h can1 message data byte 6 register 01 c1mdata601 undefined 03fec727h can1 message data byte 7 register 01 c1mdata701 undefined 03fec728h can1 message data length code register 01 c1mdlc01 0000xxxxb 03fec729h can1 message configurat ion register 01 c1mconf01 undefined 03fec72ah c1midl01 undefined 03fec72ch can1 message id register 01 c1midh01 undefined 03fec72eh can1 message control register 01 c1mctrl01 r/w 00x00000 000xx000b chapter 15 can controller 607 user?s manual u17830ee1v0um00 (20/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec740h can1 message data byte 01 register 02 c1mdata0102 undefined 03fec740h can1 message data byte 0 register 02 c1mdata002 undefined 03fec741h can1 message data byte 1 register 02 c1mdata102 undefined 03fec742h can1 message data byte 23 register 02 c1mdata2302 undefined 03fec742h can1 message data byte 2 register 02 c1mdata202 undefined 03fec743h can1 message data byte 3 register 02 c1mdata302 undefined 03fec744h can1 message data byte 45 register 02 c1mdata4502 undefined 03fec744h can1 message data byte 4 register 02 c1mdata402 undefined 03fec745h can1 message data byte 5 register 02 c1mdata502 undefined 03fec746h can1 message data byte 67 register 02 c1mdata6702 undefined 03fec746h can1 message data byte 6 register 02 c1mdata602 undefined 03fec747h can1 message data byte 7 register 02 c1mdata702 undefined 03fec748h can1 message data length code register 02 c1mdlc02 0000xxxxb 03fec749h can1 message configurat ion register 02 c1mconf02 undefined 03fec74ah c1midl02 undefined 03fec74ch can1 message id register 02 c1midh02 undefined 03fec74eh can1 message control register 02 c1mctrl02 00x00000 000xx000b 03fec760h can1 message data byte 01 register 03 c1mdata0103 undefined 03fec760h can1 message data byte 0 register 03 c1mdata003 undefined 03fec761h can1 message data byte 1 register 03 c1mdata103 undefined 03fec762h can1 message data byte 23 register 03 c1mdata2303 undefined 03fec762h can1 message data byte 2 register 03 c1mdata203 undefined 03fec763h can1 message data byte 3 register 03 c1mdata303 undefined 03fec764h can1 message data byte 45 register 03 c1mdata4503 undefined 03fec764h can1 message data byte 4 register 03 c1mdata403 undefined 03fec765h can1 message data byte 5 register 03 c1mdata503 undefined 03fec766h can1 message data byte 67 register 03 c1mdata6703 undefined 03fec766h can1 message data byte 6 register 03 c1mdata603 undefined 03fec767h can1 message data byte 7 register 03 c1mdata703 undefined 03fec768h can1 message data length code register 03 c1mdlc03 0000xxxxb 03fec769h can1 message configurat ion register 03 c1mconf03 undefined 03fec76ah c1midl03 undefined 03fec76ch can1 message id register 03 c1midh03 undefined 03fec76eh can1 message control register 03 c1mctrl03 r/w 00x00000 000xx000b chapter 15 can controller 608 user?s manual u17830ee1v0um00 (21/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec780h can1 message data byte 01 register 04 c1mdata0104 undefined 03fec780h can1 message data byte 0 register 04 c1mdata004 undefined 03fec781h can1 message data byte 1 register 04 c1mdata104 undefined 03fec782h can1 message data byte 23 register 04 c1mdata2304 undefined 03fec782h can1 message data byte 2 register 04 c1mdata204 undefined 03fec783h can1 message data byte 3 register 04 c1mdata304 undefined 03fec784h can1 message data byte 45 register 04 c1mdata4504 undefined 03fec784h can1 message data byte 4 register 04 c1mdata404 undefined 03fec785h can1 message data byte 5 register 04 c1mdata504 undefined 03fec786h can1 message data byte 67 register 04 c1mdata6704 undefined 03fec786h can1 message data byte 6 register 04 c1mdata604 undefined 03fec787h can1 message data byte 7 register 04 c1mdata704 undefined 03fec788h can1 message data length code register 04 c1mdlc04 0000xxxxb 03fec789h can1 message configurat ion register 04 c1mconf04 undefined 03fec78ah c1midl04 undefined 03fec78ch can1 message id register 04 c1midh04 undefined 03fec78eh can1 message control register 04 c1mctrl04 00x00000 000xx000b 03fec7a0h can1 message data byte 01 register 05 c1mdata0105 undefined 03fec7a0h can1 message data byte 0 register 05 c1mdata005 undefined 03fec7a1h can1 message data byte 1 register 05 c1mdata105 undefined 03fec7a2h can1 message data byte 23 register 05 c1mdata2305 undefined 03fec7a2h can1 message data byte 2 register 05 c1mdata205 undefined 03fec7a3h can1 message data byte 3 register 05 c1mdata305 undefined 03fec7a4h can1 message data byte 45 register 05 c1mdata4505 undefined 03fec7a4h can1 message data byte 4 register 05 c1mdata405 undefined 03fec7a5h can1 message data byte 5 register 05 c1mdata505 undefined 03fec7a6h can1 message data byte 67 register 05 c1mdata6705 undefined 03fec7a6h can1 message data byte 6 register 05 c1mdata605 undefined 03fec7a7h can1 message data byte 7 register 05 c1mdata705 undefined 03fec7a8h can1 message data length code register 05 c1mdlc05 0000xxxxb 03fec7a9h can1 message configur ation register 05 c1mconf05 undefined 03fec7aah c1midl05 undefined 03fec7ach can1 message id register 05 c1midh05 undefined 03fec7aeh can1 message control register 05 c1mctrl05 r/w 00x00000 000xx000b chapter 15 can controller 609 user?s manual u17830ee1v0um00 (22/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec7c0h can1 message data byte 01 register 06 c1mdata0106 undefined 03fec7c0h can1 message data byte 0 register 06 c1mdata006 undefined 03fec7c1h can1 message data byte 1 register 06 c1mdata106 undefined 03fec7c2h can1 message data byte 23 register 06 c1mdata2306 undefined 03fec7c2h can1 message data byte 2 register 06 c1mdata206 undefined 03fec7c3h can1 message data byte 3 register 06 c1mdata306 undefined 03fec7c4h can1 message data byte 45 register 06 c1mdata4506 undefined 03fec7c4h can1 message data byte 4 register 06 c1mdata406 undefined 03fec7c5h can1 message data byte 5 register 06 c1mdata506 undefined 03fec7c6h can1 message data byte 67 register 06 c1mdata6706 undefined 03fec7c6h can1 message data byte 6 register 06 c1mdata606 undefined 03fec7c7h can1 message data byte 7 register 06 c1mdata706 undefined 03fec7c8h can1 message data length code register 06 c1mdlc06 0000xxxxb 03fec7c9h can1 message configur ation register 06 c1mconf06 undefined 03fec7cah c1midl06 undefined 03fec7cch can1 message id register 06 c1midh06 undefined 03fec7ceh can1 message control register 06 c1mctrl06 00x00000 000xx000b 03fec7e0h can1 message data byte 01 register 07 c1mdata0107 undefined 03fec7e0h can1 message data byte 0 register 07 c1mdata007 undefined 03fec7e1h can1 message data byte 1 register 07 c1mdata107 undefined 03fec7e2h can1 message data byte 23 register 07 c1mdata2307 undefined 03fec7e2h can1 message data byte 2 register 07 c1mdata207 undefined 03fec7e3h can1 message data byte 3 register 07 c1mdata307 undefined 03fec7e4h can1 message data byte 45 register 07 c1mdata4507 undefined 03fec7e4h can1 message data byte 4 register 07 c1mdata407 undefined 03fec7e5h can1 message data byte 5 register 07 c1mdata507 undefined 03fec7e6h can1 message data byte 67 register 07 c1mdata6707 undefined 03fec7e6h can1 message data byte 6 register 07 c1mdata607 undefined 03fec7e7h can1 message data byte 7 register 07 c1mdata707 undefined 03fec7e8h can1 message data length code register 07 c1mdlc07 0000xxxxb 03fec7e9h can1 message configur ation register 07 c1mconf07 undefined 03fec7eah c1midl07 undefined 03fec7ech can1 message id register 07 c1midh07 undefined 03fec7eeh can1 message control register 07 c1mctrl07 r/w 00x00000 000xx000b chapter 15 can controller 610 user?s manual u17830ee1v0um00 (23/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec800h can1 message data byte 01 register 08 c1mdata0108 undefined 03fec800h can1 message data byte 0 register 08 c1mdata008 undefined 03fec801h can1 message data byte 1 register 08 c1mdata108 undefined 03fec802h can1 message data byte 23 register 08 c1mdata2308 undefined 03fec802h can1 message data byte 2 register 08 c1mdata208 undefined 03fec803h can1 message data byte 3 register 08 c1mdata308 undefined 03fec804h can1 message data byte 45 register 08 c1mdata4508 undefined 03fec804h can1 message data byte 4 register 08 c1mdata408 undefined 03fec805h can1 message data byte 5 register 08 c1mdata508 undefined 03fec806h can1 message data byte 67 register 08 c1mdata6708 undefined 03fec806h can1 message data byte 6 register 08 c1mdata608 undefined 03fec807h can1 message data byte 7 register 08 c1mdata708 undefined 03fec808h can1 message data length code register 08 c1mdlc08 0000xxxxb 03fec809h can1 message configurat ion register 08 c1mconf08 undefined 03fec80ah c1midl08 undefined 03fec80ch can1 message id register 08 c1midh08 undefined 03fec80eh can1 message control register 08 c1mctrl08 00x00000 000xx000b 03fec820h can1 message data byte 01 register 09 c1mdata0109 undefined 03fec820h can1 message data byte 0 register 09 c1mdata009 undefined 03fec821h can1 message data byte 1 register 09 c1mdata109 undefined 03fec822h can1 message data byte 23 register 09 c1mdata2309 undefined 03fec822h can1 message data byte 2 register 09 c1mdata209 undefined 03fec823h can1 message data byte 3 register 09 c1mdata309 undefined 03fec824h can1 message data byte 45 register 09 c1mdata4509 undefined 03fec824h can1 message data byte 4 register 09 c1mdata409 undefined 03fec825h can1 message data byte 5 register 09 c1mdata509 undefined 03fec826h can1 message data byte 67 register 09 c1mdata6709 undefined 03fec826h can1 message data byte 6 register 09 c1mdata609 undefined 03fec827h can1 message data byte 7 register 09 c1mdata709 undefined 03fec828h can1 message data length code register 09 c1mdlc09 0000xxxxb 03fec829h can1 message configurat ion register 09 c1mconf09 undefined 03fec82ah c1midl09 undefined 03fec82ch can1 message id register 09 c1midh09 undefined 03fec82eh can1 message control register 09 c1mctrl09 r/w 00x00000 000xx000b chapter 15 can controller 611 user?s manual u17830ee1v0um00 (24/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec840h can1 message data byte 01 register 10 c1mdata0110 undefined 03fec840h can1 message data byte 0 register 10 c1mdata010 undefined 03fec841h can1 message data byte 1 register 10 c1mdata110 undefined 03fec842h can1 message data byte 23 register 10 c1mdata2310 undefined 03fec842h can1 message data byte 2 register 10 c1mdata210 undefined 03fec843h can1 message data byte 3 register 10 c1mdata310 undefined 03fec844h can1 message data byte 45 register 10 c1mdata4510 undefined 03fec844h can1 message data byte 4 register 10 c1mdata410 undefined 03fec845h can1 message data byte 5 register 10 c1mdata510 undefined 03fec846h can1 message data byte 67 register 10 c1mdata6710 undefined 03fec846h can1 message data byte 6 register 10 c1mdata610 undefined 03fec847h can1 message data byte 7 register 10 c1mdata710 undefined 03fec848h can1 message data length code register 10 c1mdlc10 0000xxxxb 03fec849h can1 message configurat ion register 10 c1mconf10 undefined 03fec84ah c1midl10 undefined 03fec84ch can1 message id register 10 c1midh10 undefined 03fec84eh can1 message control register 10 c1mctrl10 00x00000 000xx000b 03fec860h can1 message data byte 01 register 11 c1mdata0111 undefined 03fec860h can1 message data byte 0 register 11 c1mdata011 undefined 03fec861h can1 message data byte 1 register 11 c1mdata111 undefined 03fec862h can1 message data byte 23 register 11 c1mdata2311 undefined 03fec862h can1 message data byte 2 register 11 c1mdata211 undefined 03fec863h can1 message data byte 3 register 11 c1mdata311 undefined 03fec864h can1 message data byte 45 register 11 c1mdata4511 undefined 03fec864h can1 message data byte 4 register 11 c1mdata411 undefined 03fec865h can1 message data byte 5 register 11 c1mdata511 undefined 03fec866h can1 message data byte 67 register 11 c1mdata6711 undefined 03fec866h can1 message data byte 6 register 11 c1mdata611 undefined 03fec867h can1 message data byte 7 register 11 c1mdata711 undefined 03fec868h can1 message data length code register 11 c1mdlc11 0000xxxxb 03fec869h can1 message configurat ion register 11 c1mconf11 undefined 03fec86ah c1midl11 undefined 03fec86ch can1 message id register 11 c1midh11 undefined 03fec86eh can1 message control register 11 c1mctrl11 r/w 00x00000 000xx000b chapter 15 can controller 612 user?s manual u17830ee1v0um00 (25/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec880h can1 message data byte 01 register 12 c1mdata0112 undefined 03fec880h can1 message data byte 0 register 12 c1mdata012 undefined 03fec881h can1 message data byte 1 register 12 c1mdata112 undefined 03fec882h can1 message data byte 23 register 12 c1mdata2312 undefined 03fec882h can1 message data byte 2 register 12 c1mdata212 undefined 03fec883h can1 message data byte 3 register 12 c1mdata312 undefined 03fec884h can1 message data byte 45 register 12 c1mdata4512 undefined 03fec884h can1 message data byte 4 register 12 c1mdata412 undefined 03fec885h can1 message data byte 5 register 12 c1mdata512 undefined 03fec886h can1 message data byte 67 register 12 c1mdata6712 undefined 03fec886h can1 message data byte 6 register 12 c1mdata612 undefined 03fec887h can1 message data byte 7 register 12 c1mdata712 undefined 03fec888h can1 message data length code register 12 c1mdlc12 0000xxxxb 03fec889h can1 message configurat ion register 12 c1mconf12 undefined 03fec88ah c1midl12 undefined 03fec88ch can1 message id register 12 c1midh12 undefined 03fec88eh can1 message control register 12 c1mctrl12 00x00000 000xx000b 03fec8a0h can1 message data byte 01 register 13 c1mdata0113 undefined 03fec8a0h can1 message data byte 0 register 13 c1mdata013 undefined 03fec8a1h can1 message data byte 1 register 13 c1mdata113 undefined 03fec8a2h can1 message data byte 23 register 13 c1mdata2313 undefined 03fec8a2h can1 message data byte 2 register 13 c1mdata213 undefined 03fec8a3h can1 message data byte 3 register 13 c1mdata313 undefined 03fec8a4h can1 message data byte 45 register 13 c1mdata4513 undefined 03fec8a4h can1 message data byte 4 register 13 c1mdata413 undefined 03fec8a5h can1 message data byte 5 register 13 c1mdata513 undefined 03fec8a6h can1 message data byte 67 register 13 c1mdata6713 undefined 03fec8a6h can1 message data byte 6 register 13 c1mdata613 undefined 03fec8a7h can1 message data byte 7 register 13 c1mdata713 undefined 03fec8a8h can1 message data length code register 13 c1mdlc13 0000xxxxb 03fec8a9h can1 message configur ation register 13 c1mconf13 undefined 03fec8aah c1midl13 undefined 03fec8ach can1 message id register 13 c1midh13 undefined 03fec8aeh can1 message control register 13 c1mctrl13 r/w 00x00000 000xx000b chapter 15 can controller 613 user?s manual u17830ee1v0um00 (26/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec8c0h can1 message data byte 01 register 14 c1mdata0114 undefined 03fec8c0h can1 message data byte 0 register 14 c1mdata014 undefined 03fec8c1h can1 message data byte 1 register 14 c1mdata114 undefined 03fec8c2h can1 message data byte 23 register 14 c1mdata2314 undefined 03fec8c2h can1 message data byte 2 register 14 c1mdata214 undefined 03fec8c3h can1 message data byte 3 register 14 c1mdata314 undefined 03fec8c4h can1 message data byte 45 register 14 c1mdata4514 undefined 03fec8c4h can1 message data byte 4 register 14 c1mdata414 undefined 03fec8c5h can1 message data byte 5 register 14 c1mdata514 undefined 03fec8c6h can1 message data byte 67 register 14 c1mdata6714 undefined 03fec8c6h can1 message data byte 6 register 14 c1mdata614 undefined 03fec8c7h can1 message data byte 7 register 14 c1mdata714 undefined 03fec8c8h can1 message data length code register 14 c1mdlc14 0000xxxxb 03fec8c9h can1 message configur ation register 14 c1mconf14 undefined 03fec8cah c1midl14 undefined 03fec8cch can1 message id register 14 c1midh14 undefined 03fec8ceh can1 message control register 14 c1mctrl14 00x00000 000xx000b 03fec8e0h can1 message data byte 01 register 15 c1mdata0115 undefined 03fec8e0h can1 message data byte 0 register 15 c1mdata015 undefined 03fec8e1h can1 message data byte 1 register 15 c1mdata115 undefined 03fec8e2h can1 message data byte 23 register 15 c1mdata2315 undefined 03fec8e2h can1 message data byte 2 register 15 c1mdata215 undefined 03fec8e3h can1 message data byte 3 register 15 c1mdata315 undefined 03fec8e4h can1 message data byte 45 register 15 c1mdata4515 undefined 03fec8e4h can1 message data byte 4 register 15 c1mdata415 undefined 03fec8e5h can1 message data byte 5 register 15 c1mdata515 undefined 03fec8e6h can1 message data byte 67 register 15 c1mdata6715 undefined 03fec8e6h can1 message data byte 6 register 15 c1mdata615 undefined 03fec8e7h can1 message data byte 7 register 15 c1mdata715 undefined 03fec8e8h can1 message data length code register 15 c1mdlc15 0000xxxxb 03fec8e9h can1 message configur ation register 15 c1mconf15 undefined 03fec8eah c1midl15 undefined 03fec8ech can1 message id register 15 c1midh15 undefined 03fec8eeh can1 message control register 15 c1mctrl15 r/w 00x00000 000xx000b chapter 15 can controller 614 user?s manual u17830ee1v0um00 (27/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec900h can1 message data byte 01 register 16 c1mdata0116 undefined 03fec900h can1 message data byte 0 register 16 c1mdata016 undefined 03fec901h can1 message data byte 1 register 16 c1mdata116 undefined 03fec902h can1 message data byte 23 register 16 c1mdata2316 undefined 03fec902h can1 message data byte 2 register 16 c1mdata216 undefined 03fec903h can1 message data byte 3 register 16 c1mdata316 undefined 03fec904h can1 message data byte 45 register 16 c1mdata4516 undefined 03fec904h can1 message data byte 4 register 16 c1mdata416 undefined 03fec905h can1 message data byte 5 register 16 c1mdata516 undefined 03fec906h can1 message data byte 67 register 16 c1mdata6716 undefined 03fec906h can1 message data byte 6 register 16 c1mdata616 undefined 03fec907h can1 message data byte 7 register 16 c1mdata716 undefined 03fec908h can1 message data length code register 16 c1mdlc16 0000xxxxb 03fec909h can1 message configurat ion register 16 c1mconf16 undefined 03fec90ah c1midl16 undefined 03fec90ch can1 message id register 16 c1midh16 undefined 03fec90eh can1 message control register 16 c1mctrl16 00x00000 000xx000b 03fec920h can1 message data byte 01 register 17 c1mdata0117 undefined 03fec920h can1 message data byte 0 register 17 c1mdata017 undefined 03fec921h can1 message data byte 1 register 17 c1mdata117 undefined 03fec922h can1 message data byte 23 register 17 c1mdata2317 undefined 03fec922h can1 message data byte 2 register 17 c1mdata217 undefined 03fec923h can1 message data byte 3 register 17 c1mdata317 undefined 03fec924h can1 message data byte 45 register 17 c1mdata4517 undefined 03fec924h can1 message data byte 4 register 17 c1mdata417 undefined 03fec925h can1 message data byte 5 register 17 c1mdata517 undefined 03fec926h can1 message data byte 67 register 17 c1mdata6717 undefined 03fec926h can1 message data byte 6 register 17 c1mdata617 undefined 03fec927h can1 message data byte 7 register 17 c1mdata717 undefined 03fec928h can1 message data length code register 17 c1mdlc17 0000xxxxb 03fec929h can1 message configurat ion register 17 c1mconf17 undefined 03fec92ah c1midl17 undefined 03fec92ch can1 message id register 17 c1midh17 undefined 03fec92eh can1 message control register 17 c1mctrl17 r/w 00x00000 000xx000b chapter 15 can controller 615 user?s manual u17830ee1v0um00 (28/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec940h can1 message data byte 01 register 18 c1mdata0118 undefined 03fec940h can1 message data byte 0 register 18 c1mdata018 undefined 03fec941h can1 message data byte 1 register 18 c1mdata118 undefined 03fec942h can1 message data byte 23 register 18 c1mdata2318 undefined 03fec942h can1 message data byte 2 register 18 c1mdata218 undefined 03fec943h can1 message data byte 3 register 18 c1mdata318 undefined 03fec944h can1 message data byte 45 register 18 c1mdata4518 undefined 03fec944h can1 message data byte 4 register 18 c1mdata418 undefined 03fec945h can1 message data byte 5 register 18 c1mdata518 undefined 03fec946h can1 message data byte 67 register 18 c1mdata6718 undefined 03fec946h can1 message data byte 6 register 18 c1mdata618 undefined 03fec947h can1 message data byte 7 register 18 c1mdata718 undefined 03fec948h can1 message data length code register 18 c1mdlc18 0000xxxxb 03fec949h can1 message configurat ion register 18 c1mconf18 undefined 03fec94ah c1midl18 undefined 03fec94ch can1 message id register 18 c1midh18 undefined 03fec94eh can1 message control register 18 c1mctrl18 00x00000 000xx000b 03fec960h can1 message data byte 01 register 19 c1mdata0119 undefined 03fec960h can1 message data byte 0 register 19 c1mdata019 undefined 03fec961h can1 message data byte 1 register 19 c1mdata119 undefined 03fec962h can1 message data byte 23 register 19 c1mdata2319 undefined 03fec962h can1 message data byte 2 register 19 c1mdata219 undefined 03fec963h can1 message data byte 3 register 19 c1mdata319 undefined 03fec964h can1 message data byte 45 register 19 c1mdata4519 undefined 03fec964h can1 message data byte 4 register 19 c1mdata419 undefined 03fec965h can1 message data byte 5 register 19 c1mdata519 undefined 03fec966h can1 message data byte 67 register 19 c1mdata6719 undefined 03fec966h can1 message data byte 6 register 19 c1mdata619 undefined 03fec967h can1 message data byte 7 register 19 c1mdata719 undefined 03fec968h can1 message data length code register 19 c1mdlc19 0000xxxxb 03fec969h can1 message configurat ion register 19 c1mconf19 undefined 03fec96ah c1midl19 undefined 03fec96ch can1 message id register 19 c1midh19 undefined 03fec96eh can1 message control register 19 c1mctrl19 r/w 00x00000 000xx000b chapter 15 can controller 616 user?s manual u17830ee1v0um00 (29/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec980h can1 message data byte 01 register 20 c1mdata0120 undefined 03fec980h can1 message data byte 0 register 20 c1mdata020 undefined 03fec981h can1 message data byte 1 register 20 c1mdata120 undefined 03fec982h can1 message data byte 23 register 20 c1mdata2320 undefined 03fec982h can1 message data byte 2 register 20 c1mdata220 undefined 03fec983h can1 message data byte 3 register 20 c1mdata320 undefined 03fec984h can1 message data byte 45 register 20 c1mdata4520 undefined 03fec984h can1 message data byte 4 register 20 c1mdata420 undefined 03fec985h can1 message data byte 5 register 20 c1mdata520 undefined 03fec986h can1 message data byte 67 register 20 c1mdata6720 undefined 03fec986h can1 message data byte 6 register 20 c1mdata620 undefined 03fec987h can1 message data byte 7 register 20 c1mdata720 undefined 03fec988h can1 message data length code register 20 c1mdlc20 0000xxxxb 03fec989h can1 message configurat ion register 20 c1mconf20 undefined 03fec98ah c1midl20 undefined 03fec98ch can1 message id register 20 c1midh20 undefined 03fec98eh can1 message control register 20 c1mctrl20 00x00000 000xx000b 03fec9a0h can1 message data byte 01 register 21 c1mdata0121 undefined 03fec9a0h can1 message data byte 0 register 21 c1mdata021 undefined 03fec9a1h can1 message data byte 1 register 21 c1mdata121 undefined 03fec9a2h can1 message data byte 23 register 21 c1mdata2321 undefined 03fec9a2h can1 message data byte 2 register 21 c1mdata221 undefined 03fec9a3h can1 message data byte 3 register 21 c1mdata321 undefined 03fec9a4h can1 message data byte 45 register 21 c1mdata4521 undefined 03fec9a4h can1 message data byte 4 register 21 c1mdata421 undefined 03fec9a5h can1 message data byte 5 register 21 c1mdata521 undefined 03fec9a6h can1 message data byte 67 register 21 c1mdata6721 undefined 03fec9a6h can1 message data byte 6 register 21 c1mdata621 undefined 03fec9a7h can1 message data byte 7 register 21 c1mdata721 undefined 03fec9a8h can1 message data length code register 21 c1mdlc21 0000xxxxb 03fec9a9h can1 message configur ation register 21 c1mconf21 undefined 03fec9aah c1midl21 undefined 03fec9ach can1 message id register 21 c1midh21 undefined 03fec9aeh can1 message control register 21 c1mctrl21 r/w 00x00000 000xx000b chapter 15 can controller 617 user?s manual u17830ee1v0um00 (30/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fec9c0h can1 message data byte 01 register 22 c1mdata0122 undefined 03fec9c0h can1 message data byte 0 register 22 c1mdata022 undefined 03fec9c1h can1 message data byte 1 register 22 c1mdata122 undefined 03fec9c2h can1 message data byte 23 register 22 c1mdata2322 undefined 03fec9c2h can1 message data byte 2 register 22 c1mdata222 undefined 03fec9c3h can1 message data byte 3 register 22 c1mdata322 undefined 03fec9c4h can1 message data byte 45 register 22 c1mdata4522 undefined 03fec9c4h can1 message data byte 4 register 22 c1mdata422 undefined 03fec9c5h can1 message data byte 5 register 22 c1mdata522 undefined 03fec9c6h can1 message data byte 67 register 22 c1mdata6722 undefined 03fec9c6h can1 message data byte 6 register 22 c1mdata622 undefined 03fec9c7h can1 message data byte 7 register 22 c1mdata722 undefined 03fec9c8h can1 message data length code register 22 c1mdlc22 0000xxxxb 03fec9c9h can1 message configur ation register 22 c1mconf22 undefined 03fec9cah c1midl22 undefined 03fec9cch can1 message id register 22 c1midh22 undefined 03fec9ceh can1 message control register 22 c1mctrl22 00x00000 000xx000b 03fec9e0h can1 message data byte 01 register 23 c1mdata0123 undefined 03fec9e0h can1 message data byte 0 register 23 c1mdata023 undefined 03fec9e1h can1 message data byte 1 register 23 c1mdata123 undefined 03fec9e2h can1 message data byte 23 register 23 c1mdata2323 undefined 03fec9e2h can1 message data byte 2 register 23 c1mdata223 undefined 03fec9e3h can1 message data byte 3 register 23 c1mdata323 undefined 03fec9e4h can1 message data byte 45 register 23 c1mdata4523 undefined 03fec9e4h can1 message data byte 4 register 23 c1mdata423 undefined 03fec9e5h can1 message data byte 5 register 23 c1mdata523 undefined 03fec9e6h can1 message data byte 67 register 23 c1mdata6723 undefined 03fec9e6h can1 message data byte 6 register 23 c1mdata623 undefined 03fec9e7h can1 message data byte 7 register 23 c1mdata723 undefined 03fec9e8h can1 message data length code register 23 c1mdlc23 0000xxxxb 03fec9e9h can1 message configur ation register 23 c1mconf23 undefined 03fec9eah c1midl23 undefined 03fec9ech can1 message id register 23 c1midh23 undefined 03fec9eeh can1 message control register 23 c1mctrl23 r/w 00x00000 000xx000b chapter 15 can controller 618 user?s manual u17830ee1v0um00 (31/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03feca00h can1 message data byte 01 register 24 c1mdata0124 undefined 03feca00h can1 message data byte 0 register 24 c1mdata024 undefined 03feca01h can1 message data byte 1 register 24 c1mdata124 undefined 03feca02h can1 message data byte 23 register 24 c1mdata2324 undefined 03feca02h can1 message data byte 2 register 24 c1mdata224 undefined 03feca03h can1 message data byte 3 register 24 c1mdata324 undefined 03feca04h can1 message data byte 45 register 24 c1mdata4524 undefined 03feca04h can1 message data byte 4 register 24 c1mdata424 undefined 03feca05h can1 message data byte 5 register 24 c1mdata524 undefined 03feca06h can1 message data byte 67 register 24 c1mdata6724 undefined 03feca06h can1 message data byte 6 register 24 c1mdata624 undefined 03feca07h can1 message data byte 7 register 24 c1mdata724 undefined 03feca08h can1 message data length code register 24 c1mdlc24 0000xxxxb 03feca09h can1 message configur ation register 24 c1mconf24 undefined 03feca0ah c1midl24 undefined 03feca0ch can1 message id register 24 c1midh24 undefined 03feca0eh can1 message control register 24 c1mctrl24 00x00000 000xx000b 03feca20h can1 message data byte 01 register 25 c1mdata0125 undefined 03feca20h can1 message data byte 0 register 25 c1mdata025 undefined 03feca21h can1 message data byte 1 register 25 c1mdata125 undefined 03feca22h can1 message data byte 23 register 25 c1mdata2325 undefined 03feca22h can1 message data byte 2 register 25 c1mdata225 undefined 03feca23h can1 message data byte 3 register 25 c1mdata325 undefined 03feca24h can1 message data byte 45 register 25 c1mdata4525 undefined 03feca24h can1 message data byte 4 register 25 c1mdata425 undefined 03feca25h can1 message data byte 5 register 25 c1mdata525 undefined 03feca26h can1 message data byte 67 register 25 c1mdata6725 undefined 03feca26h can1 message data byte 6 register 25 c1mdata625 undefined 03feca27h can1 message data byte 7 register 25 c1mdata725 undefined 03feca28h can1 message data length code register 25 c1mdlc25 0000xxxxb 03feca29h can1 message configur ation register 25 c1mconf25 undefined 03feca2ah c1midl25 undefined 03feca2ch can1 message id register 25 c1midh25 undefined 03feca2eh can1 message control register 25 c1mctrl25 r/w 00x00000 000xx000b chapter 15 can controller 619 user?s manual u17830ee1v0um00 (32/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03feca40h can1 message data byte 01 register 26 c1mdata0126 undefined 03feca40h can1 message data byte 0 register 26 c1mdata026 undefined 03feca41h can1 message data byte 1 register 26 c1mdata126 undefined 03feca42h can1 message data byte 23 register 26 c1mdata2326 undefined 03feca42h can1 message data byte 2 register 26 c1mdata226 undefined 03feca43h can1 message data byte 3 register 26 c1mdata326 undefined 03feca44h can1 message data byte 45 register 26 c1mdata4526 undefined 03feca44h can1 message data byte 4 register 26 c1mdata426 undefined 03feca45h can1 message data byte 5 register 26 c1mdata526 undefined 03feca46h can1 message data byte 67 register 26 c1mdata6726 undefined 03feca46h can1 message data byte 6 register 26 c1mdata626 undefined 03feca47h can1 message data byte 7 register 26 c1mdata726 undefined 03feca48h can1 message data length code register 26 c1mdlc26 0000xxxxb 03feca49h can1 message configur ation register 26 c1mconf26 undefined 03feca4ah c1midl26 undefined 03feca4ch can1 message id register 26 c1midh26 undefined 03feca4eh can1 message control register 26 c1mctrl26 00x00000 000xx000b 03feca60h can1 message data byte 01 register 27 c1mdata0127 undefined 03feca60h can1 message data byte 0 register 27 c1mdata027 undefined 03feca61h can1 message data byte 1 register 27 c1mdata127 undefined 03feca62h can1 message data byte 23 register 27 c1mdata2327 undefined 03feca62h can1 message data byte 2 register 27 c1mdata227 undefined 03feca63h can1 message data byte 3 register 27 c1mdata327 undefined 03feca64h can1 message data byte 45 register 27 c1mdata4527 undefined 03feca64h can1 message data byte 4 register 27 c1mdata427 undefined 03feca65h can1 message data byte 5 register 27 c1mdata527 undefined 03feca66h can1 message data byte 67 register 27 c1mdata6727 undefined 03feca66h can1 message data byte 6 register 27 c1mdata627 undefined 03feca67h can1 message data byte 7 register 27 c1mdata727 undefined 03feca68h can1 message data length code register 27 c1mdlc27 0000xxxxb 03feca69h can1 message configur ation register 27 c1mconf27 undefined 03feca6ah c1midl27 undefined 03feca6ch can1 message id register 27 c1midh27 undefined 03feca6eh can1 message control register 27 c1mctrl27 r/w 00x00000 000xx000b chapter 15 can controller 620 user?s manual u17830ee1v0um00 (33/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03feca80h can1 message data byte 01 register 28 c1mdata0128 undefined 03feca80h can1 message data byte 0 register 28 c1mdata028 undefined 03feca81h can1 message data byte 1 register 28 c1mdata128 undefined 03feca82h can1 message data byte 23 register 28 c1mdata2328 undefined 03feca82h can1 message data byte 2 register 28 c1mdata228 undefined 03feca83h can1 message data byte 3 register 28 c1mdata328 undefined 03feca84h can1 message data byte 45 register 28 c1mdata4528 undefined 03feca84h can1 message data byte 4 register 28 c1mdata428 undefined 03feca85h can1 message data byte 5 register 28 c1mdata528 undefined 03feca86h can1 message data byte 67 register 28 c1mdata6728 undefined 03feca86h can1 message data byte 6 register 28 c1mdata628 undefined 03feca87h can1 message data byte 7 register 28 c1mdata728 undefined 03feca88h can1 message data length code register 28 c1mdlc28 0000xxxxb 03feca89h can1 message configur ation register 28 c1mconf28 undefined 03feca8ah c1midl28 undefined 03feca8ch can1 message id register 28 c1midh28 undefined 03feca8eh can1 message control register 28 c1mctrl28 00x00000 000xx000b 03fecaa0h can1 message data byte 01 register 29 c1mdata0129 undefined 03fecaa0h can1 message data byte 0 register 29 c1mdata029 undefined 03fecaa1h can1 message data byte 1 register 29 c1mdata129 undefined 03fecaa2h can1 message data byte 23 register 29 c1mdata2329 undefined 03fecaa2h can1 message data byte 2 register 29 c1mdata229 undefined 03fecaa3h can1 message data byte 3 register 29 c1mdata329 undefined 03fecaa4h can1 message data byte 45 register 29 c1mdata4529 undefined 03fecaa4h can1 message data byte 4 register 29 c1mdata429 undefined 03fecaa5h can1 message data byte 5 register 29 c1mdata529 undefined 03fecaa6h can1 message data byte 67 register 29 c1mdata6729 undefined 03fecaa6h can1 message data byte 6 register 29 c1mdata629 undefined 03fecaa7h can1 message data byte 7 register 29 c1mdata729 undefined 03fecaa8h can1 message data length code register 29 c1mdlc29 0000xxxxb 03fecaa9h can1 message configurat ion register 29 c1mconf29 undefined 03fecaaah c1midl29 undefined 03fecaach can1 message id register 29 c1midh29 undefined 03fecaaeh can1 message control register 29 c1mctrl29 r/w 00x00000 000xx000b chapter 15 can controller 621 user?s manual u17830ee1v0um00 (34/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecac0h can1 message data byte 01 register 30 c1mdata0130 undefined 03fecac0h can1 message data byte 0 register 30 c1mdata030 undefined 03fecac1h can1 message data byte 1 register 30 c1mdata130 undefined 03fecac2h can1 message data byte 23 register 30 c1mdata2330 undefined 03fecac2h can1 message data byte 2 register 30 c1mdata230 undefined 03fecac3h can1 message data byte 3 register 30 c1mdata330 undefined 03fecac4h can1 message data byte 45 register 30 c1mdata4530 undefined 03fecac4h can1 message data byte 4 register 30 c1mdata430 undefined 03fecac5h can1 message data byte 5 register 30 c1mdata530 undefined 03fecac6h can1 message data byte 67 register 30 c1mdata6730 undefined 03fecac6h can1 message data byte 6 register 30 c1mdata630 undefined 03fecac7h can1 message data byte 7 register 30 c1mdata730 undefined 03fecac8h can1 message data length code register 30 c1mdlc30 0000xxxxb 03fecac9h can1 message configur ation register 30 c1mconf30 undefined 03fecacah c1midl30 undefined 03fecacch can1 message id register 30 c1midh30 undefined 03fecaceh can1 message control register 30 c1mctrl30 00x00000 000xx000b 03fecae0h can1 message data byte 01 register 31 c1mdata0131 undefined 03fecae0h can1 message data byte 0 register 31 c1mdata031 undefined 03fecae1h can1 message data byte 1 register 31 c1mdata131 undefined 03fecae2h can1 message data byte 23 register 31 c1mdata2331 undefined 03fecae2h can1 message data byte 2 register 31 c1mdata231 undefined 03fecae3h can1 message data byte 3 register 31 c1mdata331 undefined 03fecae4h can1 message data byte 45 register 31 c1mdata4531 undefined 03fecae4h can1 message data byte 4 register 31 c1mdata431 undefined 03fecae5h can1 message data byte 5 register 31 c1mdata531 undefined 03fecae6h can1 message data byte 67 register 31 c1mdata6731 undefined 03fecae6h can1 message data byte 6 register 31 c1mdata631 undefined 03fecae7h can1 message data byte 7 register 31 c1mdata731 undefined 03fecae8h can1 message data length code register 31 c1mdlc31 0000xxxx 03fecae9h can1 message configurat ion register 31 c1mconf31 undefined 03fecaeah c1midl31 undefined 03fecaech can1 message id register 31 c1midh31 undefined 03fecaeeh can1 message control register 31 c1mctrl31 r/w 00x00000 000xx000b chapter 15 can controller 622 user?s manual u17830ee1v0um00 (35/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecc00h can2 global control register c2gmctrl r/w ? ? 0000h 03fecc02h can2 global clock se lect register c2gmcs r/w ? ? 0fh 03fecc06h can2 global bl ock transmission control register c2gmabt r/w ? ? 0000h 03fecc08h can2 global blo ck transmission delay setting register c2gmabtd r/w ? ? 00h 03fecc40h c2mask1l 03fecc42h can2 module mask 1 register c2mask1h r/w ? ? undefined 03fecc44h c2mask2l 03fecc46h can2 module mask 2 register c2mask2h r/w ? ? undefined 03fecc48h c2mask3l 03fecc4ah can2 module mask 3 register c2mask3h r/w ? ? undefined 03fecc4ch c2mask4l 03fecc4eh can2 module mask 4 register c2mask4h r/w ? ? undefined 03fecc50h can2 module control register c2ctrl r/w ? ? 0000h 03fecc52h can2 module last error information register c2lec r/w ? ? 00h 03fecc53h can2 module information register c2info r ? ? 00h 03fecc54h can2 module error counter register c2erc r ? ? 0000h 03fecc56h can2 module interrupt enable register c2ie r/w ? ? 0000h 03fecc58h can2 module interrupt status register c2ints r/w ? ? 0000h 03fecc5ah can2 module bit rate prescaler register c2brp r/w ? ? ffh 03fecc5ch can2 module bit rate register c2btr r/w ? ? 370fh 03fecc5eh can2 module last in-pointer register c2lipt r ? ? undefined 03fecc60h can2 module receive hi story list register c2rgpt r/w ? ? xx02h 03fecc62h can2 module last out-pointer register c2lopt r ? ? undefined 03fecc64h can2 module transmit history list register c2tgpt r/w ? ? xx02h 03fecc66h can2 module time stamp register c2ts r/w ? ? 0000h chapter 15 can controller 623 user?s manual u17830ee1v0um00 (36/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecd00h can2 message data byte 01 register 00 c2mdata0100 undefined 03fecd00h can2 message data byte 0 register 00 c2mdata000 undefined 03fecd01h can2 message data byte 1 register 00 c2mdata100 undefined 03fecd02h can2 message data byte 23 register 00 c2mdata2300 undefined 03fecd02h can2 message data byte 2 register 00 c2mdata200 undefined 03fecd03h can2 message data byte 3 register 00 c2mdata300 undefined 03fecd04h can2 message data byte 45 register 00 c2mdata4500 undefined 03fecd04h can2 message data byte 4 register 00 c2mdata400 undefined 03fecd05h can2 message data byte 5 register 00 c2mdata500 undefined 03fecd06h can2 message data byte 67 register 00 c2mdata6700 undefined 03fecd06h can2 message data byte 6 register 00 c2mdata600 undefined 03fecd07h can2 message data byte 7 register 00 c2mdata700 undefined 03fecd08h can2 message data length code register 00 c2mdlc00 0000xxxxb 03fecd09h can2 message configur ation register 00 c2mconf00 undefined 03fecd0ah c2midl00 undefined 03fecd0ch can2 message id register 00 c2midh00 undefined 03fecd0eh can2 message control register 00 c2mctrl00 00x00000 000xx000b 03fecd20h can2 message data byte 01 register 01 c2mdata0101 undefined 03fecd20h can2 message data byte 0 register 01 c2mdata001 undefined 03fecd21h can2 message data byte 1 register 01 c2mdata101 undefined 03fecd22h can2 message data byte 23 register 01 c2mdata2301 undefined 03fecd22h can2 message data byte 2 register 01 c2mdata201 undefined 03fecd23h can2 message data byte 3 register 01 c2mdata301 undefined 03fecd24h can2 message data byte 45 register 01 c2mdata4501 undefined 03fecd24h can2 message data byte 4 register 01 c2mdata401 undefined 03fecd25h can2 message data byte 5 register 01 c2mdata501 undefined 03fecd26h can2 message data byte 67 register 01 c2mdata6701 undefined 03fecd26h can2 message data byte 6 register 01 c2mdata601 undefined 03fecd27h can2 message data byte 7 register 01 c2mdata701 undefined 03fecd28h can2 message data length code register 01 c2mdlc01 0000xxxxb 03fecd29h can2 message register 01 c2mconf01 undefined 03fecd2ah c2midl01 undefined 03fecd2ch can2 message id register 01 c2midh01 undefined 03fecd2eh can2 message control register 01 c2mctrl01 r/w 00x00000 000xx000b chapter 15 can controller 624 user?s manual u17830ee1v0um00 (37/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecd40h can2 message data byte 01 register 02 c2mdata0102 undefined 03fecd40h can2 message data byte 0 register 02 c2mdata002 undefined 03fecd41h can2 message data byte 1 register 02 c2mdata102 undefined 03fecd42h can2 message data byte 23 register 02 c2mdata2302 undefined 03fecd42h can2 message data byte 2 register 02 c2mdata202 undefined 03fecd43h can2 message data byte 3 register 02 c2mdata302 undefined 03fecd44h can2 message data byte 45 register 02 c2mdata4502 undefined 03fecd44h can2 message data byte 4 register 02 c2mdata402 undefined 03fecd45h can2 message data byte 5 register 02 c2mdata502 undefined 03fecd46h can2 message data byte 67 register 02 c2mdata6702 undefined 03fecd46h can2 message data byte 6 register 02 c2mdata602 undefined 03fecd47h can2 message data byte 7 register 02 c2mdata702 undefined 03fecd48h can2 message data length code register 02 c2mdlc02 0000xxxxb 03fecd49h can2 message configur ation register 02 c2mconf02 undefined 03fecd4ah c2midl02 undefined 03fecd4ch can2 message id register 02 c2midh02 undefined 03fecd4eh can2 message control register 02 c2mctrl02 00x00000 000xx000b 03fecd60h can2 message data byte 01 register 03 c2mdata0103 undefined 03fecd60h can2 message data byte 0 register 03 c2mdata003 undefined 03fecd61h can2 message data byte 1 register 03 c2mdata103 undefined 03fecd62h can2 message data byte 23 register 03 c2mdata2303 undefined 03fecd62h can2 message data byte 2 register 03 c2mdata203 undefined 03fecd63h can2 message data byte 3 register 03 c2mdata303 undefined 03fecd64h can2 message data byte 45 register 03 c2mdata4503 undefined 03fecd64h can2 message data byte 4 register 03 c2mdata403 undefined 03fecd65h can2 message data byte 5 register 03 c2mdata503 undefined 03fecd66h can2 message data byte 67 register 03 c2mdata6703 undefined 03fecd66h can2 message data byte 6 register 03 c2mdata603 undefined 03fecd67h can2 message data byte 7 register 03 c2mdata703 undefined 03fecd68h can2 message data length code register 03 c2mdlc03 0000xxxxb 03fecd69h can2 message configur ation register 03 c2mconf03 undefined 03fecd6ah c2midl03 undefined 03fecd6ch can2 message id register 03 c2midh03 undefined 03fecd6eh can2 message control register 03 c2mctrl03 r/w 00x00000 000xx000b chapter 15 can controller 625 user?s manual u17830ee1v0um00 (38/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecd80h can2 message data byte 01 register 04 c2mdata0104 undefined 03fecd80h can2 message data byte 0 register 04 c2mdata004 undefined 03fecd81h can2 message data byte 1 register 04 c2mdata104 undefined 03fecd82h can2 message data byte 23 register 04 c2mdata2304 undefined 03fecd82h can2 message data byte 2 register 04 c2mdata204 undefined 03fecd83h can2 message data byte 3 register 04 c2mdata304 undefined 03fecd84h can2 message data byte 45 register 04 c2mdata4504 undefined 03fecd84h can2 message data byte 4 register 04 c2mdata404 undefined 03fecd85h can2 message data byte 5 register 04 c2mdata504 undefined 03fecd86h can2 message data byte 67 register 04 c2mdata6704 undefined 03fecd86h can2 message data byte 6 register 04 c2mdata604 undefined 03fecd87h can2 message data byte 7 register 04 c2mdata704 undefined 03fecd88h can2 message data length code register 04 c2mdlc04 0000xxxxb 03fecd89h can2 message configur ation register 04 c2mconf04 undefined 03fecd8ah c2midl04 undefined 03fecd8ch can2 message id register 04 c2midh04 undefined 03fecd8eh can2 message control register 04 c2mctrl04 00x00000 000xx000b 03fecda0h can2 message data byte 01 register 05 c2mdata0105 undefined 03fecda0h can2 message data byte 0 register 05 c2mdata005 undefined 03fecda1h can2 message data byte 1 register 05 c2mdata105 undefined 03fecda2h can2 message data byte 23 register 05 c2mdata2305 undefined 03fecda2h can2 message data byte 2 register 05 c2mdata205 undefined 03fecda3h can2 message data byte 3 register 05 c2mdata305 undefined 03fecda4h can2 message data byte 45 register 05 c2mdata4505 undefined 03fecda4h can2 message data byte 4 register 05 c2mdata405 undefined 03fecda5h can2 message data byte 5 register 05 c2mdata505 undefined 03fecda6h can2 message data byte 67 register 05 c2mdata6705 undefined 03fecda6h can2 message data byte 6 register 05 c2mdata605 undefined 03fecda7h can2 message data byte 7 register 05 c2mdata705 undefined 03fecda8h can2 message data length code register 05 c2mdlc05 0000xxxxb 03fecda9h can2 message configur ation register 05 c2mconf05 undefined 03fecdaah c2midl05 undefined 03fecdach can2 message id register 05 c2midh05 undefined 03fecdaeh can2 message control register 05 c2mctrl05 r/w 00x00000 000xx000b chapter 15 can controller 626 user?s manual u17830ee1v0um00 (39/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecdc0h can2 message data byte 01 register 06 c2mdata0106 undefined 03fecdc0h can2 message data byte 0 register 06 c2mdata006 undefined 03fecdc1h can2 message data byte 1 register 06 c2mdata106 undefined 03fecdc2h can2 message data byte 23 register 06 c2mdata2306 undefined 03fecdc2h can2 message data byte 2 register 06 c2mdata206 undefined 03fecdc3h can2 message data byte 3 register 06 c2mdata306 undefined 03fecdc4h can2 message data byte 45 register 06 c2mdata4506 undefined 03fecdc4h can2 message data byte 4 register 06 c2mdata406 undefined 03fecdc5h can2 message data byte 5 register 06 c2mdata506 undefined 03fecdc6h can2 message data byte 67 register 06 c2mdata6706 undefined 03fecdc6h can2 message data byte 6 register 06 c2mdata606 undefined 03fecdc7h can2 message data byte 7 register 06 c2mdata706 undefined 03fecdc8h can2 message data length code register 06 c2mdlc06 0000xxxxb 03fecdc9h can2 message configur ation register 06 c2mconf06 undefined 03fecdcah c2midl06 undefined 03fecdcch can2 message id register 06 c2midh06 undefined 03fecdceh can2 message control register 06 c2mctrl06 00x00000 000xx000b 03fecde0h can2 message data byte 01 register 07 c2mdata0107 undefined 03fecde0h can2 message data byte 0 register 07 c2mdata007 undefined 03fecde1h can2 message data byte 1 register 07 c2mdata107 undefined 03fecde2h can2 message data byte 23 register 07 c2mdata2307 undefined 03fecde2h can2 message data byte 2 register 07 c2mdata207 undefined 03fecde3h can2 message data byte 3 register 07 c2mdata307 undefined 03fecde4h can2 message data byte 45 register 07 c2mdata4507 undefined 03fecde4h can2 message data byte 4 register 07 c2mdata407 undefined 03fecde5h can2 message data byte 5 register 07 c2mdata507 undefined 03fecde6h can2 message data byte 67 register 07 c2mdata6707 undefined 03fecde6h can2 message data byte 6 register 07 c2mdata607 undefined 03fecde7h can2 message data byte 7 register 07 c2mdata707 undefined 03fecde8h can2 message data length code register 07 c2mdlc07 0000xxxxb 03fecde9h can2 message configur ation register 07 c2mconf07 undefined 03fecdeah c2midl07 undefined 03fecdech can2 message id register 07 c2midh07 undefined 03fecdeeh can2 message control register 07 c2mctrl07 r/w 00x00000 000xx000b chapter 15 can controller 627 user?s manual u17830ee1v0um00 (40/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fece00h can2 message data byte 01 register 08 c2mdata0108 undefined 03fece00h can2 message data byte 0 register 08 c2mdata008 undefined 03fece01h can2 message data byte 1 register 08 c2mdata108 undefined 03fece02h can2 message data byte 23 register 08 c2mdata2308 undefined 03fece02h can2 message data byte 2 register 08 c2mdata208 undefined 03fece03h can2 message data byte 3 register 08 c2mdata308 undefined 03fece04h can2 message data byte 45 register 08 c2mdata4508 undefined 03fece04h can2 message data byte 4 register 08 c2mdata408 undefined 03fece05h can2 message data byte 5 register 08 c2mdata508 undefined 03fece06h can2 message data byte 67 register 08 c2mdata6708 undefined 03fece06h can2 message data byte 6 register 08 c2mdata608 undefined 03fece07h can2 message data byte 7 register 08 c2mdata708 undefined 03fece08h can2 message data length code register 08 c2mdlc08 0000xxxxb 03fece09h can2 message configur ation register 08 c2mconf08 undefined 03fece0ah c2midl08 undefined 03fece0ch can2 message id register 08 c2midh08 undefined 03fece0eh can2 message control register 08 c2mctrl08 00x00000 000xx000b 03fece20h can2 message data byte 01 register 09 c2mdata0109 undefined 03fece20h can2 message data byte 0 register 09 c2mdata009 undefined 03fece21h can2 message data byte 1 register 09 c2mdata109 undefined 03fece22h can2 message data byte 23 register 09 c2mdata2309 undefined 03fece22h can2 message data byte 2 register 09 c2mdata209 undefined 03fece23h can2 message data byte 3 register 09 c2mdata309 undefined 03fece24h can2 message data byte 45 register 09 c2mdata4509 undefined 03fece24h can2 message data byte 4 register 09 c2mdata409 undefined 03fece25h can2 message data byte 5 register 09 c2mdata509 undefined 03fece26h can2 message data byte 67 register 09 c2mdata6709 undefined 03fece26h can2 message data byte 6 register 09 c2mdata609 undefined 03fece27h can2 message data byte 7 register 09 c2mdata709 undefined 03fece28h can2 message data length code register 09 c2mdlc09 0000xxxxb 03fece29h can2 message configur ation register 09 c2mconf09 undefined 03fece2ah c2midl09 undefined 03fece2ch can2 message id register 09 c2midh09 undefined 03fece2eh can2 message control register 09 c2mctrl09 r/w 00x00000 000xx000b chapter 15 can controller 628 user?s manual u17830ee1v0um00 (41/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fece40h can2 message data byte 01 register 10 c2mdata0110 undefined 03fece40h can2 message data byte 0 register 10 c2mdata010 undefined 03fece41h can2 message data byte 1 register 10 c2mdata110 undefined 03fece42h can2 message data byte 23 register 10 c2mdata2310 undefined 03fece42h can2 message data byte 2 register 10 c2mdata210 undefined 03fece43h can2 message data byte 3 register 10 c2mdata310 undefined 03fece44h can2 message data byte 45 register 10 c2mdata4510 undefined 03fece44h can2 message data byte 4 register 10 c2mdata410 undefined 03fece45h can2 message data byte 5 register 10 c2mdata510 undefined 03fece46h can2 message data byte 67 register 10 c2mdata6710 undefined 03fece46h can2 message data byte 6 register 10 c2mdata610 undefined 03fece47h can2 message data byte 7 register 10 c2mdata710 undefined 03fece48h can2 message data length code register 10 c2mdlc10 0000xxxxb 03fece49h can2 message configur ation register 10 c2mconf10 undefined 03fece4ah c2midl10 undefined 03fece4ch can2 message id register 10 c2midh10 undefined 03fece4eh can2 message control register 10 c2mctrl10 00x00000 000xx000b 03fece60h can2 message data byte 01 register 11 c2mdata0111 undefined 03fece60h can2 message data byte 0 register 11 c2mdata011 undefined 03fece61h can2 message data byte 1 register 11 c2mdata111 undefined 03fece62h can2 message data byte 23 register 11 c2mdata2311 undefined 03fece62h can2 message data byte 2 register 11 c2mdata211 undefined 03fece63h can2 message data byte 3 register 11 c2mdata311 undefined 03fece64h can2 message data byte 45 register 11 c2mdata4511 undefined 03fece64h can2 message data byte 4 register 11 c2mdata411 undefined 03fece65h can2 message data byte 5 register 11 c2mdata511 undefined 03fece66h can2 message data byte 67 register 11 c2mdata6711 undefined 03fece66h can2 message data byte 6 register 11 c2mdata611 undefined 03fece67h can2 message data byte 7 register 11 c2mdata711 undefined 03fece68h can2 message data length code register 11 c2mdlc11 0000xxxxb 03fece69h can2 message configur ation register 11 c2mconf11 undefined 03fece6ah c2midl11 undefined 03fece6ch can2 message id register 11 c2midh11 undefined 03fece6eh can2 message control register 11 c2mctrl11 r/w 00x00000 000xx000b chapter 15 can controller 629 user?s manual u17830ee1v0um00 (42/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fece80h can2 message data byte 01 register 12 c2mdata0112 undefined 03fece80h can2 message data byte 0 register 12 c2mdata012 undefined 03fece81h can2 message data byte 1 register 12 c2mdata112 undefined 03fece82h can2 message data byte 23 register 12 c2mdata2312 undefined 03fece82h can2 message data byte 2 register 12 c2mdata212 undefined 03fece83h can2 message data byte 3 register 12 c2mdata312 undefined 03fece84h can2 message data byte 45 register 12 c2mdata4512 undefined 03fece84h can2 message data byte 4 register 12 c2mdata412 undefined 03fece85h can2 message data byte 5 register 12 c2mdata512 undefined 03fece86h can2 message data byte 67 register 12 c2mdata6712 undefined 03fece86h can2 message data byte 6 register 12 c2mdata612 undefined 03fece87h can2 message data byte 7 register 12 c2mdata712 undefined 03fece88h can2 message data length code register 12 c2mdlc12 0000xxxxb 03fece89h can2 message configur ation register 12 c2mconf12 undefined 03fece8ah c2midl12 undefined 03fece8ch can2 message id register 12 c2midh12 undefined 03fece8eh can2 message control register 12 c2mctrl12 00x00000 000xx000b 03fecea0h can2 message data byte 01 register 13 c2mdata0113 undefined 03fecea0h can2 message data byte 0 register 13 c2mdata013 undefined 03fecea1h can2 message data byte 1 register 13 c2mdata113 undefined 03fecea2h can2 message data byte 23 register 13 c2mdata2313 undefined 03fecea2h can2 message data byte 2 register 13 c2mdata213 undefined 03fecea3h can2 message data byte 3 register 13 c2mdata313 undefined 03fecea4h can2 message data byte 45 register 13 c2mdata4513 undefined 03fecea4h can2 message data byte 4 register 13 c2mdata413 undefined 03fecea5h can2 message data byte 5 register 13 c2mdata513 undefined 03fecea6h can2 message data byte 67 register 13 c2mdata6713 undefined 03fecea6h can2 message data byte 6 register 13 c2mdata613 undefined 03fecea7h can2 message data byte 7 register 13 c2mdata713 undefined 03fecee8h can2 message data length code register 13 c2mdlc13 0000xxxxb 03fecea9h can2 message configurat ion register 13 c2mconf13 undefined 03feceaah c2midl13 undefined 03feceach can2 message id register 13 c2midh13 undefined 03feceaeh can2 message control register 13 c2mctrl13 r/w 00x00000 000xx000b chapter 15 can controller 630 user?s manual u17830ee1v0um00 (43/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecec0h can2 message data byte 01 register 14 c2mdata0114 undefined 03fecec0h can2 message data byte 0 register 14 c2mdata014 undefined 03fecec1h can2 message data byte 1 register 14 c2mdata114 undefined 03fecec2h can2 message data byte 23 register 14 c2mdata2314 undefined 03fecec2h can2 message data byte 2 register 14 c2mdata214 undefined 03fecec3h can2 message data byte 3 register 14 c2mdata314 undefined 03fecec4h can2 message data byte 45 register 14 c2mdata4514 undefined 03fecec4h can2 message data byte 4 register 14 c2mdata414 undefined 03fecec5h can2 message data byte 5 register 14 c2mdata514 undefined 03fecec6h can2 message data byte 67 register 14 c2mdata6714 undefined 03fecec6h can2 message data byte 6 register 14 c2mdata614 undefined 03fecec7h can2 message data byte 7 register 14 c2mdata714 undefined 03fecec8h can2 message data length code register 14 c2mdlc14 0000xxxxb 03fecec9h can2 message configur ation register 14 c2mconf14 undefined 03fececah c2midl14 undefined 03fececch can2 message id register 14 c2midh14 undefined 03fececeh can2 message control register 14 c2mctrl14 00x00000 000xx000b 03fecee0h can2 message data byte 01 register 15 c2mdata0115 undefined 03fecee0h can2 message data byte 0 register 15 c2mdata015 undefined 03fecee1h can2 message data byte 1 register 15 c2mdata115 undefined 03fecee2h can2 message data byte 23 register 15 c2mdata2315 undefined 03fecee2h can2 message data byte 2 register 15 c2mdata215 undefined 03fecee3h can2 message data byte 3 register 15 c2mdata315 undefined 03fecee4h can2 message data byte 45 register 15 c2mdata4515 undefined 03fecee4h can2 message data byte 4 register 15 c2mdata415 undefined 03fecee5h can2 message data byte 5 register 15 c2mdata515 undefined 03fecee6h can2 message data byte 67 register 15 c2mdata6715 undefined 03fecee6h can2 message data byte 6 register 15 c2mdata615 undefined 03fecee7h can2 message data byte 7 register 15 c2mdata715 undefined 03fecee8h can2 message data length code register 15 c2mdlc15 0000xxxxb 03fecee9h can2 message configurat ion register 15 c2mconf15 undefined 03feceeah c2midl15 undefined 03feceech can2 message id register 15 c2midh15 undefined 03feceeeh can2 message control register 15 c2mctrl15 r/w 00x00000 000xx000b chapter 15 can controller 631 user?s manual u17830ee1v0um00 (44/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecf00h can2 message data byte 01 register 16 c2mdata0116 undefined 03fecf00h can2 message data byte 0 register 16 c2mdata016 undefined 03fecf01h can2 message data byte 1 register 16 c2mdata116 undefined 03fecf02h can2 message data byte 23 register 16 c2mdata2316 undefined 03fecf02h can2 message data byte 2 register 16 c2mdata216 undefined 03fecf03h can2 message data byte 3 register 16 c2mdata316 undefined 03fecf04h can2 message data byte 45 register 16 c2mdata4516 undefined 03fecf04h can2 message data byte 4 register 16 c2mdata416 undefined 03fecf05h can2 message data byte 5 register 16 c2mdata516 undefined 03fecf06h can2 message data byte 67 register 16 c2mdata6716 undefined 03fecf06h can2 message data byte 6 register 16 c2mdata616 undefined 03fecf07h can2 message data byte 7 register 16 c2mdata716 undefined 03fecf08h can2 message data length code register 16 c2mdlc16 0000xxxxb 03fecf09h can2 message configur ation register 16 c2mconf16 undefined 03fecf0ah c2midl16 undefined 03fecf0ch can2 message id register 16 c2midh16 undefined 03fecf0eh can2 message control register 16 c2mctrl16 00x00000 000xx000b 03fecf20h can2 message data byte 01 register 17 c2mdata0117 undefined 03fecf20h can2 message data byte 0 register 17 c2mdata017 undefined 03fecf21h can2 message data byte 1 register 17 c2mdata117 undefined 03fecf22h can2 message data byte 23 register 17 c2mdata2317 undefined 03fecf22h can2 message data byte 2 register 17 c2mdata217 undefined 03fecf23h can2 message data byte 3 register 17 c2mdata317 undefined 03fecf24h can2 message data byte 45 register 17 c2mdata4517 undefined 03fecf24h can2 message data byte 4 register 17 c2mdata417 undefined 03fecf25h can2 message data byte 5 register 17 c2mdata517 undefined 03fecf26h can2 message data byte 67 register 17 c2mdata6717 undefined 03fecf26h can2 message data byte 6 register 17 c2mdata617 undefined 03fecf27h can2 message data byte 7 register 17 c2mdata717 undefined 03fecf28h can2 message data length code register 17 c2mdlc17 0000xxxxb 03fecf29h can2 message configur ation register 17 c2mconf17 undefined 03fecf2ah c2midl17 undefined 03fecf2ch can2 message id register 17 c2midh17 undefined 03fecf2eh can2 message control register 17 c2mctrl17 r/w 00x00000 000xx000b chapter 15 can controller 632 user?s manual u17830ee1v0um00 (45/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecf40h can2 message data byte 01 register 18 c2mdata0118 undefined 03fecf40h can2 message data byte 0 register 18 c2mdata018 undefined 03fecf41h can2 message data byte 1 register 18 c2mdata118 undefined 03fecf42h can2 message data byte 23 register 18 c2mdata2318 undefined 03fecf42h can2 message data byte 2 register 18 c2mdata218 undefined 03fecf43h can2 message data byte 3 register 18 c2mdata318 undefined 03fecf44h can2 message data byte 45 register 18 c2mdata4518 undefined 03fecf44h can2 message data byte 4 register 18 c2mdata418 undefined 03fecf45h can2 message data byte 5 register 18 c2mdata518 undefined 03fecf46h can2 message data byte 67 register 18 c2mdata6718 undefined 03fecf46h can2 message data byte 6 register 18 c2mdata618 undefined 03fecf47h can2 message data byte 7 register 18 c2mdata718 undefined 03fecf48h can2 message data length code register 18 c2mdlc18 0000xxxxb 03fecf49h can2 message configur ation register 18 c2mconf18 undefined 03fecf4ah c2midl18 undefined 03fecf4ch can2 message id register 18 c2midh18 undefined 03fecf4eh can2 message control register 18 c2mctrl18 00x00000 000xx000b 03fecf60h can2 message data byte 01 register 19 c2mdata0119 undefined 03fecf60h can2 message data byte 0 register 19 c2mdata019 undefined 03fecf61h can2 message data byte 1 register 19 c2mdata119 undefined 03fecf62h can2 message data byte 23 register 19 c2mdata2319 undefined 03fecf62h can2 message data byte 2 register 19 c2mdata219 undefined 03fecf63h can2 message data byte 3 register 19 c2mdata319 undefined 03fecf64h can2 message data byte 45 register 19 c2mdata4519 undefined 03fecf64h can2 message data byte 4 register 19 c2mdata419 undefined 03fecf65h can2 message data byte 5 register 19 c2mdata519 undefined 03fecf66h can2 message data byte 67 register 19 c2mdata6719 undefined 03fecf66h can2 message data byte 6 register 19 c2mdata619 undefined 03fecf67h can2 message data byte 7 register 19 c2mdata719 undefined 03fecf68h can2 message data length code register 19 c2mdlc19 0000xxxxb 03fecf69h can2 message configur ation register 19 c2mconf19 undefined 03fecf6ah c2midl19 undefined 03fecf6ch can2 message id register 19 c2midh19 undefined 03fecf6eh can2 message control register 19 c2mctrl19 r/w 00x00000 000xx000b chapter 15 can controller 633 user?s manual u17830ee1v0um00 (46/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecf80h can2 message data byte 01 register 20 c2mdata0120 undefined 03fecf80h can2 message data byte 0 register 20 c2mdata020 undefined 03fecf81h can2 message data byte 1 register 20 c2mdata120 undefined 03fecf82h can2 message data byte 23 register 20 c2mdata2320 undefined 03fecf82h can2 message data byte 2 register 20 c2mdata220 undefined 03fecf83h can2 message data byte 3 register 20 c2mdata320 undefined 03fecf84h can2 message data byte 45 register 20 c2mdata4520 undefined 03fecf84h can2 message data byte 4 register 20 c2mdata420 undefined 03fecf85h can2 message data byte 5 register 20 c2mdata520 undefined 03fecf86h can2 message data byte 67 register 20 c2mdata6720 undefined 03fecf86h can2 message data byte 6 register 20 c2mdata620 undefined 03fecf87h can2 message data byte 7 register 20 c2mdata720 undefined 03fecf88h can2 message data length code register 20 c2mdlc20 0000xxxxb 03fecf89h can2 message configur ation register 20 c2mconf20 undefined 03fecf8ah c2midl20 undefined 03fecf8ch can2 message id register 20 c2midh20 undefined 03fecf8eh can2 message control register 20 c2mctrl20 00x00000 000xx000b 03fecfa0h can2 message data byte 01 register 21 c2mdata0121 undefined 03fecfa0h can2 message data byte 0 register 21 c2mdata021 undefined 03fecfa1h can2 message data byte 1 register 21 c2mdata121 undefined 03fecfa2h can2 message data byte 23 register 21 c2mdata2321 undefined 03fecfa2h can2 message data byte 2 register 21 c2mdata221 undefined 03fecfa3h can2 message data byte 3 register 21 c2mdata321 undefined 03fecfa4h can2 message data byte 45 register 21 c2mdata4521 undefined 03fecfa4h can2 message data byte 4 register 21 c2mdata421 undefined 03fecfa5h can2 message data byte 5 register 21 c2mdata521 undefined 03fecfa6h can2 message data byte 67 register 21 c2mdata6721 undefined 03fecfa6h can2 message data byte 6 register 21 c2mdata621 undefined 03fecfa7h can2 message data byte 7 register 21 c2mdata721 undefined 03fecfa8h can2 message data length code register 21 c2mdlc21 0000xxxxb 03fecfa9h can2 message configur ation register 21 c2mconf21 undefined 03fecfaah c2midl21 undefined 03fecfach can2 message id register 21 c2midh21 undefined 03fecfaeh can2 message control register 21 c2mctrl21 r/w 00x00000 000xx000b chapter 15 can controller 634 user?s manual u17830ee1v0um00 (47/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fecfc0h can2 message data byte 01 register 22 c2mdata0122 undefined 03fecfc0h can2 message data byte 0 register 22 c2mdata022 undefined 03fecfc1h can2 message data byte 1 register 22 c2mdata122 undefined 03fecfc2h can2 message data byte 23 register 22 c2mdata2322 undefined 03fecfc2h can2 message data byte 2 register 22 c2mdata222 undefined 03fecfc3h can2 message data byte 3 register 22 c2mdata322 undefined 03fecfc4h can2 message data byte 45 register 22 c2mdata4522 undefined 03fecfc4h can2 message data byte 4 register 22 c2mdata422 undefined 03fecfc5h can2 message data byte 5 register 22 c2mdata522 undefined 03fecfc6h can2 message data byte 67 register 22 c2mdata6722 undefined 03fecfc6h can2 message data byte 6 register 22 c2mdata622 undefined 03fecfc7h can2 message data byte 7 register 22 c2mdata722 undefined 03fecfc8h can2 message data length code register 22 c2mdlc22 0000xxxxb 03fecfc9h can2 message configur ation register 22 c2mconf22 undefined 03fecfcah c2midl22 undefined 03fecfcch can2 message id register 22 c2midh22 undefined 03fecfceh can2 message control register 22 c2mctrl22 00x00000 000xx000b 03fecfe0h can2 message data byte 01 register 23 c2mdata0123 undefined 03fecfe0h can2 message data byte 0 register 23 c2mdata023 undefined 03fecfe1h can2 message data byte 1 register 23 c2mdata123 undefined 03fecfe2h can2 message data byte 23 register 23 c2mdata2323 undefined 03fecfe2h can2 message data byte 2 register 23 c2mdata223 undefined 03fecfe3h can2 message data byte 3 register 23 c2mdata323 undefined 03fecfe4h can2 message data byte 45 register 23 c2mdata4523 undefined 03fecfe4h can2 message data byte 4 register 23 c2mdata423 undefined 03fecfe5h can2 message data byte 5 register 23 c2mdata523 undefined 03fecfe6h can2 message data byte 67 register 23 c2mdata6723 undefined 03fecfe6h can2 message data byte 6 register 23 c2mdata623 undefined 03fecfe7h can2 message data byte 7 register 23 c2mdata723 undefined 03fecfe8h can2 message data length code register 23 c2mdlc23 0000xxxxb 03fecfe9h can2 message configur ation register 23 c2mconf23 undefined 03fecfeah c2midl23 undefined 03fecfech can2 message id register 23 c2midh23 undefined 03fecfeeh can2 message control register 23 c2mctrl23 r/w 00x00000 000xx000b chapter 15 can controller 635 user?s manual u17830ee1v0um00 (48/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed000h can2 message data byte 01 register 24 c2mdata0124 undefined 03fed000h can2 message data byte 0 register 24 c2mdata024 undefined 03fed001h can2 message data byte 1 register 24 c2mdata124 undefined 03fed002h can2 message data byte 23 register 24 c2mdata2324 undefined 03fed002h can2 message data byte 2 register 24 c2mdata224 undefined 03fed003h can2 message data byte 3 register 24 c2mdata324 undefined 03fed004h can2 message data byte 45 register 24 c2mdata4524 undefined 03fed004h can2 message data byte 4 register 24 c2mdata424 undefined 03fed005h can2 message data byte 5 register 24 c2mdata524 undefined 03fed006h can2 message data byte 67 register 24 c2mdata6724 undefined 03fed006h can2 message data byte 6 register 24 c2mdata624 undefined 03fed007h can2 message data byte 7 register 24 c2mdata724 undefined 03fed008h can2 message data length code register 24 c2mdlc24 0000xxxxb 03fed009h can2 message configurat ion register 24 c2mconf24 undefined 03fed00ah c2midl24 undefined 03fed00ch can2 message id register 24 c2midh24 undefined 03fed00eh can2 message control register 24 c2mctrl24 00x00000 000xx000b 03fed020h can2 message data byte 01 register 25 c2mdata0125 undefined 03fed020h can2 message data byte 0 register 25 c2mdata025 undefined 03fed021h can2 message data byte 1 register 25 c2mdata125 undefined 03fed022h can2 message data byte 23 register 25 c2mdata2325 undefined 03fed022h can2 message data byte 2 register 25 c2mdata225 undefined 03fed023h can2 message data byte 3 register 25 c2mdata325 undefined 03fed024h can2 message data byte 45 register 25 c2mdata4525 undefined 03fed024h can2 message data byte 4 register 25 c2mdata425 undefined 03fed025h can2 message data byte 5 register 25 c2mdata525 undefined 03fed026h can2 message data byte 67 register 25 c2mdata6725 undefined 03fed026h can2 message data byte 6 register 25 c2mdata625 undefined 03fed027h can2 message data byte 7 register 25 c2mdata725 undefined 03fed028h can2 message data length code register 25 c2mdlc25 0000xxxxb 03fed029h can2 message configurat ion register 25 c2mconf25 undefined 03fed02ah c2midl25 undefined 03fed02ch can2 message id register 25 c2midh25 undefined 03fed02eh can2 message control register 25 c2mctrl25 r/w 00x00000 000xx000b chapter 15 can controller 636 user?s manual u17830ee1v0um00 (49/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed040h can2 message data byte 01 register 26 c2mdata0126 undefined 03fed040h can2 message data byte 0 register 26 c2mdata026 undefined 03fed041h can2 message data byte 1 register 26 c2mdata126 undefined 03fed042h can2 message data byte 23 register 26 c2mdata2326 undefined 03fed042h can2 message data byte 2 register 26 c2mdata226 undefined 03fed043h can2 message data byte 3 register 26 c2mdata326 undefined 03fed044h can2 message data byte 45 register 26 c2mdata4526 undefined 03fed044h can2 message data byte 4 register 26 c2mdata426 undefined 03fed045h can2 message data byte 5 register 26 c2mdata526 undefined 03fed046h can2 message data byte 67 register 26 c2mdata6726 undefined 03fed046h can2 message data byte 6 register 26 c2mdata626 undefined 03fed047h can2 message data byte 7 register 26 c2mdata726 undefined 03fed048h can2 message data length code register 26 c2mdlc26 0000xxxxb 03fed049h can2 message configurat ion register 26 c2mconf26 undefined 03fed04ah c2midl26 undefined 03fed04ch can2 message id register 26 c2midh26 undefined 03fed04eh can2 message control register 26 c2mctrl26 00x00000 000xx000b 03fed060h can2 message data byte 01 register 27 c2mdata0127 undefined 03fed060h can2 message data byte 0 register 27 c2mdata027 undefined 03fed061h can2 message data byte 1 register 27 c2mdata127 undefined 03fed062h can2 message data byte 23 register 27 c2mdata2327 undefined 03fed062h can2 message data byte 2 register 27 c2mdata227 undefined 03fed063h can2 message data byte 3 register 27 c2mdata327 undefined 03fed064h can2 message data byte 45 register 27 c2mdata4527 undefined 03fed064h can2 message data byte 4 register 27 c2mdata427 undefined 03fed065h can2 message data byte 5 register 27 c2mdata527 undefined 03fed066h can2 message data byte 67 register 27 c2mdata6727 undefined 03fed066h can2 message data byte 6 register 27 c2mdata627 undefined 03fed067h can2 message data byte 7 register 27 c2mdata727 undefined 03fed068h can2 message data length code register 27 c2mdlc27 0000xxxxb 03fed069h can2 message configurat ion register 27 c2mconf27 undefined 03fed06ah c2midl27 undefined 03fed06ch can2 message id register 27 c2midh27 undefined 03fed06eh can2 message control register 27 c2mctrl27 r/w 00x00000 000xx000b chapter 15 can controller 637 user?s manual u17830ee1v0um00 (50/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed080h can2 message data byte 01 register 28 c2mdata0128 undefined 03fed080h can2 message data byte 0 register 28 c2mdata028 undefined 03fed081h can2 message data byte 1 register 28 c2mdata128 undefined 03fed082h can2 message data byte 23 register 28 c2mdata2328 undefined 03fed082h can2 message data byte 2 register 28 c2mdata228 undefined 03fed083h can2 message data byte 3 register 28 c2mdata328 undefined 03fed084h can2 message data byte 45 register 28 c2mdata4528 undefined 03fed084h can2 message data byte 4 register 28 c2mdata428 undefined 03fed085h can2 message data byte 5 register 28 c2mdata528 undefined 03fed086h can2 message data byte 67 register 28 c2mdata6728 undefined 03fed086h can2 message data byte 6 register 28 c2mdata628 undefined 03fed087h can2 message data byte 7 register 28 c2mdata728 undefined 03fed088h can2 message data length code register 28 c2mdlc28 0000xxxxb 03fed089h can2 message configurat ion register 28 c2mconf28 undefined 03fed08ah c2midl28 undefined 03fed08ch can2 message id register 28 c2midh28 undefined 03fed08eh can2 message control register 28 c2mctrl28 00x00000 000xx000b 03fed0a0h can2 message data byte 01 register 29 c2mdata0129 undefined 03fed0a0h can2 message data byte 0 register 29 c2mdata029 undefined 03fed0a1h can2 message data byte 1 register 29 c2mdata129 undefined 03fed0a2h can2 message data byte 23 register 29 c2mdata2329 undefined 03fed0a2h can2 message data byte 2 register 29 c2mdata229 undefined 03fed0a3h can2 message data byte 3 register 29 c2mdata329 undefined 03fed0a4h can2 message data byte 45 register 29 c2mdata4529 undefined 03fed0a4h can2 message data byte 4 register 29 c2mdata429 undefined 03fed0a5h can2 message data byte 5 register 29 c2mdata529 undefined 03fed0a6h can2 message data byte 67 register 29 c2mdata6729 undefined 03fed0a6h can2 message data byte 6 register 29 c2mdata629 undefined 03fed0a7h can2 message data byte 7 register 29 c2mdata729 undefined 03fed0a8h can2 message data length code register 29 c2mdlc29 0000xxxxb 03fed0a9h can2 message configur ation register 29 c2mconf29 undefined 03fed0aah c2midl29 undefined 03fed0ach can2 message id register 29 c2midh29 undefined 03fed0aeh can2 message control register 29 c2mctrl29 r/w 00x00000 000xx000b chapter 15 can controller 638 user?s manual u17830ee1v0um00 (51/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed0c0h can2 message data byte 01 register 30 c2mdata0130 undefined 03fed0c0h can2 message data byte 0 register 30 c2mdata030 undefined 03fed0c1h can2 message data byte 1 register 30 c2mdata130 undefined 03fed0c2h can2 message data byte 23 register 30 c2mdata2330 undefined 03fed0c2h can2 message data byte 2 register 30 c2mdata230 undefined 03fed0c3h can2 message data byte 3 register 30 c2mdata330 undefined 03fed0c4h can2 message data byte 45 register 30 c2mdata4530 undefined 03fed0c4h can2 message data byte 4 register 30 c2mdata430 undefined 03fed0c5h can2 message data byte 5 register 30 c2mdata530 undefined 03fed0c6h can2 message data byte 67 register 30 c2mdata6730 undefined 03fed0c6h can2 message data byte 6 register 30 c2mdata630 undefined 03fed0c7h can2 message data byte 7 register 30 c2mdata730 undefined 03fed0c8h can2 message data length code register 30 c2mdlc30 0000xxxxb 03fed0c9h can2 message configur ation register 30 c2mconf30 undefined 03fed0cah c2midl30 undefined 03fed0cch can2 message id register 30 c2midh30 undefined 03fed0ceh can2 message control register 30 c2mctrl30 00x00000 000xx000b 03fed0e0h can2 message data byte 01 register 31 c2mdata0131 undefined 03fed0e0h can2 message data byte 0 register 31 c2mdata031 undefined 03fed0e1h can2 message data byte 1 register 31 c2mdata131 undefined 03fed0e2h can2 message data byte 23 register 31 c2mdata2331 undefined 03fed0e2h can2 message data byte 2 register 31 c2mdata231 undefined 03fed0e3h can2 message data byte 3 register 31 c2mdata331 undefined 03fed0e4h can2 message data byte 45 register 31 c2mdata4531 undefined 03fed0e4h can2 message data byte 4 register 31 c2mdata431 undefined 03fed0e5h can2 message data byte 5 register 31 c2mdata531 undefined 03fed0e6h can2 message data byte 67 register 31 c2mdata6731 undefined 03fed0e6h can2 message data byte 6 register 31 c2mdata631 undefined 03fed0e7h can2 message data byte 7 register 31 c2mdata731 undefined 03fed0e8h can2 message data length code register 31 c2mdlc31 0000xxxx 03fed0e9h can2 message configur ation register 31 c2mconf31 undefined 03fed0eah c2midl31 undefined 03fed0ech can2 message id register 31 c2midh31 undefined 03fed0eeh can2 message control register 31 c2mctrl31 r/w 00x00000 000xx000b chapter 15 can controller 639 user?s manual u17830ee1v0um00 (52/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed200h can3 global control register c3gmctrl r/w ? ? 0000h 03fed202h can3 global clock se lect register c3gmcs r/w ? ? 0fh 03fed206h can3 global blo ck transmission control register c3gmabt r/w ? ? 0000h 03fed208h can3 global block transmission delay setting register c3gmabtd r/w ? ? 00h 03fed240h c3mask1l 03fed242h can3 module mask 1 register c3mask1h r/w ? ? undefined 03fed244h c3mask2l 03fed246h can3 module mask 2 register c3mask2h r/w ? ? undefined 03fed248h c3mask3l 03fed24ah can3 module mask 3 register c3mask3h r/w ? ? undefined 03fed24ch c3mask4l 03fed24eh can3 module mask 4 register c3mask4h r/w ? ? undefined 03fed250h can3 module control register c3ctrl r/w ? ? 0000h 03fed252h can3 module last error information register c3lec r/w ? ? 00h 03fed253h can3 module information register c3info r ? ? 00h 03fed254h can3 module error counter register c3erc r ? ? 0000h 03fed256h can3 module interrupt enable register c3ie r/w ? ? 0000h 03fed258h can3 module interrupt status register c3ints r/w ? ? 0000h 03fed25ah can3 module bit rate prescaler register c3brp r/w ? ? ffh 03fed25ch can3 module bit rate register c3btr r/w ? ? 370fh 03fed25eh can3 module last in-pointer register c3lipt r ? ? undefined 03fed260h can3 module receive hist ory list register c3rgpt r/w ? ? xx02h 03fed262h can3 module last out-pointer register c3lopt r ? ? undefined 03fed264h can3 module transmit history list register c3tgpt r/w ? ? xx02h 03fed266h can3 module time stamp register c3ts r/w ? ? 0000h chapter 15 can controller 640 user?s manual u17830ee1v0um00 (53/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed300h can3 message data byte 01 register 00 c3mdata0100 undefined 03fed300h can3 message data byte 0 register 00 c3mdata000 undefined 03fed301h can3 message data byte 1 register 00 c3mdata100 undefined 03fed302h can3 message data byte 23 register 00 c3mdata2300 undefined 03fed302h can3 message data byte 2 register 00 c3mdata200 undefined 03fed303h can3 message data byte 3 register 00 c3mdata300 undefined 03fed304h can3 message data byte 45 register 00 c3mdata4500 undefined 03fed304h can3 message data byte 4 register 00 c3mdata400 undefined 03fed305h can3 message data byte 5 register 00 c3mdata500 undefined 03fed306h can3 message data byte 67 register 00 c3mdata6700 undefined 03fed306h can3 message data byte 6 register 00 c3mdata600 undefined 03fed307h can3 message data byte 7 register 00 c3mdata700 undefined 03fed308h can3 message data length code register 00 c3mdlc00 0000xxxxb 03fed309h can3 message configurat ion register 00 c3mconf00 undefined 03fed30ah c3midl00 undefined 03fed30ch can3 message id register 00 c3midh00 undefined 03fed30eh can3 message control register 00 c3mctrl00 00x00000 000xx000b 03fed320h can3 message data byte 01 register 01 c3mdata0101 undefined 03fed320h can3 message data byte 0 register 01 c3mdata001 undefined 03fed321h can3 message data byte 1 register 01 c3mdata101 undefined 03fed322h can3 message data byte 23 register 01 c3mdata2301 undefined 03fed322h can3 message data byte 2 register 01 c3mdata201 undefined 03fed323h can3 message data byte 3 register 01 c3mdata301 undefined 03fed324h can3 message data byte 45 register 01 c3mdata4501 undefined 03fed324h can3 message data byte 4 register 01 c3mdata401 undefined 03fed325h can3 message data byte 5 register 01 c3mdata501 undefined 03fed326h can3 message data byte 67 register 01 c3mdata6701 undefined 03fed326h can3 message data byte 6 register 01 c3mdata601 undefined 03fed327h can3 message data byte 7 register 01 c3mdata701 undefined 03fed328h can3 message data length code register 01 c3mdlc01 0000xxxxb 03fed329h can3 message configurat ion register 01 c3mconf01 undefined 03fed32ah c3midl01 undefined 03fed32ch can3 message id register 01 c3midh01 undefined 03fed32eh can3 message control register 01 c3mctrl01 r/w 00x00000 000xx000b chapter 15 can controller 641 user?s manual u17830ee1v0um00 (54/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed340h can3 message data byte 01 register 02 c3mdata0102 undefined 03fed340h can3 message data byte 0 register 02 c3mdata002 undefined 03fed341h can3 message data byte 1 register 02 c3mdata102 undefined 03fed342h can3 message data byte 23 register 02 c3mdata2302 undefined 03fed342h can3 message data byte 2 register 02 c3mdata202 undefined 03fed343h can3 message data byte 3 register 02 c3mdata302 undefined 03fed344h can3 message data byte 45 register 02 c3mdata4502 undefined 03fed344h can3 message data byte 4 register 02 c3mdata402 undefined 03fed345h can3 message data byte 5 register 02 c3mdata502 undefined 03fed346h can3 message data byte 67 register 02 c3mdata6702 undefined 03fed346h can3 message data byte 6 register 02 c3mdata602 undefined 03fed347h can3 message data byte 7 register 02 c3mdata702 undefined 03fed348h can3 message data length code register 02 c3mdlc02 0000xxxxb 03fed349h can3 message configurat ion register 02 c3mconf02 undefined 03fed34ah c3midl02 undefined 03fed34ch can3 message id register 02 c3midh02 undefined 03fed34eh can3 message control register 02 c3mctrl02 00x00000 000xx000b 03fed360h can3 message data byte 01 register 03 c3mdata0103 undefined 03fed360h can3 message data byte 0 register 03 c3mdata003 undefined 03fed361h can3 message data byte 1 register 03 c3mdata103 undefined 03fed362h can3 message data byte 23 register 03 c3mdata2303 undefined 03fed362h can3 message data byte 2 register 03 c3mdata203 undefined 03fed363h can3 message data byte 3 register 03 c3mdata303 undefined 03fed364h can3 message data byte 45 register 03 c3mdata4503 undefined 03fed364h can3 message data byte 4 register 03 c3mdata403 undefined 03fed365h can3 message data byte 5 register 03 c3mdata503 undefined 03fed366h can3 message data byte 67 register 03 c3mdata6703 undefined 03fed366h can3 message data byte 6 register 03 c3mdata603 undefined 03fed367h can3 message data byte 7 register 03 c3mdata703 undefined 03fed368h can3 message data length code register 03 c3mdlc03 0000xxxxb 03fed369h can3 message configurat ion register 03 c3mconf03 undefined 03fed36ah c3midl03 undefined 03fed36ch can3 message id register 03 c3midh03 undefined 03fed36eh can3 message control register 03 c3mctrl03 r/w 00x00000 000xx000b chapter 15 can controller 642 user?s manual u17830ee1v0um00 (55/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed380h can3 message data byte 01 register 04 c3mdata0104 undefined 03fed380h can3 message data byte 0 register 04 c3mdata004 undefined 03fed381h can3 message data byte 1 register 04 c3mdata104 undefined 03fed382h can3 message data byte 23 register 04 c3mdata2304 undefined 03fed382h can3 message data byte 2 register 04 c3mdata204 undefined 03fed383h can3 message data byte 3 register 04 c3mdata304 undefined 03fed384h can3 message data byte 45 register 04 c3mdata4504 undefined 03fed384h can3 message data byte 4 register 04 c3mdata404 undefined 03fed385h can3 message data byte 5 register 04 c3mdata504 undefined 03fed386h can3 message data byte 67 register 04 c3mdata6704 undefined 03fed386h can3 message data byte 6 register 04 c3mdata604 undefined 03fed387h can3 message data byte 7 register 04 c3mdata704 undefined 03fed388h can3 message data length code register 04 c3mdlc04 0000xxxxb 03fed389h can3 message configurat ion register 04 c3mconf04 undefined 03fed38ah c3midl04 undefined 03fed38ch can3 message id register 04 c3midh04 undefined 03fed38eh can3 message control register 04 c3mctrl04 00x00000 000xx000b 03fed3a0h can3 message data byte 01 register 05 c3mdata0105 undefined 03fed3a0h can3 message data byte 0 register 05 c3mdata005 undefined 03fed3a1h can3 message data byte 1 register 05 c3mdata105 undefined 03fed3a2h can3 message data byte 23 register 05 c3mdata2305 undefined 03fed3a2h can3 message data byte 2 register 05 c3mdata205 undefined 03fed3a3h can3 message data byte 3 register 05 c3mdata305 undefined 03fed3a4h can3 message data byte 45 register 05 c3mdata4505 undefined 03fed3a4h can3 message data byte 4 register 05 c3mdata405 undefined 03fed3a5h can3 message data byte 5 register 05 c3mdata505 undefined 03fed3a6h can3 message data byte 67 register 05 c3mdata6705 undefined 03fed3a6h can3 message data byte 6 register 05 c3mdata605 undefined 03fed3a7h can3 message data byte 7 register 05 c3mdata705 undefined 03fed3a8h can3 message data length code register 05 c3mdlc05 0000xxxxb 03fed3a9h can3 message configur ation register 05 c3mconf05 undefined 03fed3aah c3midl05 undefined 03fed3ach can3 message id register 05 c3midh05 undefined 03fed3aeh can3 message control register 05 c3mctrl05 r/w 00x00000 000xx000b chapter 15 can controller 643 user?s manual u17830ee1v0um00 (56/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed3c0h can3 message data byte 01 register 06 c3mdata0106 undefined 03fed3c0h can3 message data byte 0 register 06 c3mdata006 undefined 03fed3c1h can3 message data byte 1 register 06 c3mdata106 undefined 03fed3c2h can3 message data byte 23 register 06 c3mdata2306 undefined 03fed3c2h can3 message data byte 2 register 06 c3mdata206 undefined 03fed3c3h can3 message data byte 3 register 06 c3mdata306 undefined 03fed3c4h can3 message data byte 45 register 06 c3mdata4506 undefined 03fed3c4h can3 message data byte 4 register 06 c3mdata406 undefined 03fed3c5h can3 message data byte 5 register 06 c3mdata506 undefined 03fed3c6h can3 message data byte 67 register 06 c3mdata6706 undefined 03fed3c6h can3 message data byte 6 register 06 c3mdata606 undefined 03fed3c7h can3 message data byte 7 register 06 c3mdata706 undefined 03fed3c8h can3 message data length code register 06 c3mdlc06 0000xxxxb 03fed3c9h can3 message configur ation register 06 c3mconf06 undefined 03fed3cah c3midl06 undefined 03fed3cch can3 message id register 06 c3midh06 undefined 03fed3ceh can3 message control register 06 c3mctrl06 00x00000 000xx000b 03fed3e0h can3 message data byte 01 register 07 c3mdata0107 undefined 03fed3e0h can3 message data byte 0 register 07 c3mdata007 undefined 03fed3e1h can3 message data byte 1 register 07 c3mdata107 undefined 03fed3e2h can3 message data byte 23 register 07 c3mdata2307 undefined 03fed3e2h can3 message data byte 2 register 07 c3mdata207 undefined 03fed3e3h can3 message data byte 3 register 07 c3mdata307 undefined 03fed3e4h can3 message data byte 45 register 07 c3mdata4507 undefined 03fed3e4h can3 message data byte 4 register 07 c3mdata407 undefined 03fed3e5h can3 message data byte 5 register 07 c3mdata507 undefined 03fed3e6h can3 message data byte 67 register 07 c3mdata6707 undefined 03fed3e6h can3 message data byte 6 register 07 c3mdata607 undefined 03fed3e7h can3 message data byte 7 register 07 c3mdata707 undefined 03fed3e8h can3 message data length code register 07 c3mdlc07 0000xxxxb 03fed3e9h can3 message configur ation register 07 c3mconf07 undefined 03fed3eah c3midl07 undefined 03fed3ech can3 message id register 07 c3midh07 undefined 03fed3eeh can3 message control register 07 c3mctrl07 r/w 00x00000 000xx000b chapter 15 can controller 644 user?s manual u17830ee1v0um00 (57/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed400h can3 message data byte 01 register 08 c3mdata0108 undefined 03fed400h can3 message data byte 0 register 08 c3mdata008 undefined 03fed401h can3 message data byte 1 register 08 c3mdata108 undefined 03fed402h can3 message data byte 23 register 08 c3mdata2308 undefined 03fed402h can3 message data byte 2 register 08 c3mdata208 undefined 03fed403h can3 message data byte 3 register 08 c3mdata308 undefined 03fed404h can3 message data byte 45 register 08 c3mdata4508 undefined 03fed404h can3 message data byte 4 register 08 c3mdata408 undefined 03fed405h can3 message data byte 5 register 08 c3mdata508 undefined 03fed406h can3 message data byte 67 register 08 c3mdata6708 undefined 03fed406h can3 message data byte 6 register 08 c3mdata608 undefined 03fed407h can3 message data byte 7 register 08 c3mdata708 undefined 03fed408h can3 message data length code register 08 c3mdlc08 0000xxxxb 03fed409h can3 message configurat ion register 08 c3mconf08 undefined 03fed40ah c3midl08 undefined 03fed40ch can3 message id register 08 c3midh08 undefined 03fed40eh can3 message control register 08 c3mctrl08 00x00000 000xx000b 03fed420h can3 message data byte 01 register 09 c3mdata0109 undefined 03fed420h can3 message data byte 0 register 09 c3mdata009 undefined 03fed421h can3 message data byte 1 register 09 c3mdata109 undefined 03fed422h can3 message data byte 23 register 09 c3mdata2309 undefined 03fed422h can3 message data byte 2 register 09 c3mdata209 undefined 03fed423h can3 message data byte 3 register 09 c3mdata309 undefined 03fed424h can3 message data byte 45 register 09 c3mdata4509 undefined 03fed424h can3 message data byte 4 register 09 c3mdata409 undefined 03fed425h can3 message data byte 5 register 09 c3mdata509 undefined 03fed426h can3 message data byte 67 register 09 c3mdata6709 undefined 03fed426h can3 message data byte 6 register 09 c3mdata609 undefined 03fed427h can3 message data byte 7 register 09 c3mdata709 undefined 03fed428h can3 message data length code register 09 c3mdlc09 0000xxxxb 03fed429h can3 message configurat ion register 09 c3mconf09 undefined 03fed42ah c3midl09 undefined 03fed42ch can3 message id register 09 c3midh09 undefined 03fed42eh can3 message control register 09 c3mctrl09 r/w 00x00000 000xx000b chapter 15 can controller 645 user?s manual u17830ee1v0um00 (58/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed440h can3 message data byte 01 register 10 c3mdata0110 undefined 03fed440h can3 message data byte 0 register 10 c3mdata010 undefined 03fed441h can3 message data byte 1 register 10 c3mdata110 undefined 03fed442h can3 message data byte 23 register 10 c3mdata2310 undefined 03fed442h can3 message data byte 2 register 10 c3mdata210 undefined 03fed443h can3 message data byte 3 register 10 c3mdata310 undefined 03fed444h can3 message data byte 45 register 10 c3mdata4510 undefined 03fed444h can3 message data byte 4 register 10 c3mdata410 undefined 03fed445h can3 message data byte 5 register 10 c3mdata510 undefined 03fed446h can3 message data byte 67 register 10 c3mdata6710 undefined 03fed446h can3 message data byte 6 register 10 c3mdata610 undefined 03fed447h can3 message data byte 7 register 10 c3mdata710 undefined 03fed448h can3 message data length code register 10 c3mdlc10 0000xxxxb 03fed449h can3 message configurat ion register 10 c3mconf10 undefined 03fed44ah c3midl10 undefined 03fed44ch can3 message id register 10 c3midh10 undefined 03fed44eh can3 message control register 10 c3mctrl10 00x00000 000xx000b 03fed460h can3 message data byte 01 register 11 c3mdata0111 undefined 03fed460h can3 message data byte 0 register 11 c3mdata011 undefined 03fed461h can3 message data byte 1 register 11 c3mdata111 undefined 03fed462h can3 message data byte 23 register 11 c3mdata2311 undefined 03fed462h can3 message data byte 2 register 11 c3mdata211 undefined 03fed463h can3 message data byte 3 register 11 c3mdata311 undefined 03fed464h can3 message data byte 45 register 11 c3mdata4511 undefined 03fed464h can3 message data byte 4 register 11 c3mdata411 undefined 03fed465h can3 message data byte 5 register 11 c3mdata511 undefined 03fed466h can3 message data byte 67 register 11 c3mdata6711 undefined 03fed466h can3 message data byte 6 register 11 c3mdata611 undefined 03fed467h can3 message data byte 7 register 11 c3mdata711 undefined 03fed468h can3 message data length code register 11 c3mdlc11 0000xxxxb 03fed469h can3 message configurat ion register 11 c3mconf11 undefined 03fed46ah c3midl11 undefined 03fed46ch can3 message id register 11 c3midh11 undefined 03fed46eh can3 message control register 11 c3mctrl11 r/w 00x00000 000xx000b chapter 15 can controller 646 user?s manual u17830ee1v0um00 (59/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed480h can3 message data byte 01 register 12 c3mdata0112 undefined 03fed480h can3 message data byte 0 register 12 c3mdata012 undefined 03fed481h can3 message data byte 1 register 12 c3mdata112 undefined 03fed482h can3 message data byte 23 register 12 c3mdata2312 undefined 03fed482h can3 message data byte 2 register 12 c3mdata212 undefined 03fed483h can3 message data byte 3 register 12 c3mdata312 undefined 03fed484h can3 message data byte 45 register 12 c3mdata4512 undefined 03fed484h can3 message data byte 4 register 12 c3mdata412 undefined 03fed485h can3 message data byte 5 register 12 c3mdata512 undefined 03fed486h can3 message data byte 67 register 12 c3mdata6712 undefined 03fed486h can3 message data byte 6 register 12 c3mdata612 undefined 03fed487h can3 message data byte 7 register 12 c3mdata712 undefined 03fed488h can3 message data length code register 12 c3mdlc12 0000xxxxb 03fed489h can3 message configurat ion register 12 c3mconf12 undefined 03fed48ah c3midl12 undefined 03fed48ch can3 message id register 12 c3midh12 undefined 03fed48eh can3 message control register 12 c3mctrl12 00x00000 000xx000b 03fed4a0h can3 message data byte 01 register 13 c3mdata0113 undefined 03fed4a0h can3 message data byte 0 register 13 c3mdata013 undefined 03fed4a1h can3 message data byte 1 register 13 c3mdata113 undefined 03fed4a2h can3 message data byte 23 register 13 c3mdata2313 undefined 03fed4a2h can3 message data byte 2 register 13 c3mdata213 undefined 03fed4a3h can3 message data byte 3 register 13 c3mdata313 undefined 03fed4a4h can3 message data byte 45 register 13 c3mdata4513 undefined 03fed4a4h can3 message data byte 4 register 13 c3mdata413 undefined 03fed4a5h can3 message data byte 5 register 13 c3mdata513 undefined 03fed4a6h can3 message data byte 67 register 13 c3mdata6713 undefined 03fed4a6h can3 message data byte 6 register 13 c3mdata613 undefined 03fed4a7h can3 message data byte 7 register 13 c3mdata713 undefined 03fed4a8h can3 message data length code register 13 c3mdlc13 0000xxxxb 03fed4a9h can3 message configur ation register 13 c3mconf13 undefined 03fed4aah c3midl13 undefined 03fed4ach can3 message id register 13 c3midh13 undefined 03fed4aeh can3 message control register 13 c3mctrl13 r/w 00x00000 000xx000b chapter 15 can controller 647 user?s manual u17830ee1v0um00 (60/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed4c0h can3 message data byte 01 register 14 c3mdata0114 undefined 03fed4c0h can3 message data byte 0 register 14 c3mdata014 undefined 03fed4c1h can3 message data byte 1 register 14 c3mdata114 undefined 03fed4c2h can3 message data byte 23 register 14 c3mdata2314 undefined 03fed4c2h can3 message data byte 2 register 14 c3mdata214 undefined 03fed4c3h can3 message data byte 3 register 14 c3mdata314 undefined 03fed4c4h can3 message data byte 45 register 14 c3mdata4514 undefined 03fed4c4h can3 message data byte 4 register 14 c3mdata414 undefined 03fed4c5h can3 message data byte 5 register 14 c3mdata514 undefined 03fed4c6h can3 message data byte 67 register 14 c3mdata6714 undefined 03fed4c6h can3 message data byte 6 register 14 c3mdata614 undefined 03fed4c7h can3 message data byte 7 register 14 c3mdata714 undefined 03fed4c8h can3 message data length code register 14 c3mdlc14 0000xxxxb 03fed4c9h can3 message configur ation register 14 c3mconf14 undefined 03fed4cah c3midl14 undefined 03fed4cch can3 message id register 14 c3midh14 undefined 03fed4ceh can3 message control register 14 c3mctrl14 00x00000 000xx000b 03fed4e0h can3 message data byte 01 register 15 c3mdata0115 undefined 03fed4e0h can3 message data byte 0 register 15 c3mdata015 undefined 03fed4e1h can3 message data byte 1 register 15 c3mdata115 undefined 03fed4e2h can3 message data byte 23 register 15 c3mdata2315 undefined 03fed4e2h can3 message data byte 2 register 15 c3mdata215 undefined 03fed4e3h can3 message data byte 3 register 15 c3mdata315 undefined 03fed4e4h can3 message data byte 45 register 15 c3mdata4515 undefined 03fed4e4h can3 message data byte 4 register 15 c3mdata415 undefined 03fed4e5h can3 message data byte 5 register 15 c3mdata515 undefined 03fed4e6h can3 message data byte 67 register 15 c3mdata6715 undefined 03fed4e6h can3 message data byte 6 register 15 c3mdata615 undefined 03fed4e7h can3 message data byte 7 register 15 c3mdata715 undefined 03fed4e8h can3 message data length code register 15 c3mdlc15 0000xxxxb 03fed4e9h can3 message configur ation register 15 c3mconf15 undefined 03fed4eah c3midl15 undefined 03fed4ech can3 message id register 15 c3midh15 undefined 03fed4eeh can3 message control register 15 c3mctrl15 r/w 00x00000 000xx000b chapter 15 can controller 648 user?s manual u17830ee1v0um00 (61/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed500h can3 message data byte 01 register 16 c3mdata0116 undefined 03fed500h can3 message data byte 0 register 16 c3mdata016 undefined 03fed501h can3 message data byte 1 register 16 c3mdata116 undefined 03fed502h can3 message data byte 23 register 16 c3mdata2316 undefined 03fed502h can3 message data byte 2 register 16 c3mdata216 undefined 03fed503h can3 message data byte 3 register 16 c3mdata316 undefined 03fed504h can3 message data byte 45 register 16 c3mdata4516 undefined 03fed504h can3 message data byte 4 register 16 c3mdata416 undefined 03fed505h can3 message data byte 5 register 16 c3mdata516 undefined 03fed506h can3 message data byte 67 register 16 c3mdata6716 undefined 03fed506h can3 message data byte 6 register 16 c3mdata616 undefined 03fed507h can3 message data byte 7 register 16 c3mdata716 undefined 03fed508h can3 message data length code register 16 c3mdlc16 0000xxxxb 03fed509h can3 message configurat ion register 16 c3mconf16 undefined 03fed50ah c3midl16 undefined 03fed50ch can3 message id register 16 c3midh16 undefined 03fed50eh can3 message control register 16 c3mctrl16 00x00000 000xx000b 03fed520h can3 message data byte 01 register 17 c3mdata0117 undefined 03fed520h can3 message data byte 0 register 17 c3mdata017 undefined 03fed521h can3 message data byte 1 register 17 c3mdata117 undefined 03fed522h can3 message data byte 23 register 17 c3mdata2317 undefined 03fed522h can3 message data byte 2 register 17 c3mdata217 undefined 03fed523h can3 message data byte 3 register 17 c3mdata317 undefined 03fed524h can3 message data byte 45 register 17 c3mdata4517 undefined 03fed524h can3 message data byte 4 register 17 c3mdata417 undefined 03fed525h can3 message data byte 5 register 17 c3mdata517 undefined 03fed526h can3 message data byte 67 register 17 c3mdata6717 undefined 03fed526h can3 message data byte 6 register 17 c3mdata617 undefined 03fed527h can3 message data byte 7 register 17 c3mdata717 undefined 03fed528h can3 message data length code register 17 c3mdlc17 0000xxxxb 03fed529h can3 message configurat ion register 17 c3mconf17 undefined 03fed52ah c3midl17 undefined 03fed52ch can3 message id register 17 c3midh17 undefined 03fed52eh can3 message control register 17 c3mctrl17 r/w 00x00000 000xx000b chapter 15 can controller 649 user?s manual u17830ee1v0um00 (62/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed540h can3 message data byte 01 register 18 c3mdata0118 undefined 03fed540h can3 message data byte 0 register 18 c3mdata018 undefined 03fed541h can3 message data byte 1 register 18 c3mdata118 undefined 03fed542h can3 message data byte 23 register 18 c3mdata2318 undefined 03fed542h can3 message data byte 2 register 18 c3mdata218 undefined 03fed543h can3 message data byte 3 register 18 c3mdata318 undefined 03fed544h can3 message data byte 45 register 18 c3mdata4518 undefined 03fed544h can3 message data byte 4 register 18 c3mdata418 undefined 03fed545h can3 message data byte 5 register 18 c3mdata518 undefined 03fed546h can3 message data byte 67 register 18 c3mdata6718 undefined 03fed546h can3 message data byte 6 register 18 c3mdata618 undefined 03fed547h can3 message data byte 7 register 18 c3mdata718 undefined 03fed548h can3 message data length code register 18 c3mdlc18 0000xxxxb 03fed549h can3 message configurat ion register 18 c3mconf18 undefined 03fed54ah c3midl18 undefined 03fed54ch can3 message id register 18 c3midh18 undefined 03fed54eh can3 message control register 18 c3mctrl18 00x00000 000xx000b 03fed560h can3 message data byte 01 register 19 c3mdata0119 undefined 03fed560h can3 message data byte 0 register 19 c3mdata019 undefined 03fed561h can3 message data byte 1 register 19 c3mdata119 undefined 03fed562h can3 message data byte 23 register 19 c3mdata2319 undefined 03fed562h can3 message data byte 2 register 19 c3mdata219 undefined 03fed563h can3 message data byte 3 register 19 c3mdata319 undefined 03fed564h can3 message data byte 45 register 19 c3mdata4519 undefined 03fed564h can3 message data byte 4 register 19 c3mdata419 undefined 03fed565h can3 message data byte 5 register 19 c3mdata519 undefined 03fed566h can3 message data byte 67 register 19 c3mdata6719 undefined 03fed566h can3 message data byte 6 register 19 c3mdata619 undefined 03fed567h can3 message data byte 7 register 19 c3mdata719 undefined 03fed568h can3 message data length code register 19 c3mdlc19 0000xxxxb 03fed569h can3 message configurat ion register 19 c3mconf19 undefined 03fed56ah c3midl19 undefined 03fed56ch can3 message id register 19 c3midh19 undefined 03fed56eh can3 message control register 19 c3mctrl19 r/w 00x00000 000xx000b chapter 15 can controller 650 user?s manual u17830ee1v0um00 (63/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed580h can3 message data byte 01 register 20 c3mdata0120 undefined 03fed580h can3 message data byte 0 register 20 c3mdata020 undefined 03fed581h can3 message data byte 1 register 20 c3mdata120 undefined 03fed582h can3 message data byte 23 register 20 c3mdata2320 undefined 03fed582h can3 message data byte 2 register 20 c3mdata220 undefined 03fed583h can3 message data byte 3 register 20 c3mdata320 undefined 03fed584h can3 message data byte 45 register 20 c3mdata4520 undefined 03fed584h can3 message data byte 4 register 20 c3mdata420 undefined 03fed585h can3 message data byte 5 register 20 c3mdata520 undefined 03fed586h can3 message data byte 67 register 20 c3mdata6720 undefined 03fed586h can3 message data byte 6 register 20 c3mdata620 undefined 03fed587h can3 message data byte 7 register 20 c3mdata720 undefined 03fed588h can3 message data length code register 20 c3mdlc20 0000xxxxb 03fed589h can3 message configurat ion register 20 c3mconf20 undefined 03fed58ah c3midl20 undefined 03fed58ch can3 message id register 20 c3midh20 undefined 03fed58eh can3 message control register 20 c3mctrl20 00x00000 000xx000b 03fed5a0h can3 message data byte 01 register 21 c3mdata0121 undefined 03fed5a0h can3 message data byte 0 register 21 c3mdata021 undefined 03fed5a1h can3 message data byte 1 register 21 c3mdata121 undefined 03fed5a2h can3 message data byte 23 register 21 c3mdata2321 undefined 03fed5a2h can3 message data byte 2 register 21 c3mdata221 undefined 03fed5a3h can3 message data byte 3 register 21 c3mdata321 undefined 03fed5a4h can3 message data byte 45 register 21 c3mdata4521 undefined 03fed5a4h can3 message data byte 4 register 21 c3mdata421 undefined 03fed5a5h can3 message data byte 5 register 21 c3mdata521 undefined 03fed5a6h can3 message data byte 67 register 21 c3mdata6721 undefined 03fed5a6h can3 message data byte 6 register 21 c3mdata621 undefined 03fed5a7h can3 message data byte 7 register 21 c3mdata721 undefined 03fed5a8h can3 message data length code register 21 c3mdlc21 0000xxxxb 03fed5a9h can3 message configur ation register 21 c3mconf21 undefined 03fed5aah c3midl21 undefined 03fed5ach can3 message id register 21 c3midh21 undefined 03fed5aeh can3 message control register 21 c3mctrl21 r/w 00x00000 000xx000b chapter 15 can controller 651 user?s manual u17830ee1v0um00 (64/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed5c0h can3 message data byte 01 register 22 c3mdata0122 undefined 03fed5c0h can3 message data byte 0 register 22 c3mdata022 undefined 03fed5c1h can3 message data byte 1 register 22 c3mdata122 undefined 03fed5c2h can3 message data byte 23 register 22 c3mdata2322 undefined 03fed5c2h can3 message data byte 2 register 22 c3mdata222 undefined 03fed5c3h can3 message data byte 3 register 22 c3mdata322 undefined 03fed5c4h can3 message data byte 45 register 22 c3mdata4522 undefined 03fed5c4h can3 message data byte 4 register 22 c3mdata422 undefined 03fed5c5h can3 message data byte 5 register 22 c3mdata522 undefined 03fed5c6h can3 message data byte 67 register 22 c3mdata6722 undefined 03fed5c6h can3 message data byte 6 register 22 c3mdata622 undefined 03fed5c7h can3 message data byte 7 register 22 c3mdata722 undefined 03fed5c8h can3 message data length code register 22 c3mdlc22 0000xxxxb 03fed5c9h can3 message configur ation register 22 c3mconf22 undefined 03fed5cah c3midl22 undefined 03fed5cch can3 message id register 22 c3midh22 undefined 03fed5ceh can3 message control register 22 c3mctrl22 00x00000 000xx000b 03fed5e0h can3 message data byte 01 register 23 c3mdata0123 undefined 03fed5e0h can3 message data byte 0 register 23 c3mdata023 undefined 03fed5e1h can3 message data byte 1 register 23 c3mdata123 undefined 03fed5e2h can3 message data byte 23 register 23 c3mdata2323 undefined 03fed5e2h can3 message data byte 2 register 23 c3mdata223 undefined 03fed5e3h can3 message data byte 3 register 23 c3mdata323 undefined 03fed5e4h can3 message data byte 45 register 23 c3mdata4523 undefined 03fed5e4h can3 message data byte 4 register 23 c3mdata423 undefined 03fed5e5h can3 message data byte 5 register 23 c3mdata523 undefined 03fed5e6h can3 message data byte 67 register 23 c3mdata6723 undefined 03fed5e6h can3 message data byte 6 register 23 c3mdata623 undefined 03fed5e7h can3 message data byte 7 register 23 c3mdata723 undefined 03fed5e8h can3 message data length code register 23 c3mdlc23 0000xxxxb 03fed5e9h can3 message configur ation register 23 c3mconf23 undefined 03fed5eah c3midl23 undefined 03fed5ech can3 message id register 23 c3midh23 undefined 03fed5eeh can3 message control register 23 c3mctrl23 r/w 00x00000 000xx000b chapter 15 can controller 652 user?s manual u17830ee1v0um00 (65/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed600h can3 message data byte 01 register 24 c3mdata0124 undefined 03fed600h can3 message data byte 0 register 24 c3mdata024 undefined 03fed601h can3 message data byte 1 register 24 c3mdata124 undefined 03fed602h can3 message data byte 23 register 24 c3mdata2324 undefined 03fed602h can3 message data byte 2 register 24 c3mdata224 undefined 03fed603h can3 message data byte 3 register 24 c3mdata324 undefined 03fed604h can3 message data byte 45 register 24 c3mdata4524 undefined 03fed604h can3 message data byte 4 register 24 c3mdata424 undefined 03fed605h can3 message data byte 5 register 24 c3mdata524 undefined 03fed606h can3 message data byte 67 register 24 c3mdata6724 undefined 03fed606h can3 message data byte 6 register 24 c3mdata624 undefined 03fed607h can3 message data byte 7 register 24 c3mdata724 undefined 03fed608h can3 message data length code register 24 c3mdlc24 0000xxxxb 03fed609h can3 message configurat ion register 24 c3mconf24 undefined 03fed60ah c3midl24 undefined 03fed60ch can3 message id register 24 c3midh24 undefined 03fed60eh can3 message control register 24 c3mctrl24 00x00000 000xx000b 03fed620h can3 message data byte 01 register 25 c3mdata0125 undefined 03fed620h can3 message data byte 0 register 25 c3mdata025 undefined 03fed621h can3 message data byte 1 register 25 c3mdata125 undefined 03fed622h can3 message data byte 23 register 25 c3mdata2325 undefined 03fed622h can3 message data byte 2 register 25 c3mdata225 undefined 03fed623h can3 message data byte 3 register 25 c3mdata325 undefined 03fed624h can3 message data byte 45 register 25 c3mdata4525 undefined 03fed624h can3 message data byte 4 register 25 c3mdata425 undefined 03fed625h can3 message data byte 5 register 25 c3mdata525 undefined 03fed626h can3 message data byte 67 register 25 c3mdata6725 undefined 03fed626h can3 message data byte 6 register 25 c3mdata625 undefined 03fed627h can3 message data byte 7 register 25 c3mdata725 undefined 03fed628h can3 message data length code register 25 c3mdlc25 0000xxxxb 03fed629h can3 message configurat ion register 25 c3mconf25 undefined 03fed62ah c3midl25 undefined 03fed62ch can3 message id register 25 c3midh25 undefined 03fed62eh can3 message control register 25 c3mctrl25 r/w 00x00000 000xx000b chapter 15 can controller 653 user?s manual u17830ee1v0um00 (66/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed640h can3 message data byte 01 register 26 c3mdata0126 undefined 03fed640h can3 message data byte 0 register 26 c3mdata026 undefined 03fed641h can3 message data byte 1 register 26 c3mdata126 undefined 03fed642h can3 message data byte 23 register 26 c3mdata2326 undefined 03fed642h can3 message data byte 2 register 26 c3mdata226 undefined 03fed643h can3 message data byte 3 register 26 c3mdata326 undefined 03fed644h can3 message data byte 45 register 26 c3mdata4526 undefined 03fed644h can3 message data byte 4 register 26 c3mdata426 undefined 03fed645h can3 message data byte 5 register 26 c3mdata526 undefined 03fed646h can3 message data byte 67 register 26 c3mdata6726 undefined 03fed646h can3 message data byte 6 register 26 c3mdata626 undefined 03fed647h can3 message data byte 7 register 26 c3mdata726 undefined 03fed648h can3 message data length code register 26 c3mdlc26 0000xxxxb 03fed649h can3 message configurat ion register 26 c3mconf26 undefined 03fed64ah c3midl26 undefined 03fed64ch can3 message id register 26 c3midh26 undefined 03fed64eh can3 message control register 26 c3mctrl26 00x00000 000xx000b 03fed660h can3 message data byte 01 register 27 c3mdata0127 undefined 03fed660h can3 message data byte 0 register 27 c3mdata027 undefined 03fed661h can3 message data byte 1 register 27 c3mdata127 undefined 03fed662h can3 message data byte 23 register 27 c3mdata2327 undefined 03fed662h can3 message data byte 2 register 27 c3mdata227 undefined 03fed663h can3 message data byte 3 register 27 c3mdata327 undefined 03fed664h can3 message data byte 45 register 27 c3mdata4527 undefined 03fed664h can3 message data byte 4 register 27 c3mdata427 undefined 03fed665h can3 message data byte 5 register 27 c3mdata527 undefined 03fed666h can3 message data byte 67 register 27 c3mdata6727 undefined 03fed666h can3 message data byte 6 register 27 c3mdata627 undefined 03fed667h can3 message data byte 7 register 27 c3mdata727 undefined 03fed668h can3 message data length code register 27 c3mdlc27 0000xxxxb 03fed669h can3 message configurat ion register 27 c3mconf27 undefined 03fed66ah c3midl27 undefined 03fed66ch can3 message id register 27 c3midh27 undefined 03fed66eh can3 message control register 27 c3mctrl27 r/w 00x00000 000xx000b chapter 15 can controller 654 user?s manual u17830ee1v0um00 (67/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed680h can3 message data byte 01 register 28 c3mdata0128 undefined 03fed680h can3 message data byte 0 register 28 c3mdata028 undefined 03fed681h can3 message data byte 1 register 28 c3mdata128 undefined 03fed682h can3 message data byte 23 register 28 c3mdata2328 undefined 03fed682h can3 message data byte 2 register 28 c3mdata228 undefined 03fed683h can3 message data byte 3 register 28 c3mdata328 undefined 03fed684h can3 message data byte 45 register 28 c3mdata4528 undefined 03fed684h can3 message data byte 4 register 28 c3mdata428 undefined 03fed685h can3 message data byte 5 register 28 c3mdata528 undefined 03fed686h can3 message data byte 67 register 28 c3mdata6728 undefined 03fed686h can3 message data byte 6 register 28 c3mdata628 undefined 03fed687h can3 message data byte 7 register 28 c3mdata728 undefined 03fed688h can3 message data length code register 28 c3mdlc28 0000xxxxb 03fed689h can3 message configurat ion register 28 c3mconf28 undefined 03fed68ah c3midl28 undefined 03fed68ch can3 message id register 28 c3midh28 undefined 03fed68eh can3 message control register 28 c3mctrl28 00x00000 000xx000b 03fed6a0h can3 message data byte 01 register 29 c3mdata0129 undefined 03fed6a0h can3 message data byte 0 register 29 c3mdata029 undefined 03fed6a1h can3 message data byte 1 register 29 c3mdata129 undefined 03fed6a2h can3 message data byte 23 register 29 c3mdata2329 undefined 03fed6a2h can3 message data byte 2 register 29 c3mdata229 undefined 03fed6a3h can3 message data byte 3 register 29 c3mdata329 undefined 03fed6a4h can3 message data byte 45 register 29 c3mdata4529 undefined 03fed6a4h can3 message data byte 4 register 29 c3mdata429 undefined 03fed6a5h can3 message data byte 5 register 29 c3mdata529 undefined 03fed6a6h can3 message data byte 67 register 29 c3mdata6729 undefined 03fed6a6h can3 message data byte 6 register 29 c3mdata629 undefined 03fed6a7h can3 message data byte 7 register 29 c3mdata729 undefined 03fed6a8h can3 message data length code register 29 c3mdlc29 0000xxxxb 03fed6a9h can3 message configur ation register 29 c3mconf29 undefined 03fed6aah c3midl29 undefined 03fed6ach can3 message id register 29 c3midh29 undefined 03fed6aeh can3 message control register 29 c3mctrl29 r/w 00x00000 000xx000b chapter 15 can controller 655 user?s manual u17830ee1v0um00 (68/68) bit manipulation units address register name symbol r/w 1 8 16 after reset 03fed6c0h can3 message data byte 01 register 30 c3mdata0130 undefined 03fed6c0h can3 message data byte 0 register 30 c3mdata030 undefined 03fed6c1h can3 message data byte 1 register 30 c3mdata130 undefined 03fed6c2h can3 message data byte 23 register 30 c3mdata2330 undefined 03fed6c2h can3 message data byte 2 register 30 c3mdata230 undefined 03fed6c3h can3 message data byte 3 register 30 c3mdata330 undefined 03fed6c4h can3 message data byte 45 register 30 c3mdata4530 undefined 03fed6c4h can3 message data byte 4 register 30 c3mdata430 undefined 03fed6c5h can3 message data byte 5 register 30 c3mdata530 undefined 03fed6c6h can3 message data byte 67 register 30 c3mdata6730 undefined 03fed6c6h can3 message data byte 6 register 30 c3mdata630 undefined 03fed6c7h can3 message data byte 7 register 30 c3mdata730 undefined 03fed6c8h can3 message data length code register 30 c3mdlc30 0000xxxxb 03fed6c9h can3 message configur ation register 30 c3mconf30 undefined 03fed6cah c3midl30 undefined 03fed6cch can3 message id register 30 c3midh30 undefined 03fed6ceh can3 message control register 30 c3mctrl30 00x00000 000xx000b 03fed6e0h can3 message data byte 01 register 31 c3mdata0131 undefined 03fed6e0h can3 message data byte 0 register 31 c3mdata031 undefined 03fed6e1h can3 message data byte 1 register 31 c3mdata131 undefined 03fed6e2h can3 message data byte 23 register 31 c3mdata2331 undefined 03fed6e2h can3 message data byte 2 register 31 c3mdata231 undefined 03fed6e3h can3 message data byte 3 register 31 c3mdata331 undefined 03fed6e4h can3 message data byte 45 register 31 c3mdata4531 undefined 03fed6e4h can3 message data byte 4 register 31 c3mdata431 undefined 03fed6e5h can3 message data byte 5 register 31 c3mdata531 undefined 03fed6e6h can3 message data byte 67 register 31 c3mdata6731 undefined 03fed6e6h can3 message data byte 6 register 31 c3mdata631 undefined 03fed6e7h can3 message data byte 7 register 31 c3mdata731 undefined 03fed6e8h can3 message data length code register 31 c3mdlc31 0000xxxx 03fed6e9h can3 message configur ation register 31 c3mconf31 undefined 03fed6eah c3midl31 undefined 03fed6ech can3 message id register 31 c3midh31 undefined 03fed6eeh can3 message control register 31 c3mctrl31 r/w 00x00000 000xx000b chapter 15 can controller 656 user?s manual u17830ee1v0um00 15.5.3 register bit configuration table 15-17. can global register bit configuration address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fexx00h 0 0 0 0 0 0 0 clear gom 03fexx01h cngmctrl (w) 0 0 0 0 0 0 set efsd set gom 03fexx00h 0 0 0 0 0 0 efsd gom 03fexx01h cngmctrl (r) mbon 0 0 0 0 0 0 0 03fexx02h cngmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 03fexx06h 0 0 0 0 0 0 0 clear abttrg 03fexx07h cngmabt (w) 0 0 0 0 0 0 set abtclr set abttrg 03fexx06h 0 0 0 0 0 0 abtclr abttrg 03fexx07h cngmabt (r) 0 0 0 0 0 0 0 0 03fexx08h cngmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 657 user?s manual u17830ee1v0um00 table 15-18. can module register bit configuration (1/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fexx40h cm1id[7:0] 03fexx41h cnmask1l cm1id[15:8] 03fexx42h cm1id[23:16] 03fexx43h cnmask1h 0 0 0 cm1id[28:24] 03fexx44h cm2id[7:0] 03fexx45h cnmask2l cm2id[15:8] 03fexx46h cm2id[23:16] 03fexx47h cnmask2h 0 0 0 cm2id[28:24] 03fexx48h cm3id[7:0] 03fexx49h cnmask3l cm3id[15:8] 03fexx4ah cm3id[23:16] 03fexx4bh cnmask3h 0 0 0 cm3id[28:24] 03fexx4ch cm4id[7:0] 03fexx4dh cnmask4l cm4id[15:8] 03fexx4eh cm4id[23:16] 03fexx4fh cnmask4h 0 0 0 cm4id[28:24] 03fexx50h 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 03fexx51h cnctrl (w) set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 03fexx50h ccerc al valid ps mode1 ps mode0 op mode2 op mode1 op mode0 03fexx51h cnctrl (r) 0 0 0 0 0 0 rstat tstat 03fexx52h cnlec (w) 0 0 0 0 0 0 0 0 03fexx52h cnlec (r) 0 0 0 0 0 lec2 lec1 lec0 03fexx53h cninfo 0 0 0 boff tecs1 tecs0 recs1 recs0 03fexx54h tec[7:0] 03fexx55h cnerc reps rec[6:0] 03fexx56h 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 03fexx57h cnie (w) 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 03fexx56h 0 0 cie5 cie4 cie3 cie2 cie1 cie0 03fexx57h cnie (r) 0 0 0 0 0 0 0 0 03fexx58h 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 03fexx59h cnints (w) 0 0 0 0 0 0 0 0 03fexx58h 0 0 cints5 cints4 cints3 cints2 cints1 cints0 03fexx59h cnints (r) 0 0 0 0 0 0 0 0 remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 658 user?s manual u17830ee1v0um00 (2/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fexx5ah cnbrp tqprs[7:0] 03fexx5ch 0 0 0 0 tseg1[3:0] 03fexx5dh cnbtr 0 0 sjw[1:0] 0 tseg2[2:0] 03fexx5eh cnlipt lipt[7:0] 03fexx60h 0 0 0 0 0 0 0 clear rovf 03fexx61h cnrgpt (w) 0 0 0 0 0 0 0 0 03fexx60h 0 0 0 0 0 0 rhpm rovf 03fexx61h cnrgpt (r) rgpt[7:0] 03fexx62h cnlopt lopt[7:0] 03fexx64h 0 0 0 0 0 0 0 clear tovf 03fexx65h cntgpt (w) 0 0 0 0 0 0 0 0 03fexx64h 0 0 0 0 0 0 thpm tovf 03fexx65h cntgpt (r) tgpt[7:0] 03fexx66h 0 0 0 0 0 clear tslock clear tssel clear tsen 03fexx67h cnts (w) 0 0 0 0 0 set tslock set tssel set tsen 03fexx66h 0 0 0 0 0 tslock tssel tsen 03fexx67h cnts (r) 0 0 0 0 0 0 0 0 03fexx68h to 03fexxffh ? access prohibited (reserved for future use) remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 659 user?s manual u17830ee1v0um00 table 15-19. message buffer register bit configuration address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fexxx0h message data (byte 0) 03fexxx1h cnmdata01m message data (byte 1) 03fexxx0h cnmdata0m message data (byte 0) 03fexxx1h cnmdata1m message data (byte 1) 03fexxx2h message data (byte 2) 03fexxx3h cnmdata23m message data (byte 3) 03fexxx2h cnmdata2m message data (byte 2) 03fexxx3h cnmdata3m message data (byte 3) 03fexxx4h message data (byte 4) 03fexxx5h cnmdata45m message data (byte 5) 03fexxx4h cnmdata4m message data (byte 4) 03fexxx5h cnmdata5m message data (byte 5) 03fexxx6h message data (byte 6) 03fexxx7h cnmdata67m message data (byte 7) 03fexxx6h cnmdata6m message data (byte 6) 03fexxx7h cnmdata7m message data (byte 7) 03fexxx8h cnmdlcm 0 mdlc3 mdlc2 mdlc1 mdlc0 03fexxx9h cnmconfm ows rtr mt2 mt1 mt0 0 0 ma0 03fexxxah id7 id6 id5 id4 id3 id2 id1 id0 03fexxxbh cnmidlm id15 id14 id13 id12 id11 id10 id9 id8 03fexxxch id23 id22 id21 id20 id19 id18 id17 id16 03fexxxdh cnmidhm ide 0 0 id28 id27 id26 id25 id24 03fexxxeh 0 0 0 clear mow clear ie clear dn clear trq clear rdy 03fexxxfh cnmctrlm (w) 0 0 0 0 set ie 0 set trq set rdy 03fexxxeh 0 0 0 mow ie dn trq rdy 03fexxxfh cnmctrlm (r) 0 0 muc 0 0 0 0 0 03fexxx0 to 03fexxxfh ? access prohibited (reserved for future use) remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 660 user?s manual u17830ee1v0um00 15.6 control registers remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 (1) can global control re gister (cngmctrl) the cngmctrl register is used to cont rol the operation of the can module. (1/2) after reset: 0000h r/w address: c0gmctrl 03ffec000h, c1gmctrl 03fec600h c2gmctrl 03fecc00h, c3gmctrl 03fed200h (a) read 15 14 13 12 11 10 9 8 cngmctrl mbon 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 efsd gom (b) write 15 14 13 12 11 10 9 8 cngmctrl 0 0 0 0 0 0 set efsd set gom 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear gom (a) read mbon bit enabling access to message buffer regi ster, transmit/receive history registers 0 write access and read access to the message buffer register and the transm it/receive history list registers is disabled. 1 write access and read access to the message buffer register and the transm it/receive history list registers is enabled. cautions 1. while the mbon bit is cleared (to 0), software access to the message buffers (cnmdata0m, cnmdata1m, cnmdat a01m, cnmdata2m, cnmdata3m, cnmdata23m, cnmdata4m, cnmdat a5m, cnmdata45m, cnmdata6m, cnmdata7m, cnmdata67m, cnmdlcm, cnmconfm, cnmidlm, cnmidhm, and cnmctrlm), or registers rela ted to transmit history or receive history (cnlopt, cntgpt, cnlipt, and cnrgpt) is disabled. 2. this bit is read-only. even if 1 is writ ten to mbon while it is 0, the value of mbon does not change, and access to the message buffe r registers, or registers related to transmit history or recei ve history remains disabled. chapter 15 can controller 661 user?s manual u17830ee1v0um00 (2/2) efsd bit enabling forced shut down 0 forced shut down by gom = 0 disabled. 1 forced shut down by gom = 0 enabled. caution to request forced shut down, the gom bi t must be cleared to 0 immediately after the efsd bit has been set to 1. if access to another regist er (including reading the cngmctrl register) is executed without cl earing the gom bit immediately after the efsd bit has been set to 1, th e efsd bit is forcibly cleared to 0, and the forced shut down request is invalid. gom global operation mode bit 0 can module is disabled from operating. 1 can module is enabled to operate. caution the gom bit is cleared only in the initialization mode. (b) write set efsd efsd bit setting 0 no change in efsd bit. 1 efsd bit set to 1. set gom clear gom gom bit setting 0 1 gom bit cleared to 0. 1 0 gom bit set to 1. other than above no change in gom bit. chapter 15 can controller 662 user?s manual u17830ee1v0um00 (2) can global clock selection register (cngmcs) the cngmcs register is used to select the can module system clock. after reset: 0fh r/w address: c0gmcs 03fec002h, c1gmcs 03fec602h c2gmcs 03fecc02h, c3gmcs 03fed202h 7 6 5 4 3 2 1 0 cngmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 ccp3 ccp2 ccp1 ccp1 can module system clock (f canmod ) 0 0 0 0 f can /1 0 0 0 1 f can /2 0 0 1 0 f can /3 0 0 1 1 f can /4 0 1 0 0 f can /5 0 1 0 1 f can /6 0 1 1 0 f can /7 0 1 1 1 f can /8 1 0 0 0 f can /9 1 0 0 1 f can /10 1 0 1 0 f can /11 1 0 1 1 f can /12 1 1 0 0 f can /13 1 1 0 1 f can /14 1 1 1 0 f can /15 1 1 1 1 f can /16 (default value) remark f can = clock supplied to can = f xx chapter 15 can controller 663 user?s manual u17830ee1v0um00 (3) can global automatic block transm ission control register (cngmabt) the cngmabt register is used to control the automatic block transmission (abt) operation. (1/2) after reset: 0000h r/w address: c0gmabt 03fec006h, c1gmabt 03fec606h c2gmabt 03fecc06h, c3gmabt 03fed206h (a) read 15 14 13 12 11 10 9 8 cngmabt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 abtclr abttrg (a) write 15 14 13 12 11 10 9 8 cngmabt 0 0 0 0 0 0 set abtclr set abttrg 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear abttrg caution before changing the norma l operation mode with abt to the initialization mode, be sure to set the cngmabt register to the default value (00h). (a) read abtclr automatic block transmi ssion engine clear status bit 0 clearing the automatic transmission engine is completed. 1 the automatic transmissi on engine is being cleared. remarks 1. set the abtclr bit to 1 while t he abttrg bit is cleared to 0. the operation is not guaranteed if the abtclr bit is set to 1 while the abttrg bit is set to 1. 2. when the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared to 0 as soon as the requested clearing processing is complete. abttrg automatic block transmission status bit 0 automatic block transmission is stopped. 1 automatic block transmissi on is under execution. caution do not set the abttrg bit in the initiali zation mode. if the abttrg bit is set in the initialization mode, the opera tion is not guaranteed after the can module has entered the normal operation mode with abt. chapter 15 can controller 664 user?s manual u17830ee1v0um00 (2/2) (b) write set abtclr automatic block trans mission engine clear request bit 0 the automatic block transmission engine is in idle state or under operation. 1 request to clear the automatic block transmissi on engine. after the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the abttrg bit to 1. set abttrg clear abttrg automati c block transmi ssion start bit 0 1 request to stop automatic block transmission. 1 0 request to start automatic block transmission. other than above no change in abttrg bit. chapter 15 can controller 665 user?s manual u17830ee1v0um00 (4) can global automatic block transm ission delay register (cngmabtd) the cngmabtd register is used to set the interval at which the data of the message buffer assigned to abt is to be transmitted in the normal operation mode with abt. after reset: 00h r/w address: c0gmabtd 03fec008h, c1gmabtd 03fec608h c2gmabtd 03fecc08h, c3gmabtd 03fed208h 7 6 5 4 3 2 1 0 cngmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 abtd3 abtd2 abtd1 abtd0 data frame interval during aut omatic block transmission (unit: data bit time (dbt)) 0 0 0 0 0 dbt (default value) 0 0 0 1 2 5 dbt 0 0 1 0 2 6 dbt 0 0 1 1 2 7 dbt 0 1 0 0 2 8 dbt 0 1 0 1 2 9 dbt 0 1 1 0 2 10 dbt 0 1 1 1 2 11 dbt 1 0 0 0 2 12 dbt other than above setting prohibited cautions 1. do not change the contents of the cngmabtd register while th e abttrg bit is set to 1. 2. the timing at which th e abt message is actually transmitted onto the can bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an abt mess age (message buffers 8 to 31) is made. chapter 15 can controller 666 user?s manual u17830ee1v0um00 (5) can module mask control register (cnmas kal, cnmaskah) (a = 1, 2, 3, or 4) the cnmaskal and cnmaskah registers are used to extend the number of receivable messages by masking part of the identifier (id) of a message and invalidating the id of the masked part. (1/2) ? cann module mask 1 register (cnmask1l, cnmask1h) after reset: undefined r/w address: c0mask1l 03fec040h, c1mask1l 03fec640h c2mask1l 03fecc40h, c3mask1l 03fed240h c0mask1h 03fec042h, c1mask1h 03fec642h c2mask1h 03fecc42h, c3mask1h 03fed242h 15 14 13 12 11 10 9 8 cnmask1l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 cnmask1h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 ? cann module mask 2 register (cnmask2l, cnmask2h) after reset: undefined r/w address: c0mask2l 03fec044h, c1mask2l 03fec644h c2mask2l 03fecc44h, c3mask2l 03fed244h c0mask2h 03fec046h, c1mask2h 03fec646h c2mask2h 03fecc46h, c3mask2h 03fed246h 15 14 13 12 11 10 9 8 cnmask2l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 cnmask2h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 chapter 15 can controller 667 user?s manual u17830ee1v0um00 (2/2) ? cann module mask 3 register (cnmask3l, cnmask3h) after reset: undefined r/w address: c0mask3l 03fec048h, c1mask3l 03fec648h c2mask3l 03fecc48h, c3mask3l 03fed248h c0mask3h 03fec04ah, c1mask3h 03fec64ah c2mask3h 03fecc4ah, c3mask3h 03fed24ah 15 14 13 12 11 10 9 8 cnmask3l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 cnmask3h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 ? cann module mask 4 register (cnmask4l, cnmask4h) after reset: undefined r/w address: c0mask4l 03fec04ch, c1mask4l 03fec64ch c2mask4l 03fecc4ch, c3mask4l 03fed24ch c0mask4h 03fec04eh, c1mask4h 03fec64eh c2mask4h 03fecc4eh, c3mask4h 03fed24eh 15 14 13 12 11 10 9 8 cnmask4l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 cnmask4h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmid28 to cmid0 mask pattern setting of id bit 0 the id bits of the message buffer set by the cmid28 to cmid0 bits are compared with the id bits of the received message frame. 1 the id bits of the message buffer set by the cmid28 to cmid0 bits are not compared with the id bits of the received message frame (they are masked). remark masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, cmid17 to cmid0 are ignored. therefor e, only cmid28 to cmid18 of the received id are masked. the same mask can be us ed for both the standard and extended ids. chapter 15 can controller 668 user?s manual u17830ee1v0um00 (6) can module control register (cnctrl) the cnctrl register is used to control the operation mode of the can module. (1/4) after reset: 0000h r/w address: c0ctrl 03fec050h, c1ctrl 03fec650h c2ctrl 03fecc50h, c3ctrl 03fed250h (a) read 15 14 13 12 11 10 9 8 cnctrl 0 0 0 0 0 0 rstat tstat 7 6 5 4 3 2 1 0 ccerc al valid psmode 1 psmode 0 opmode 2 opmode 1 opmode 0 (a) write 15 14 13 12 11 10 9 8 cnctrl set ccerc set al 0 set psmode 1 set psmode 0 set opmode 2 set opmode 1 set opmode 0 7 6 5 4 3 2 1 0 0 clear al clear valid clear psmode 1 clear psmode 0 clear opmode 2 clear opmode 1 clear opmode 0 (a) read rstat reception status bit 0 reception is stopped. 1 reception is in progress. remark ? the rstat bit is set to 1 under the following conditions (timing) ? the sof bit of a receive frame is detected ? on occurrence of arbitration loss during a transmit frame ? the rstat bit is cleared to 0 under the following conditions (timing) ? when a recessive level is detected at the second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space chapter 15 can controller 669 user?s manual u17830ee1v0um00 (2/4) tstat transmission status bit 0 transmission is stopped. 1 transmission is in progress. remark ? the tstat bit is set to 1 under the following conditions (timing) ? the sof bit of a transmit frame is detected ? the first bit of an error flag is detected during a transmit frame ? the tstat bit is cleared to 0 under the following conditions (timing) ? during transition to bus-off state ? on occurrence of arbitration loss in transmit frame ? on detection of recessive level at t he second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space ccerc error counter clear bit 0 the cnerc and cninfo registers are not cleared in the initialization mode. 1 the cnerc and cninfo registers are cleared in the initialization mode. remarks 1. the ccerc bit is used to clear the cnerc and cninfo registers for re-initialization or forced recovery from the bus-off state. this bit can be set to 1 only in the initialization mode. 2. when the cnerc and cninfo registers have bee n cleared, the ccerc bit is also cleared to 0 automatically. 3. the ccerc bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. the ccerc bit is read-only in t he can sleep mode or can stop mode. al bit to set operation in case of arbitration loss 0 re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 re-transmission is executed in case of an arbitration loss in the single-shot mode. remarks 1. the al bit is valid only in the single-shot mode. 2. the al bit is read-only in the can sleep mode or can stop mode. chapter 15 can controller 670 user?s manual u17830ee1v0um00 (3/4) valid valid receive message frame detection bit 0 a valid message frame has not been received since the valid bit was last cleared to 0. 1 a valid message frame has been received since the valid bit was last cleared to 0. remarks 1 . detection of a valid receive message fram e is not dependent upon storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. clear the valid bit (0) before changing the initialization mode to an operation mode. 3 . if only two can nodes are connected to the can bus with one transmitting a message frame in the normal mode and the other in the reception mode, the valid bit is not set to 1 before the transmitting node enters the error passive state. 4 . to clear the valid bit, set the clear valid bit to 1 first and confirm that the valid bit is cleared. if it is not cleared, perform clearing processing again. psmode1 psmode0 power save mode 0 0 no power save mode is selected. 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode caution transition to and from the can stop mode must be made via can sleep mode. a request for direct transition to and fr om the can stop mode is ignored. opmode2 opmode1 opmo de0 operation mode 0 0 0 no operation mode is selected (can module is in the initialization mode). 0 0 1 normal operation mode 0 1 0 normal operation mode with automat ic block transmission function (normal operation mode with abt) 0 1 1 receive-only mode 1 0 0 single-shot mode 1 0 1 self-test mode other than above setting prohibited remark the opmode[2:0] bits are read-only in the can sleep mode or can stop mode. chapter 15 can controller 671 user?s manual u17830ee1v0um00 (4/4) (b) write set ccerc setting of ccerc bit 1 ccerc bit is set to 1. other than above ccerc bit is not changed. set al clear al setting of al bit 0 1 al bit is cleared to 0. 1 0 al bit is set to 1. other than above al bit is not changed. clear valid setting of valid bit 0 valid bit is not changed. 1 valid bit is cleared to 0. set psmode0 clear psmode0 setting of psmode0 bit 0 1 psmode0 bit is cleared to 0. 1 0 psmode bit is set to 1. other than above psmode0 bit is not changed. set psmode1 clear psmode1 setting of psmode1 bit 0 1 psmode1 bit is cleared to 0. 1 0 psmode1 bit is set to 1. other than above psmode1 bit is not changed. set opmode0 clear opmode0 setting of opmode0 bit 0 1 opmode0 bit is cleared to 0. 1 0 opmode0 bit is set to 1. other than above opmode0 bit is not changed. set opmode1 clear opmode1 setting of opmode1 bit 0 1 opmode1 bit is cleared to 0. 1 0 opmode1 bit is set to 1. other than above opmode1 bit is not changed. set opmode2 clear opmode2 setting of opmode2 bit 0 1 opmode2 bit is cleared to 0. 1 0 opmode2 bit is set to 1. other than above opmode2 bit is not changed. chapter 15 can controller 672 user?s manual u17830ee1v0um00 (7) can module last error info rmation register (cnlec) the cnlec register provides the erro r information of the can protocol. after reset: 00h r/w address: c0lec 03fec052h, c1lec 03fec652h c2lec 03fecc52h, c3lec 03fed252h 7 6 5 4 3 2 1 0 cnlec 0 0 0 0 0 lec2 lec1 lec0 remarks 1. the contents of the cnlec register are not cleared when the can module changes from an operation mode to the initialization mode. 2. if an attempt is made to write a value other than 00h to the cnlec register by software, the access is ignored. lec2 lec1 lec0 last can protocol error information 0 0 0 no error 0 0 1 stuff error 0 1 0 form error 0 1 1 ack error 1 0 0 bit error. (the can module tried to transm it a recessive-level bit as part of a transmit message (except the arbitration fi eld), but the value on the can bus is a dominant-level bit.) 1 0 1 bit error. (the can module tried to tran smit a dominant-level bit as part of a transmit message, ack bit, error frame, or overload frame, but the value on the can bus is a recessive-level bit.) 1 1 0 crc error 1 1 1 undefined chapter 15 can controller 673 user?s manual u17830ee1v0um00 (8) can module information register (cninfo) the cninfo register indicates the status of the can module. after reset: 00h r address: c0info 03fec053h, c1info 03fec653h c2info 03fecc53h, c3info 03fed253h 7 6 5 4 3 2 1 0 cninfo 0 0 0 boff tecs1 tecs0 recs1 recs0 boff bus-off status bit 0 not bus-off state (transmit error counter 255). (the value of the transmit counter is less than 256.) 1 bus-off state (transmit error counter > 255). (the value of the transmit counter is 256 or more.) tecs1 tecs0 transmission e rror counter status bit 0 0 the value of the transmission error counter is less than that of the warning level ( < 96). 0 1 the value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 undefined 1 1 the value of the transmission error counter is in the range of the error pas sive or bus-off state ( 128). recs1 recs0 reception error counter status bit 0 0 the value of the reception error counter is less than that of the warning level ( < 96). 0 1 the value of the reception error counter is in the range of the warning level (96 to 127). 1 0 undefined 1 1 the value of the reception error c ounter is in the error passive range ( 128). chapter 15 can controller 674 user?s manual u17830ee1v0um00 (9) can module error counter register (cnerc) the cnerc register indicates the count value of the transmission/reception error counter. after reset: 0000h r address: c0erc 03fec054h, c1erc 03fec654h c2erc 03fecc54h, c3erc 03fed254h 15 14 13 12 11 10 9 8 cnerc reps rec6 rec5 rec4 rec3 rec2 rec1 rec0 7 6 5 4 3 2 1 0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 reps reception error passive status bit 0 reception error counter is not error passive ( < 128) 1 reception error counter is error passive range ( 128) rec6 to rec0 reception error counter bit 0 to 127 number of reception errors. these bits reflect the status of the reception error counter. the number of errors is defined by the can protocol. remark rec7 to rec0 of the reception error counter are invalid in the reception error passive state (recs[1:0] = 11b). tec7 to tec0 transmission error counter bit 0 to 255 number of transmission errors. these bits reflect the status of the transmission error counter. the number of errors is defined by the can protocol. remark tec7 to tec0 of the transmission error coun ter are invalid in the bus-off state (boff = 1). chapter 15 can controller 675 user?s manual u17830ee1v0um00 (10) can module interrupt enable register (cnie) the cnie register is used to enable or disable the interrupts of the can module. (1/2) after reset: 0000h r/w address: c0ie 03fec056h, c1ie 03fec656h c2ie 03fecc56h, c3ie 03fed256h (a) read 15 14 13 12 11 10 9 8 cnie 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 cie5 cie4 cie3 cie2 cie1 cie0 (b) write 15 14 13 12 11 10 9 8 cnie 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 7 6 5 4 3 2 1 0 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 (a) read cie5 to cie0 can module interrupt enable bit 0 output of the interrupt corresponding to inte rrupt status register cintsx is disabled. 1 output of the interrupt corresponding to interrupt status register cintsx is enabled. chapter 15 can controller 676 user?s manual u17830ee1v0um00 (2/2) (b) write set cie5 clear cie5 setting of cie5 bit 0 1 cie5 bit is cleared to 0. 1 0 cie5 bit is set to 1. other than above cie5 bit is not changed. set cie4 clear cie4 setting of cie4 bit 0 1 cie4 bit is cleared to 0. 1 0 cie4 bit is set to 1. other than above cie4 bit is not changed. set cie3 clear cie3 setting of cie3 bit 0 1 cie3 bit is cleared to 0. 1 0 cie3 bit is set to 1. other than above cie3 bit is not changed. set cie2 clear cie2 setting of cie2 bit 0 1 cie2 bit is cleared to 0. 1 0 cie2 bit is set to 1. other than above cie2 bit is not changed. set cie1 clear cie1 setting of cie1 bit 0 1 cie1 bit is cleared to 0. 1 0 cie1 bit is set to 1. other than above cie1 bit is not changed. set cie0 clear cie0 setting of cie0 bit 0 1 cie0 bit is cleared to 0. 1 0 cie0 bit is set to 1. other than above cie0 bit is not changed. chapter 15 can controller 677 user?s manual u17830ee1v0um00 (11) can module interrupt status register (cnints) the cnints register indicates the in terrupt status of the can module. after reset: 0000h r/w address: c0ints 03fec058h, c1ints 03fec658h c2ints 03fecc58h, c3ints 03fed258h (a) read 15 14 13 12 11 10 9 8 cnints 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 cints5 cints4 cints3 cints2 cints1 cints0 (b) write 15 14 13 12 11 10 9 8 cnints 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 (a) read cints5 to cints0 can interrupt status bit 0 no related interrupt source event is pending. 1 a related interrupt source event is pending. interrupt status bit related interrupt source event cints5 wakeup interrupt from can sleep mode note cints4 arbitration loss interrupt cints3 can protocol error interrupt cints2 can error status interrupt cints1 interrupt on completion of reception of valid message frame to message buffer m cints0 interrupt on normal completion of tr ansmission of message frame from message buffer m note the cints5 bit is set only when the can module is woken up from the can sleep mode by a can bus operation. the cint s5 bit is not set when the can sleep mode has been released by software. (b) write clear cints5 to cints0 setting of cints5 to cints0 bits 0 cints5 to cints0 bits are not changed. 1 cints5 to cints0 bits are cleared to 0. chapter 15 can controller 678 user?s manual u17830ee1v0um00 (12) can module bit rate prescaler register (cnbrp) the cnbrp register is used to select the can protocol layer base clock (f tq ). the communication baud rate is set to the cnbtr register. after reset: ffh r/w address: c0brp 03fec05ah, c1brp 03fec65ah c2brp 03fecc5ah, c3brp 03fed25ah 7 6 5 4 3 2 1 0 cnbrp tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 tqprs7 to tqprs0 can protocol layer base system clock (f tq ) 0 f canmod /1 1 f canmod /2 n f canmod /(n+1) ..... ..... 255 f canmod /256 (default value) figure 15-23. can module clock ccp 3 ccp2 prescaler can module bit-rate prescaler register (cnbrp) can module clock selection register (cngmcs) baud rate generator can bit-rate register (cnbtr) ccp1 ccp0 tqprs0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7 remark f can : clock supplied to can = f xx f canmod : can module system clock f tq : can protocol layer basic system clock caution the cnbrp register can be write- accessed only in the initialization mode. chapter 15 can controller 679 user?s manual u17830ee1v0um00 (13) can module bit rate register (cnbtr) the cnbtr register is used to control the data bit time of the communication baud rate. (1/2) after reset: 370fh r/w address: c0btr 03fec05ch, c1btr 03fec65ch c2btr 03fecc5ch, c3btr 03fed25ch 15 14 13 12 11 10 9 8 cnbtr 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 7 6 5 4 3 2 1 0 0 0 0 0 tseg13 t seg12 tseg11 tseg10 figure 15-24. data bit time data bit time (dbt) time segment 1 (tseg1) phase segment 2 phase segment 1 sample point (spt) prop segment sync segment time segment 2 (tseg2) chapter 15 can controller 680 user?s manual u17830ee1v0um00 (2/2) sjw1 sjw0 length of synchronization jump width 0 0 1tq 0 1 2tq 1 0 3tq 1 1 4tq (default value) tseg22 tseg21 tseg20 length of time segment 2 0 0 0 1tq 0 0 1 2tq 0 1 0 3tq 0 1 1 4tq 1 0 0 5tq 1 0 1 6tq 1 1 0 7tq 1 1 1 8tq (default value) tseg13 tseg12 tseg 11 tseg10 length of time segment 1 0 0 0 0 setting prohibited 0 0 0 1 2tq note 0 0 1 0 3tq note 0 0 1 1 4tq 0 1 0 0 5tq 0 1 0 1 6tq 0 1 1 0 7tq 0 1 1 1 8tq 1 0 0 0 9tq 1 0 0 1 10tq 1 0 1 0 11tq 1 0 1 1 12tq 1 1 0 0 13tq 1 1 0 1 14tq 1 1 1 0 15tq 1 1 1 1 16tq (default value) note this setting must not be made when the cnbrp register = 00h. remark tq = 1/f tq (f tq : can protocol layer basic system clock) chapter 15 can controller 681 user?s manual u17830ee1v0um00 (14) can module last in-pointer register (cnlipt) the cnlipt register indicates the number of the message buffer in whic h a data frame or a remote frame was last stored. after reset: undefined r address: c0lipt 03fec05eh, c1lipt 03fec65eh c2lipt 03fecc5eh, c3lipt 03fed25eh 7 6 5 4 3 2 1 0 cnlipt lipt7 lipt6 lipt5 li pt4 lipt3 lipt2 lipt1 lipt0 lipt7 to lipt0 last in-pointer register (cnlipt) 0.....31 when the cnlipt register is read, the contents of the element indexed by the last in-pointer (lipt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame was last stored. remark the read value of the cnlipt r egister is undefined if a data fr ame or a remote frame has never been stored in the message buffer. if the rhpm bit of the cnrgpt register is set to 1 after the can module has changed from the initialization mo de to an operation mode, therefore, the read value of the cnlipt register is undefined. chapter 15 can controller 682 user?s manual u17830ee1v0um00 (15) can module receive history list register (cnrgpt) the cnrgpt register is used to read the receive history list. (1/2) after reset: xx02h r/w address: c0rgpt 03fec060h, c1rgpt 03fec660h c2rgpt 03fecc60h, c3rgpt 03fed260h (a) read 15 14 13 12 11 10 9 8 cnrgpt rgpt7 rgpt6 rgpt5 rg pt4 rgpt3 rgpt2 rgpt1 rgpt0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 rhpm rovf (b) write 15 14 13 12 11 10 9 8 cnrgpt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear rovf (a) read rgpt7 to rgpt0 receive history list read pointer 0.....31 when the cnrgpt register is read, the contents of the element indexed by the receive history list get pointer (rgpt) of the receive history list are re ad. these contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. rhpm note 1 receive history list pointer match 0 the receive history list has at least one message buffer number that has not been read. 1 the receive history list has no message buffer numbers that have not been read. rovf receive history list overflow bit 0 all the message buffer numbers that have not bee n read are preserved. all the numbers of the message buffers in which a new data frame or remo te frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 all the message buffer numbers that are recorded are preserved except the message buffer number recorded last note 2 . the number of the message buffer in wh ich a new data frame or remote frame has been received and stored is recorded to the receiv e history list, by overwr iting the message buffer number that was recorded last (the receive history list does not have a vacant element). notes 1. the read value of rgpt0 to 7 is invalid when rhpm = 1. 2. if no new data frame or remote frame is rece ived and stored in a message buffer after the rovf bit has been set, the message buffer number last recorded to the receive history list is preserved. chapter 15 can controller 683 user?s manual u17830ee1v0um00 (2/2) (b) write clear rovf setting of rovf bit 0 rovf bit is not changed. 1 rovf bit is cleared to 0. (16) can module last out-pointer register (cnlopt) the cnlopt register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. after reset: undefined r address: c0lopt 03fec062h, c1lopt 03fec662h c2lopt 03fecc62h, c3lopt 03fed262h 7 6 5 4 3 2 1 0 cnlopt lopt7 lopt6 lopt5 lo pt4 lopt3 lopt 2 lopt1 lopt0 lopt7 to lopt0 last out-pointer of transmit history list (lopt) 0.....31 when the cnlopt register is read, the contents of the element indexed by the last out-pointer (lopt) of the receive history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. remark the value read from the cnlopt register is undefined if a data fr ame or remote frame has never been transmitted from a message buffer. if the th pm bit is set to 1 after the can module has changed from the initialization m ode to an operation mode, theref ore, the read value of the cnlopt register is undefined. chapter 15 can controller 684 user?s manual u17830ee1v0um00 (17) can module transmit history list register (cntgpt) the cntgpt register is used to read the transmit history list. (1/2) after reset: xx02h r/w address: c0tgpt 03fec064h, c1tgpt 03fec664h c2tgpt 03fecc64h, c3tgpt 03fed264h (a) read 15 14 13 12 11 10 9 8 cntgpt tgpt7 tgpt6 tgpt5 tg pt4 tgpt3 tgpt2 tgpt1 tgpt0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 thpm tovf 15 14 13 12 11 10 9 8 cntgpt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear tovf tgpt7 to tgpt0 transmit history list read pointer 0.....31 when the cntgpt register is read, the content s of the element indexed by the read pointer (tgpt) of the transmit history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. thpm note 1 transmit history pointer match 0 the transmit history list has at least one message buffer number that has not been read. 1 the transmit history list has no message buffer numbers that have not been read. tovf transmit history list overflow bit 0 all the message buffer numbers that have not bee n read are preserved. all the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transm it history list has a vacant element). 1 all the message buffer numbers that are reco rded are preserved except the message buffer number recorded last note 2 . the number of the message buffer to which a new data frame or remote frame has been transmitted is recorded to the transmit history list, by overwriting the message buffer number that was recorded last (the transmit history list does not have a vacant element). notes 1. the read value of tgpt0 to tgpt 7 is invalid when thpm = 1.3. 2. if no new data frame or remote frame is tr ansmitted after the tovf bit has been set, the message buffer number last recorded to the transmit history list is preserved. remark transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal operation mode with abt. chapter 15 can controller 685 user?s manual u17830ee1v0um00 (2/2) (b) write clear tovf setting of tovf bit 0 tovf bit is not changed. 1 tovf bit is cleared to 0. (18) can module time stamp register (cnts) the cnts register is used to c ontrol the time stamp function. (1/2) after reset: 0000h r/w address: c0ts 03fec066h, c1ts 03fec666h c2ts 03fecc66h, c3ts 03fed266h (a) read 15 14 13 12 11 10 9 8 cnts 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 tslock tssel tsen (b) write 15 14 13 12 11 10 9 8 cnts 0 0 0 0 0 set tslock set tssel set tsen 7 6 5 4 3 2 1 0 0 0 0 0 0 clear tslock clear tssel clear tsen remark the time stamp function must not be used when the can modul e is in the normal operation mode with abt. chapter 15 can controller 686 user?s manual u17830ee1v0um00 (2/2) (a) read tslock time stamp lock function enable bit 0 time stamp lock function stopped. the tsout signal is toggled each time the selected time stamp capture event occurs. 1 time stamp lock function enabled. the tsout output signal is locked when a data frame has been correctly received to message buffer 0 note . note the tsen bit is automatically cleared to 0. tssel time stamp capture event selection bit 0 the time capture event is sof. 1 the time stamp capture event is the last bit of eof. tsen tsout operation setting bit 0 tsout toggle operation is disabled. 1 tsout toggle operation is enabled. (b) write set tslock clear tslock setting of tslock bit 0 1 tslock bit is cleared to 0. 1 0 tslock bit is set to 1. other than above tslock bit is not changed. set tssel clear tssel setting of tssel bit 0 1 tssel bit is cleared to 0. 1 0 tssel bit is set to 1. other than above tssel bit is not changed. set tsen clear tsen setting of tsen bit 0 1 tsen bit is cleared to 0. 1 0 tsen bit is set to 1. other than above tsen bit is not changed . chapter 15 can controller 687 user?s manual u17830ee1v0um00 (19) can message data byte register (cnmdataxm) (x = 0 to 7) the cnmdataxm register is used to store the data of a transmit/receive message. (1/2) after reset: undefined r/w address: see table 15-16 . 15 14 13 12 11 10 9 8 cnmdata01m mdata01 15 mdata01 14 mdata01 13 mdata01 12 mdata01 11 mdata01 10 mdata01 9 mdata01 8 7 6 5 4 3 2 1 0 mdata01 7 mdata01 6 mdata01 5 mdata01 4 mdata01 3 mdata01 2 mdata01 1 mdata01 0 7 6 5 4 3 2 1 0 cnmdata0m mdata0 7 mdata0 6 mdata0 5 mdata0 4 mdata0 3 mdata0 2 mdata0 1 mdata0 0 7 6 5 4 3 2 1 0 cnmdata1m mdata1 7 mdata1 6 mdata1 5 mdata1 4 mdata1 3 mdata1 2 mdata1 1 mdata1 0 15 14 13 12 11 10 9 8 cnmdata23m mdata23 15 mdata23 14 mdata23 13 mdata23 12 mdata23 11 mdata23 10 mdata23 9 mdata23 8 7 6 5 4 3 2 1 0 mdata23 7 mdata23 6 mdata23 5 mdata23 4 mdata23 3 mdata23 2 mdata23 1 mdata23 0 7 6 5 4 3 2 1 0 cnmdata2m mdata2 7 mdata2 6 mdata2 5 mdata2 4 mdata2 3 mdata2 2 mdata2 1 mdata2 0 7 6 5 4 3 2 1 0 cnmdata3m mdata3 7 mdata3 6 mdata3 5 mdata3 4 mdata3 3 mdata3 2 mdata3 1 mdata3 0 chapter 15 can controller 688 user?s manual u17830ee1v0um00 (2/2) 15 14 13 12 11 10 9 8 cnmdata45m mdata45 15 mdata45 14 mdata45 13 mdata45 12 mdata45 11 mdata45 10 mdata45 9 mdata45 8 7 6 5 4 3 2 1 0 mdata45 7 mdata45 6 mdata45 5 mdata45 4 mdata45 3 mdata45 2 mdata45 1 mdata45 0 7 6 5 4 3 2 1 0 cnmdata4m mdata4 7 mdata4 6 mdata4 5 mdata4 4 mdata4 3 mdata4 2 mdata4 1 mdata4 0 7 6 5 4 3 2 1 0 cnmdata5m mdata5 7 mdata5 6 mdata5 5 mdata5 4 mdata5 3 mdata5 2 mdata5 1 mdata5 0 15 14 13 12 11 10 9 8 cnmdata67m mdata67 15 mdata67 14 mdata67 13 mdata67 12 mdata67 11 mdata67 10 mdata67 9 mdata67 8 7 6 5 4 3 2 1 0 mdata67 7 mdata67 6 mdata67 5 mdata67 4 mdata67 3 mdata67 2 mdata67 1 mdata67 0 7 6 5 4 3 2 1 0 cnmdata6m mdata6 7 mdata6 6 mdata6 5 mdata6 4 mdata6 3 mdata6 2 mdata6 1 mdata6 0 7 6 5 4 3 2 1 0 cnmdata7m mdata7 7 mdata7 6 mdata7 5 mdata7 4 mdata7 3 mdata7 2 mdata7 1 mdata7 0 chapter 15 can controller 689 user?s manual u17830ee1v0um00 (20) can message data length register m (cnmdlcm) the cnmdlcm register is used to set the number of bytes of the data field of a message buffer. after reset: 0000xxxxb r/w address: see table 15-16 . 7 6 5 4 3 2 1 0 cnmdlcm 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 mdlc3 mdlc2 mdlc1 mdlc0 data length of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 setting prohibited (if these bits are set during transmi ssion, 8-byte data is transmitted regardless of the set dlc value when a data frame is transmitted. however, the dlc actually transmitted to the can bus is the dlc value set to this register.) note note the data and dlc value actually transmitted to can bus are as follows. type of transmit frame length of transmit data dlc transmitted data frame number of bytes specified by dlc (however, 8 bytes if dlc 8) remote frame 0 bytes mdlc[3:0] cautions 1. be sure to set bits 7 to 4 to 0000b. 2. receive data is stored in as many cn mdatax as the number of bytes (however, the upper limit is 8) corresponding to dlc. cnm datax in which no data is stored is undefined. chapter 15 can controller 690 user?s manual u17830ee1v0um00 (21) can message configurat ion register (cnmconfm) the cnmconfm register is used to specify t he type of the message buffer and to set a mask. (1/2) after reset: undefined r/w address: see table 15-16 . 7 6 5 4 3 2 1 0 cnmconfm ows rtr mt2 mt1 mt0 0 0 ma0 ows overwrite control bit 0 the message buffer note that has already received a data frame is not overwritten by a newly received data frame. the newly received data frame is discarded. 1 the message buffer that has already received a data frame is overwritten by a newly received data frame. note the ?message buffer that has already received a data frame? is a receive message buffer whose dn bit has been set to 1. remark a remote frame is received and stored, regardl ess of the setting of ows and dn. a remote frame that satisfies the other conditions (id matches, rtr = 0, trq = 0) is always received and stored in the corresponding message buffer (interrupt generated, dn flag set, mdlc[3:0] bits updated, and recorded to the receive history list). rtr remote frame request bit note 0 transmit a data frame. 1 transmit a remote frame. note the rtr bit specifies the type of message frame that is transmitted from a message buffer defined as a transmit message buffer. even if a valid remo te frame has been received, rtr of the transmit message buffer that has received the frame remains cleared to 0. even if a remote frame whose id matches has been received from the can bus with the rtr bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, dn flag set, mdlc[3:0] bits updated, and recorded to the receive history list). mt2 mt1 mt0 message buffer type setting bit 0 0 0 transmit message buffer 0 0 1 receive message buffer (no mask setting) 0 1 0 receive message buffer (mask 1 set) 0 1 1 receive message buffer (mask 2 set) 1 0 0 receive message buffer (mask 3 set) 1 0 1 receive message buffer (mask 4 set) other than above setting prohibited chapter 15 can controller 691 user?s manual u17830ee1v0um00 (2/2) ma0 message buffer assignment bit 0 message buffer not used. 1 message buffer used. caution be sure to write 0 to bits 2 and 1. (22) can message id register m (cnmidlm, cnmidhm) the cnmidlm and cnmidhm registers ar e used to set an identifier (id). after reset: undefined r/w address: see table 15-16 . 15 14 13 12 11 10 9 8 cnmidlm id15 id14 id13 id12 id11 id10 id9 id8 7 6 5 4 3 2 1 0 id7 id6 id5 id4 id3 id2 id1 id0 15 14 13 12 11 10 9 8 cnmidhm ide 0 0 id28 id27 id26 id25 id24 7 6 5 4 3 2 1 0 id23 id22 id21 id20 id19 id18 id17 id16 ide format mode specification bit 0 standard format mode (id28 to id18: 11 bits) note 1 extended format mode (id28 to id0: 29 bits) note the id17 to id0 bits are not used. id28 to id0 message id id28 to id18 standard id value of 11 bits (when ide = 0) id28 to id0 extended id value of 29 bits (when ide = 1) caution be sure to write 0 to bits 14 and 13 of the cnmidhm register. chapter 15 can controller 692 user?s manual u17830ee1v0um00 (23) can message control register m (cnmctrlm) the cnmctrlm register is used to cont rol the operation of the message buffer. (1/2) after reset: 00x000000 00000000b r/w address: see table 15-16 . (a) read 15 14 13 12 11 10 9 8 cnmctrlm 0 0 muc 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 mow ie dn trq rdy (b) write 15 14 13 12 11 10 9 8 cnmctrlm 0 0 0 0 set ie 0 set trq set rdy 7 6 5 4 3 2 1 0 0 0 0 clear mow clear ie clear dn clear trq clear rdy (a) read muc note bit indicating that message buffer data is being updated 0 the can module is not updating the me ssage buffer (reception and storage). 1 the can module is updating the message buffer (reception and storage). note the muc bit is undefined until the firs t reception and storage is performed. mow message buffer overwrite status bit 0 the message buffer is not overwritt en by a newly received data frame. 1 the message buffer is overwritten by a newly received data frame. remark mow is not set to 1 even if a remote frame is received and stored in the transmit message buffer with dn = 1. ie message buffer interrupt request enable bit 0 receive message buffer: valid message re ception completion interrupt disabled. transmit message buffer: normal message tr ansmission completion interrupt disabled. 1 receive message buffer: valid message reception completion interrupt enabled. transmit message buffer: normal message transmission completion interrupt enabled. dn message buffer data update bit 0 a data frame or remote frame is not stored in the message buffer. 1 a data frame or remote frame is stored in the message buffer. chapter 15 can controller 693 user?s manual u17830ee1v0um00 (2/2) trq message buffer transmission request bit 0 no message frame transmitting request that is pe nding or being transmitted is in the message buffer. 1 the message buffer is holding transmission of a me ssage frame pending or is transmitting a message frame. rdy message buffer ready bit 0 the message buffer can be written by software. the can module cannot write to the message buffer. 1 writing the message buffer by software is ignored (e xcept a write access to the rdy, trq, dn, and mow bits). the can module can write to the message buffer. caution do not clear the rdy bit (0) during message transmission. (b) write clear mow setting of mow bit 0 mow bit is not changed. 1 mow bit is cleared to 0. set ie clear ie setting of ie bit 0 1 ie bit is cleared to 0. 1 0 ie bit is set to 1. other than above ie bit is not changed. clear dn setting of dn bit 1 dn bit is cleared to 0. 0 dn bit is not changed. caution do not set the dn bit to 1 by softw are. be sure to write 0 to bit 10. set trq clear trq setting of trq bit 0 1 trq bit is cleared to 0. 1 0 trq bit is set to 1. other than above trq bit is not changed. set rdy clear rdy setting of rdy bit 0 1 rdy bit is cleared to 0. 1 0 rdy bit is set to 1. other than above rdy bit is not changed. chapter 15 can controller 694 user?s manual u17830ee1v0um00 15.7 bit set/clear function the can control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following registers are written directly. do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. ? can global control register (cngmctrl) ? can global automatic block trans mission control register (cngmabt) ? can module control register (cnctrl) ? can module interrupt enable register (cnie) ? can module interrupt status register (cnints) ? can module receive history list register (cnrgpt) ? can module transmit history list register (cntgpt) ? can module time stamp register (cnts) ? can message control register (cnmctrlm) remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 all the 16 bits in the above register s can be read via the usual method. use the procedure described in figure 15- 25 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the bit status after set/clear operation is specified in figure 15-26). figure 15-25 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. chapter 15 can controller 695 user?s manual u17830ee1v0um00 figure 15-25. example of bi t setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set no change clear bit status register?s current value write value register?s value after write operation clear clear no change no change set figure 15-26. bit status after bit setting/clearing operations 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 c lear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of bit n after bit set/clear operation 0 0 no change 0 1 0 1 0 1 1 1 no change remark n = 0 to 7 chapter 15 can controller 696 user?s manual u17830ee1v0um00 15.8 can controller initialization 15.8.1 initialization of can module before can module operation is enabled, the can modu le system clock needs to be determined by setting the ccp[3:0] bits of the cngmcs register by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting t he gom bit of the cngmctrl register. for the procedure of initializ ing the can module, refer to 15.16 operation of can controller. 15.8.2 initialization of message buffer after the can module is enabled, the message buffers contai n undefined values. a minimum initialization for all the message buffers, even for those not used in the applicat ion, is necessary before switching the can module from the initialization mode to on e of the operation modes. ? clear the rdy, trq, and dn bits of the cnmctrlm register to 0. ? clear the ma0 bit of the cnmconfm register to 0. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 15.8.3 redefinition of message buffer redefining a message buffer means changing the id a nd control information of the message buffer while a message is being received or transmitted, without a ffecting other transmissi on/reception operations. (1) to redefine message buffe r in initialization mode place the can module in the initialization mode once an d then change the id and control information of the message buffer in the initialization mode. after c hanging the id and control information, set the can module to an operation mode. (2) to redefine message buffer during reception perform redefinition as shown in figure 15-38. (3) to redefine message buffer during transmission to rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (refer to 15.10.4 (1) transmission abort in normal operation mode and 15.10.4 (2) transmission abort in normal operation mode with automatic bl ock transmission (abt)) . confirm that transmission has been aborted or comple ted, and then redefine the message buffer. after redefining the transmit message buffer, set a transmissio n request using the procedure described below. when setting a transmission request to a message buf fer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. chapter 15 can controller 697 user?s manual u17830ee1v0um00 figure 15-27. setting transmission request (trq) to transmit message buffer after redefinition execute transmission? wait for 1 bit of can data. set trq bit set trq bit = 1 clear trq bit = 0 yes no redefinition completed end cautions 1. when a message is r eceived, reception filtering is perf ormed in accordance with the id and mask set to each receive messag e buffer. if the procedure in figure 15-38 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). if this happens, check that the id and ide received first and stored in the messag e buffer following redefinition are those stored after the message buffer has been redefined. if no id and ide are stored after redefinition, redefine the message buffer again. 2. when a message is transm itted, the transmission priority is checked in accordance with the id, ide, and rtr bits set to each transmit message buffer to which a transmission request was set. the transmit mes sage buffer having the highest priority is selected for transmission. if the procedure in figure 15- 27 is not observed, a message with an id not having the highest priority may be transmitted afte r redefinition. 15.8.4 transition from initializa tion mode to operation mode the can module can be switched to the following operation modes. ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode chapter 15 can controller 698 user?s manual u17830ee1v0um00 figure 15-28. transition to operation modes can module channel invalid [receive-only mode] opmode[2:0]=03h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 03h [single-shot mode] opmode[2:0]=04h opmode[2:0] = 04h opmode[2:0] = 05h init mode opmode[2:0] = 00h efsd = 1 and gom = 0 all can modules are in init mode and gom = 0 gom = 1 reset reset released [normal operation mode with abt] opmode[2:0]=02h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 02h opmode[2:0] = 01h opmode[2:0] = 00h and can bus is busy. [normal operation mode] opmode[2:0]=01h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and can bus is busy. [self-test mode] opmode[2:0]=05h the transition from the initia lization mode to an operation mode is contro lled by the bit string opmode[2:0] in the cnctrl register. changing from one operation mode into another requires sh ifting to the initialization mode in between. do not change one operation mode to another directly; otherwise the operation will not be guaranteed. requests for transition from an operation mode to the in itialization mode are held pending when the can bus is not in the interframe space (i.e., frame reception or tran smission is in progress), and the can module enters the initialization mode at the first bit in the interframe space (the values of opmode[2:0] are changed to 00h). after issuing a request to change the mode to the initialization mode, read the opmode[2:0] bits until their values become 000b to confirm that the module has enter ed the initialization mode (refer to figure 15-36 ). remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 15.8.5 resetting error counter cnerc of can module if it is necessary to reset the can module error counter cnerc and the can module information register cninfo when re-initialization or forced recovery from the bus-off st ate is made, set the ccerc bit of the cnctrl register to 1 in the initialization mode. when this bit is set to 1, the can module error counter cnerc and the can module information register cninfo are cleared to their default values. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 699 user?s manual u17830ee1v0um00 15.9 message reception 15.9.1 message reception in all the operation modes, when a message is received, a message buffer that is to store the message is searched from all the message buffers satisfying the following conditions. ? used as a message buffer (ma0 bit of cnmconfm register set to 1b.) ? set as a receive message buffer (mt[2:0] bits of cnmconfm register set to 001b, 010b, 011b, 100b, or 101b.) ? ready for reception (rdy bit of cnmctrlm register set to 1.) when two or more message buffers of the can module receive a message, the message is stored according to the priority explained below. the message is always stor ed in the message buffer with the highest priority, not in a message buffer with a low priority. for example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same id, the message is always stored in the unmasked receive message buffer even if this unmasked receive buffer has already received a message earlier. priority storing condition if same id is set dn = 0 1 (high) unmasked message buffer dn = 1 and ows = 1 dn = 0 2 message buffer linked to mask 1 dn = 1 and ows = 1 dn = 0 3 message buffer linked to mask 2 dn = 1 and ows = 1 dn = 0 4 message buffer linked to mask 3 dn = 1 and ows = 1 dn = 0 5 (low) message buffer linked to mask 4 dn = 1 and ows = 1 chapter 15 can controller 700 user?s manual u17830ee1v0um00 15.9.2 receive history list function the receive history list (rhl) function records in the re ceive history list the number of the receive message buffer in which each data frame or remote frame was receiv ed and stored. the rhl c onsists of storage elements equivalent to up to 23 messages, the last in-message pointe r (lipt) with the correspondi ng cnlipt register and the receive history list get pointer (rgpt) with the corresponding cnrgpt register. the rhl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlipt register holds the contents of the rhl element i ndicated by the value of the lipt pointer minus 1. by reading the cnlipt register, therefore, the number of t he message buffer that received and stored a data frame or remote frame first can be checked. the lipt pointer is utilized as a write pointer that indi cates to what part of the rhl a message buffer number is recorded. any time a dat a frame or remote frame is received and stored, the corresponding message buffer number is recorded to the rhl element indicated by the lipt pointer. each time recording to the rhl has been completed; the lipt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the rgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the rhl. this pointer indicates the first rhl element that the cpu has not read yet. by readi ng the cnrgpt register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. each time a message buffer number is read from the cnrgpt regist er, the rgpt pointer is automatically incremented. if the value of the rgpt pointer matc hes the value of the lipt pointer, the rhpm bit (receive history list pointer match) of the cnrgpt register is set to 1. this i ndicates that no message buffer num ber that has not been read remains in the rhl. if a new message buffer number is re corded, the lipt pointer is incremented and because its value no longer matches the value of t he rgpt pointer, the rhpm bit is cleared. in other words, the numbers of the unread message buffers exist in the rhl. if the lipt pointer is incremented and matches the value of the rgpt point er minus 1, the rovf bit (receive history list overflow) of the cnrgpt regist er is set to 1. this indicates that the rhl is full of numbers of message buffers that have not been read. when further message re ception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the new message. after the rovf bit has been set (1), therefor e, the recorded message buffer numbers in the rhl do not completely reflect the chronological order. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 701 user?s manual u17830ee1v0um00 figure 15-29. receive history list 23 1 2 3 4 5 6 7 receive history list (rhl) 23 1 2 3 4 5 6 7 receive history list (rhl) last in-message pointer (lipt) 23 0 1 2 3 4 5 6 7 23 1 2 3 4 5 6 7 0 when rhl is full rovf is set. : : : when message buffer 6 is read : : : : : : 22 0 0 22 22 22 message buffer 7 message buffer 2 message buffer 9 message buffer 6 if message is stored in message buffers 3, 4, and 8 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 receive history list get pointer (rgpt) receive history list (rhl) message buffer 1 message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 message buffer 9 receive history list get pointer (rgpt) last in-message pointer (lipt) lipt is locked. receive history list get pointer (rgpt) receive history list get pointer (rgpt) last in-message pointer (lipt) message buffer 3 message buffer 9 message buffer 7 message buffer 5 message buffer 3 message buffer 4 message buffer 8 message buffer 2 message buffer 9 receive history list (rhl) when rovf = 1, message buffer number is stored (overwritten) to element indicated by lipt-1. last in-message pointer (lipt) when message buffer 3 receives and stores more messages chapter 15 can controller 702 user?s manual u17830ee1v0um00 15.9.3 mask function it can be defined whether masking of the identifier that is set to a message buffer is linked with another message buffer. by using the mask function, the identifier of a messa ge received from the can bus can be compared with the identifier set to a message buffer in advance. regardless of whether the masked id is set to 0 or 1, the received message can be stored in the defined message buffer. while the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding ident ifier bit in the message buffer. however, this comparison is performed for any bi t whose value is defined as 0 by the mask. for example, let us assume that all messages that have a standard-format id, in which bits id27 to id25 are 0 and bits id24 and id22 are 1, are to be stored in message bu ffer 14. the procedure for this example is shown below. <1> identifier to be stored in message buffer id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x x = don?t care <2> identifier to be configured in message buffer 14 (example) (using cann message id registers l14 and h14 (cnmidl14 and cnmidh14)) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 x x x x x x x x x x x id6 id5 id4 id3 id2 id1 id0 x x x x x x x id with id27 to id25 cleared to 0 and id24 and id22 set to 1 is registered (initialized) to message buffer 14. remark message buffer 14 is set as a standard format id entifier that is linked to mask 1 (mt[2:0] of cnmconf14 register are set to 010b). chapter 15 can controller 703 user?s manual u17830ee1v0um00 <3> mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 1 0 0 0 0 1 0 1 1 1 1 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 1 1 1 1 1 1 1 1 1 1 1 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1 1 1 1 1 1 1 1: not compared (masked) 0: compared the cmid27 to cmid24 and cmid22 bits are cleared to 0, and the cmid28, cmid23, and cmid21 to cmid0 bits are set to 1. chapter 15 can controller 704 user?s manual u17830ee1v0um00 15.9.4 multi buffer rece ive block function the multi buffer receive block (mbrb) function is used to store a block of data in two or more message buffers sequentially with no cpu interaction, by setting the same id to two or more message buffers with the same message buffer type. suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same id is set to each message buffer. if the firs t message whose id matches an id of the message buffers is received, it is stored in message buffer 10. at this point, the dn bit of message buffer 10 is set, prohibiting overwriting the message buffer when subsequent messages are received. when the next message with a matching id is received, it is received and stored in message buffer 11. each time a message with a matching id is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. even when a data block co nsisting of multiple messages is re ceived, the messages can be stored and received without overwriting the prev iously received matching-id data. whether a data block has been received and stored can be checked by setting the ie bit of the cnmctrlm register of each message buffer. fo r example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. the ie bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the ie bit in message buffer k-1 is set to 1 (interrupts enabled). in this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that mbrb has become full. alternatively, by clearing the ie bit of message buffers 0 to (k-3) and setting the ie bit of message buffer k-2, a warning that mbrb is about to overflow can be issued. the basic conditions of storing rece ive data in each message buffer for the mbrb are the same as the conditions of storing data in a single message buffer. cautions 1. mbrb can be configured for each of th e same message buffer types. therefore, even if a message buffer of another mbrb whose id ma tches but whose message buffer type is different has a vacancy, the r eceived message is not stored in that message buffer, but instead discarded. 2. mbrb does not have a ring buffer structure. therefore, after a message is stored in the message buffer having the highest number in the mbrb configuration, a newly received message will not be stored in the message buffe r having the lowest message buffer number. 3. mbrb operates based on the reception and storage conditions; there are no settings dedicated to mbrb, such as func tion enable bits. by setting the same message buffer type and id to two or more message buffe rs, mbrb is automati cally configured. 4. with mbrb, ?matching id? means ?matching id after mask?. even if the id set to each message buffer is not the same, if the id that is masked by the mask register matches, it is considered a matching id and the buffer that has this id is treated as the storage destination of a message. 5. the priority between mbrbs is mentione d in the table of 15.9.1 message reception. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 705 user?s manual u17830ee1v0um00 15.9.5 remote frame reception in all the operation modes, when a remote frame is received , the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. ? used as a message buffer (ma0 bit of cnmconfm register set to 1b.) ? set as a transmit message buffer (mt[2:0] bits in cnmconfm register set to 000b) ? ready for reception (rdy bit of cnmctrlm register set to 1.) ? set to transmit message (rtr bit of cnmconfm register is cleared to 0.) ? transmission request is not set. (trq bit of cnmctrlm register is cleared to 1.) upon acceptance of a remote frame, the following actions are executed if the id of the received remote frame matches the id of a message buffer that satisfies the above conditions. ? the dlc[3:0] bit string in the cnmdlcm re gister stores the received dlc value. ? cnmdata0m to cnmdata7m in the data area are not updated (data before reception is saved). ? the dn bit of the cnmctrlm register is set to 1. ? the cints1 bit of the cnints register is set to 1 (if the ie bit in the cnmctrlm register of the message buffer that receives and stores the frame is set to 1). ? the receive completion interrupt (int recn) is output (if the ie bit in t he cnmctrlm register of the message buffer that receives and stores the frame is set to 1 and if the cie1 bit of the cnie register is set to 1). ? the message buffer number is recorded in the receive history list. caution when a message buffer is searched for receiving and storing a remote frame, overwrite control by the ows bit of the cnmconfm register of the message buffer and the dn bit of the cnmctrlm register are not affected. if more than one transmit me ssage buffer has the same id and the id of the received remote frame matches that id, the remote frame is stor ed in the transmit messag e buffer with the lowest message buffer number. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 706 user?s manual u17830ee1v0um00 15.10 message transmission 15.10.1 message transmission in all the operation modes, if the trq bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to tr ansmit a message is searched. ? used as a message buffer (ma0 bit of cnmconfm register set to 1b.) ? set as a transmit message buffer (mt[2:0] bits of cnmconfm register set to 000b.) ? ready for transmission (rdy bit of cnmctrlm register set to 1.) the can system is a multi-master communication system. in a system like this, the priority of message transmission is determined based on message identifiers (ids). to facilitate transmission processing by software when there are several messages awaiting transmission, t he can module uses hardware to check the id of the message with the highest priority and automatically identifi es that message. this elim inates the need for software- based priority control. transmission priority is controlled by the identifier (id). figure 15-30. message processing example message no. the can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 after the transmit message search, the transmit message wit h the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the trq bit set to 1 in advance) is transmitted. if a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. if the new transmission request has a higher priority, it is transmitted, unless transmi ssion of a message with a low priority has already started. if transmission of a message with a low priority has already started, however, the new transmission request is transmitted later. the highest priority is determined according to the following rules. chapter 15 can controller 707 user?s manual u17830ee1v0um00 priority conditions description 1 (high) value of first 11 bits of id [id28 to id18]: the message frame with the lowest value represented by the first 11 bits of the id is transmitted first. if the value of an 11- bit standard id is equal to or smaller than the first 11 bits of a 29-bit extended id, the 11-bit standard id has a higher priority than a message frame with a 29-bit extended id. 2 frame type a data frame with an 11-bit standard id (rtr bit is cleared to 0) has a higher priority than a remote frame with a standard id and a message frame with an extended id. 3 id type a message frame with a standard id (ide bit is cleared to 0) has a higher priority than a message frame with an extended id. 4 value of lower 18 bits of id [id17 to id0]: if one or more transmission-pending ex tended id message frame has equal values in the first 11 bits of the id and the same frame type (equal rtr bit values), the message frame with the lowest value in the lower 18 bits of its extended id is transmitted first. 5 (low) message buffer number if two or more message buffers request tr ansmission of message frames with the same id, the message from the message buffer with the lowest message buffer number is transmitted first. remarks 1. if the automatic block transmission request bit abttrg is set to 1 in the normal operation mode with abt, the trq bit is set to 1 only for one message buffer in the abt message buffer group. if the trq bit is set to 1 for this buffer and fo r the message buffers that do not belong to the abt message buffer group, a conflict occurs. when messages are successively transmitted from the automatic block transmission area (message buffers 0 to 7), therefore, the priority of the transmission id is not searched, and the message s are transmitted sequentially, starting from the buffer with the lowest number. however, the pr iority among automatic block transmission messages and message buffers other than those in the automat ic block transmission area is in compliance with the above rule. upon successful transmission of a message fr ame, the following operations are performed. ? the trq flag of the corresponding transmit me ssage buffer is automatically cleared to 0. ? the transmission completion status bit cints0 of th e cnints register is set to 1 (if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). ? an interrupt request signal intrrx1 is output (if the cie0 bit of the cnie regi ster is set to 1 and if the interrupt enable bit (ie) of the corres ponding transmit message buffer is set to 1). 2. n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 708 user?s manual u17830ee1v0um00 15.10.2 transmit history list function the transmit history list (thl) function records in the tr ansmit history list the number of the transmit message buffer in which each data frame or remote frame was received an d stored. the thl consists of storage elements equivalent to up to seven messages, the last out-message pointer (lopt) with the corresponding cnlopt register, and the transmit history list get pointer (tgpt) with the corresponding cntgpt register. the thl is undefined immediately after t he transition of the can m odule from the initialization mode to one of the operation modes. the cnlopt register holds t he contents of the thl element indicated by the value of the lopt pointer minus 1. by reading the cnlopt register, therefor e, the number of the message buffer that transmitted a data frame or remote frame first can be checked. the lopt poi nter is utilized as a write pointer that indicates to what part of the thl a message buffer number is reco rded. any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the thl element indica ted by the lopt pointer. each time recording to the thl has been completed; the lopt point er is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the tgpt pointer is utilized as a read pointer that reads a recorded me ssage buffer number from the thl. this pointer indicates the first thl element that the cpu has not yet read. by reading the cn tgpt register by software, the number of a message buffer that has completed transmissi on can be read. each time a message buffer number is read from the cntgpt register, the tg pt pointer is automatically incremented. if the value of the tgpt pointer matches the value of the lopt pointer, the th pm bit (transmit history list pointer match) of the cntgpt register is set to 1. this indicates that no messag e buffer numbers that have not been read remain in the thl. if a new message buffer number is re corded, the lopt pointer is incremented and because its value no longer matches the value of the tgpt pointer, the th pm bit is cleared. in other words, the numbers of the unread message buffers exist in the thl. if the lopt pointer is incremented and matches the value of the tgpt point er minus 1, the tovf bit (receive history list overflow) of the cntgpt regi ster is set to 1. this indicates that the thl is full of message buffer numbers that have not been read. if a new message is received and stored, the message buffer number recorded last is overwritten by the number of the message buffer that received and stored the new message. after the tovf bit has been set (1), therefore, the recorded message buffer numbers in the thl do not completely reflect the chronological order. chapter 15 can controller 709 user?s manual u17830ee1v0um00 figure 15-31. transmit history list 1 2 3 4 5 6 7 transmit history list (thl) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 when thl is full tovf is set. 0 0 0 when tovf = 1, message buffer number is stored (overwritten) to element indicated by lopt-1. 0 last out-message pointer (lopt) message buffer 7 message buffer 2 message buffer 9 message buffer 6 transmit history list get pointer (tgpt) transmit history list (thl) message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 when message buffer 6 is read if transmission from message buffers 3 and 4 is completed last out-message pointer (lopt) transmit history list get pointer (tgpt) transmit history list(thl) transmit history list get pointer (tgpt) last out-message pointer (lopt) lopt is locked. transmit history list get pointer (tgpt) transmit history list (thl) when transmission from message buffer 3 is completed. last out-message pointer (lopt) message buffer 3 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 chapter 15 can controller 710 user?s manual u17830ee1v0um00 15.10.3 automatic blo ck transmission (abt) the automatic block transmission (abt) function is used to transmit two or more data frames successively with no cpu interaction. the maximum number of transmit messa ge buffers assigned to the abt function is eight (message buffer numbers 0 to 7). by setting opmode[2:0] of the cnctrl register to 010b, ?normal operation mode with automatic block transmission function? (hereafter referred to as abt mode) can be selected. to issue an abt transmission request, define the message buffe rs by software first. set the ma0 bit (1) in all the message buffers used for abt, and define all the buffers as transmit message buffers by setting the mt[2:0] bits to 000b. be sure to set the same id for the message buffers for atb even when that id is being used for all the message buffers. to use two or more ids, set the id of each message buffer by using the cnmidlm and cnmidhm registers. set the cnmdlcm and cnmdata0m to cnmdata7 m registers before issuing a transmission request for the abt function. after initialization of message buffers for abt is finished, the rdy bit needs to be set (1). in the abt mode, the trq bit does not have to be manipulated by software. after the data for the abt message buffers has been pr epared, set the abttrg bit to 1. automatic block transmission is then started. when abt is started, the trq bit in the first message buffer (message buffer 0) is automatically set to 1. after transmi ssion of the data of message buffer 0 is fi nished, trq of the next message buffer, message buffer 1, is set automatically. in th is way, transmission is executed successively. a delay time can be inserted by program in the interval in which the transmission requ est (trq) is automatically set while successive transmission is being executed. th e delay time to be inserted is defined by the cngmabtd register. the unit of the delay time is dbt (data bit time). dbt depends on the setting of the cnbrp and cnbtr registers. during abt, the priority of the transmission id is not sear ched. the data of message buffers 0 to 7 is sequentially transmitted. when transmission of t he data frame from message buffer 7 has been completed, the abttrg bit is automatically cleared to 0 and the abt operation is finished. if the rdy bit of an abt message buffer is cleared during abt, no data frame is transmitt ed from that buffer, abt is stopped, and the abttrg bit is cleared. after that, transmission can be resumed from the message buffer where abt stopped, by setting the rdy and abttrg bits to 1 by so ftware. to not resume transmission from the message buffer where abt stopped, the internal abt engine can be re set by setting the abtclr bit to 1 while abt mode is stopped and abttrg is cleared to 0. in this case, transmi ssion is started from message buffer 0 if the abtclr bit is cleared to 0 and then the abttrg bit is set to 1. an interrupt can be used to check if data frames have b een transmitted from all the message buffers for abt. to do so, the ie bit of the cnmctrlm register of each me ssage buffer except the last message buffer needs to be cleared (0). if a transmit message buffer other than those used by the abt function (message buffer 8 to 31) is assigned to a transmit message buffer, the priority of the message to be tr ansmitted is determined by the priority of the transmission id of the abt message buffer whose transmission is currently held pending and the transmission id of the message buffers other than those us ed by the abt function. transmission of a data frame from an abt message buffer is not recorded in the transmit history list (thl). chapter 15 can controller 711 user?s manual u17830ee1v0um00 cautions 1. set the abtclr bit to 1 while the abttrg bi t is cleared to 0. if the abtclr bit is set to 1 while the abttrg bit is set to 1, the subsequent operation is not guaranteed. 2. if the automatic bl ock transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared immediately after th e processing of the clearing request is completed. 3. do not set the abttrg bit in the initialization mode. if the abttrg bit is set in the initialization mode, the proper operation is not guaranteed afte r the mode is changed from the initialization mode to the abt mode. 4. do not set trq of the abt message buffers to 1 by software in the normal operation mode with abt. otherwise, the operation is not guaranteed. 5. the cngmabtd register is used to set the delay time that is inserte d in the period from completion of the preceding abt message to setting of th e trq bit for the next abt message when the transmissi on requests are set in the order of message numbers for each message for abt that is successively transmitted in th e abt mode. the timing at which the messages are actually transmitte d onto the can bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other th an the abt messages (message buffer 8 to 31). 6. if a transmission request is made for a message other than an abt message and if no delay time is inserted in the interval in which transmission requests for abt are automatically set (cngmabtd = 00h), messages other than abt messages are transmitted. at this time , transmission does not depend on the priority of the abt message. 7. do not clear the rdy bit to 0 when abttrg = 1. 8. if a message is received from another node in the normal opera tion mode with abt, the message may be transmitted after the time of one frame has el apsed (when cngmabtd register = 00h). chapter 15 can controller 712 user?s manual u17830ee1v0um00 15.10.4 transmission abort process (1) transmission abort in normal operation mode the user can clear the trq bit of the cnmctrlm regi ster to 0 to abort a transmission request. the trq bit will be cleared immediately if the abort was successful. whether the transmission wa s successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt r egister, which indicate the transmission status on the can bus (for details, refer to the processing in figure 15-44 ). (2) transmission abort process except for abt tran smission in normal operati on mode with automatic block transmission (abt) the user can clear the abttrg bit of the cngmabt register to 0 to abort a transmission request. after checking the abttrg bit of the cngmabt register = 0, clear the trq bit of the cnmctrlm register to 0. the trq bit will be cleared immediately if the abor t was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of t he cnctrl register and the cntgpt register, which indicate the transmission status on the ca n bus (for details, refer to the processing in figure 15-46). (3) transmission abort in no rmal operation mode with automa tic block transmission (abt) to abort abt that is already started, clear the abttrg bit of the cngmabt r egister to 0. in this case, the abttrg bit remains 1 if an abt message is curr ently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. this aborts abt. if the last transmission (before abt) was successful, t he normal operation mode with abt is left with the internal abt pointer pointing to the next message buffer to be transmitted. in the case of an erroneous transmissi on, the position of the internal abt pointer depends on the status of the trq bit in the last transmi tted message buffer. if the trq bit is se t to 1 when clearing the abttrg bit is requested, the internal abt pointer points to the last transmitted mess age buffer (for details, refer to the process in figure 15-45 ). when the normal operation mode with abt is resumed afte r abt has been aborted and abttrg is set to 1, the next abt message buffer to be transmitted can be determined from the following table. status of trq of abt message buffer abort after succe ssful transmission abort a fter erroneous transmission set (1) next message buffer in the abt area note same message buffer in the abt area cleared (0) next message buffer in the abt area note next message buffer in the abt area note note the above resumption operation can be performed only if a message buffer ready for abt exists in the abt area. for example, an abort request that is issu ed while abt of message buffer 7 is in progress is regarded as completion of abt, rather than abor t, if transmission of message buffer 7 has been successfully completed, even if abttrg is cleared to 0. if the rdy bit in the next message buffer in the abt area is cleared to 0, the intern al abt pointer is retained, but the resumption operation is not performed even if abttrg is set to 1, and abt ends immediately. 15.10.5 remote frame transmission remote frames can be transmitted only from transmit mess age buffers. set whether a data frame or remote frame is transmitted via the rtr bit of the cnmconfm register. setting (1) the rt r bit sets remote frame transmission. chapter 15 can controller 713 user?s manual u17830ee1v0um00 15.11 power saving modes 15.11.1 can sleep mode the can sleep mode can be used to set the can contro ller to standby mode in order to reduce power consumption. the can module can ent er the can sleep mode from all operati on modes. release of the can sleep mode returns the can module to exactly the same oper ation mode from which the can sleep mode was entered. in the can sleep mode, the can module does not transmit messages, even when transmission requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition request by writing 01b to the psmode[1:0] bits of the cnctrl register. this transition request is only acknowledged only under the following conditions. (i) the can module is already in one of the following operation modes ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode ? can stop mode in all the above operation modes (ii) the can bus state is bus idle (the 4th bit in the interframe space is recessive) note note if the can bus is fixed to dominant, the request for transition to the can sleep mode is held pending. (iii) no transmission request is pending if any one of the conditions mentioned above is not met, the can module will operate as follows. ? if the can sleep mode is requested from the initializati on mode, the can sleep mode transition request is ignored and the can module remains in the initialization mode. ? if the can bus state is not bus idle (i.e., the can bus state is either transmitting or receiving) when the can sleep mode is requested in one of the operatio n modes, immediate transition to the can sleep mode is not possible. in this case, the can sleep mode transition request has to be held pending until the can bus state becomes bus idle (t he 4th bit in the interframe space is recessive). in the time from the can sleep mode request to successful transition, the psmode[1:0] bits remain 00b. when the module has entered the can sleep mode, psmode[1:0] are set to 01b. ? if a request for transition to the initialization mode and a request for transition to the can sleep mode are made at the same time while the can module is in one of the operation modes, the request for the initialization mode is enabled. t he can module enters the initialization mode at a predetermined timing. at this time, the can sleep mode request is not held pending and is ignored. ? if a can sleep mode request is pending waiting for the can bus state to bec ome bus idle while the can module is in one of the operat ion modes, and if a request for transit ion to the initialization mode is made, the pending can sleep mode request becomes disabled, and only the initialization mode request is enabled (in this case, the can sleep mode request continues to be held pending). ? if the can sleep mode transition request is made while an initialization mode transition request is held pending waiting for completion of communication in one of the operation modes, the can sleep mode transition request is ignored and only the initializa tion mode transition request remains valid (in this case, the can sleep mode request continues to be held pending). chapter 15 can controller 714 user?s manual u17830ee1v0um00 (2) status in can sleep mode the can module is in one of the following states after it enters the can sleep mode. ? the internal operating clock is stopped a nd the power consumption is minimized. ? the function to detect the falling edge of the can re ception pin (crxdn) remains in effect to wake up the can module from the can bus. ? to wake up the can module from the cpu, data can be written to psmode[1:0] of the can module control register (cnctrl), but nothing can be writt en to other can module registers or bits. ? the can module registers can be read, exc ept for cnlipt, cnrgpt, cnlopt, and cntgpt. ? the can message buffer registers cannot be written or read. ? a request for transition to the initializati on mode is not acknowledged and is ignored. (3) releasing can sleep mode the can sleep mode is releas ed by the following events. ? when the cpu writes 00b to the psmode[ 1:0] bits of the cnctrl register ? a falling edge at the can reception pin (crxdn) (i.e. the can bus level shifts from recessive to dominant) caution if this falling edge is at the sof of a r eceive frame, no receive opera tion, including returning ack, is performed on that frame. no recei ve operation is perfo rmed on the subsequent frames either, unless the clock is supplied to the can macro. after releasing the sleep mode, the can module return s to the operation mode from which the can sleep mode was requested and the psmode[1:0] bits of the cnctrl register are rese t to 00b. if the can sleep mode is released by a change in the can bus state, the cints5 bit of the cnints register is set to 1, regardle ss of the cie bit of the cnie register. after the can module is released from the can sleep mode, it participates in the can bus again by automatically detecting 11 consecutive recessive-level bits on the can bus. when a request for transition to the initialization mode is made while the can module is in the can sleep mode, that request is ignored; the cpu has to be released from sleep mode by software first before entering the initialization mode. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 15.11.2 can stop mode the can stop mode can be used to set the can controller to standby mode to reduce power consumption. the can module can enter the can stop mode only from the ca n sleep mode. release of the can stop mode puts the can module in the can sleep mode. the can stop mode can only be released by writing 01b to the psmode[1:0] bits of the cnctrl register and not by a change in the can bus state. no message is tr ansmitted even when transmission requests are issued or pending. (1) entering can stop mode a can stop mode transition request is issued by writing 11b to the psmode[1:0] bits of the cnctrl register. a can stop mode request is only acknowledged when the ca n module is in the can sleep mode. in all other modes, the request is ignored. chapter 15 can controller 715 user?s manual u17830ee1v0um00 caution to set the can module to the can stop mode , the module must be in the can sleep mode. to confirm that the module is in the sleep m ode, check that psmode[1:0] = 01b, and then request the can stop mode. if a bus change occurs at the can reception pin (crxd) while this process is being performed, the can sleep m ode is automatically released. in this case, the can stop mode transition re quest cannot be acknowledged. (2) status in can stop mode the can module is in one of the following states after it enters the can stop mode. ? the internal operating clock is stopped a nd the power consumption is minimized. ? to wake up the can module from the cpu, data can be written to psmode[1:0] of the can module control register (cnctrl), but nothing can be writt en to other can module registers or bits. ? the can module registers can be read, exc ept for cnlipt, cnrgpt, cnlopt, and cntgpt. ? the can message buffer registers cannot be written or read. ? an initialization mode transition reques t is not acknowledged and is ignored. (3) releasing can stop mode the can stop mode can only be released by writing 01b to the psmode[1:0] bits of the cnctrl register. when the initialization mode is reques ted while the can module is in t he can stop mode, that request is ignored; the cpu has to release the stop mode a nd subsequently can sleep mode before entering the initialization mode. 15.11.3 example of us ing power saving modes in some application systems, it may be necessary to plac e the cpu in a power saving mode to reduce the power consumption. by using the power saving mode specific to the can module and the power saving mode specific to the cpu in combination, the cpu can be woken up from the power saving status by the can bus. here is an example of using the power saving modes. first, put the can module in the ca n sleep mode (psmode = 01b). next, put the cpu in the power saving mode. if an edge transition from recessive to dominant is detected at the can reception pin (crxdn) in this status, the cints5 bit in the can module is set to 1. if the cie5 bit of the cnctrl r egister is set to 1, a wakeup interrupt (intwup) is generated. the can module is automatically released from the can sleep mode (psmode = 00b) and returns to the normal operation mode. the cpu, in response to intwup, can release its own power saving mode and return to the normal operation mode. to further reduce the power consumption of the cpu, the internal clocks, in cluding that of the can module, may be stopped. in this case, the operating clock supplied to the can module is stopped afte r the can module is put in the can sleep mode. then the cpu enters a power saving m ode in which the clock supplied to the cpu is stopped. if an edge transition from recessive to dominant is detected at the can reception pin (crxdn ) in this status, the can module can set the cints5 bit to 1 and generate the wakeup in terrupt (intwup) even if it is not supplied with the clock. the other functions, howeve r, do not operate because clock supply to the can module is stopped, and the module remains in the can sleep mode. the cpu, in re sponse to intwup, releases its power saving mode, resumes supply of the internal clocks, including the clock to the can module, after the oscillation stabilization time has elapsed, and starts instruction ex ecution. the can module is immediat ely released from the can sleep mode when clock supply is resumed, and returns to the normal operation mode (psmode = 00b). chapter 15 can controller 716 user?s manual u17830ee1v0um00 15.12 interrupt function the can module provides 6 different interrupt sources. the occurrence of these interrupt source s is stored in interrupt status regist ers. four separate interrupt request signals are generated from the six interrupt sources. when an interrupt request signal that corresponds to two or more interrupt sources is generated, the in terrupt sources can be identified by usi ng an interrupt status register. after an interrupt source has occurred, the corresponding inte rrupt status bit must be cleared to 0 by software. table 15-20. list of can module interrupt sources interrupt status bit interrupt enable bit no. name register name register interrupt request signal interrupt source description 1 cints0 cnints cie0 note cnie intcntrx message frame successfu lly transmitted from message buffer m 2 cints1 cnints cie1 note cnie intcnrec valid message frame reception in message buffer m 3 cints2 cnints cie2 cnie can module error state interrupt (supplement 1) 4 cints3 cnints cie3 cnie can module protocol error interrupt (supplement 2) 5 cints4 cnints cie4 cnie intcnerr can module arbitration loss interrupt 6 cints5 cnints cie5 cnie intcnwup can module wakeup interrupt from can sleep mode (supplement 3) note the ie bit (message buffer interrupt enable bit) in the cnmctrl register of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process. supplements 1. this interrupt is generated when the transmission/re ception error counter is at the warning level, or in the error passive or bus-off state. 2. this interrupt is generated when a stuff error, form error, ack error, bit error, or crc error occurs. 3. this interrupt is generated when the can m odule is woken up from the can sleep mode because a falling edge is detected at the can rec eption pin (can bus transition from recessive to dominant). remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 717 user?s manual u17830ee1v0um00 15.13 diagnosis functions and special operational modes the can module provides a receive- only mode, single-shot mode, and self-test mode to support can bus diagnosis functions or the operation of special can communication methods. 15.13.1 receive-only mode the receive-only mode is used to monitor receive mess ages without causing any interf erence on the can bus and can be used for can bus analysis nodes. for example, this mode can be used for automatic baud- rate detection. the baud rate in the can module is changed until ?valid reception? is detect ed, so that the baud rates in the module match (?valid reception? means a message frame has been received in the can protocol laye r without occurrence of an e rror and with an appropriate ack between nodes connected to the can bus). a valid rec eption does not require mess age frames to be stored in a receive message buffer (data frames) or transmit message buffe r (remote frames). the event of valid reception is indicated by setting the valid bit of the cnctrl register (1). figure 15-32. can module terminal co nnection in receive-only mode can macro rx tx ctxdn crxdn fixed to the recessive level chapter 15 can controller 718 user?s manual u17830ee1v0um00 in the receive-only mode, no message frames can be trans mitted from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are held pending. in the receive-only mode, the can transmission pin (ctxdn) in the can module is fixed to the recessive level. therefore, no active error flag can be transmitted from the can module to the can bus even when a can bus error is detected while receiving a mess age frame. since no transmission can be issued from the can module, the transmission error counter tec is never updated. therefore, a can module in the receive-only mode does not enter the bus-off state. furthermore, ack is not returned to the can bus in th is mode upon the valid reception of a message frame. internally, the local node recognizes that it has transmitted ack. an overload frame cannot be transmitted to the can bus. caution if only two can nodes are c onnected to the can bus and one of them is operating in the receive- only mode, there is no ack on the can bus. due to the missing ack, the tr ansmitting node will transmit an active error flag, and repeat tran smitting a message frame. the transmitting node becomes error passive after transm itting the message frame 16 ti mes (assuming that the error counter was 0 in the beginning an d no other errors have occurre d). when the message frame is transmitted for the 17th time, the transmitting node generates a passive error flag. the receiving node in the receive-only mode detects the first va lid message frame at this point, and the valid bit is set to 1 for the first time. 15.13.2 single-shot mode in the single-shot mode, automatic re-t ransmission as defined in the can protoc ol is switched off. (according to the can protocol, a message frame transmission that has been aborted by either arbi tration loss or error occurrence has to be repeated without control by software.) the single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the al bit of the cnctrl regi ster. when the al bit is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. if the al bit is set to 1, re-transmission upon error occurrence is disabled, but re- transmission upon arbitration loss is enabled. as a cons equence, the trq bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events. ? successful transmission of the message frame ? arbitration loss while sending the message frame (al bit = 0) ? error occurrence while sending the message frame the events arbitration loss and error occurrence can be dist inguished by checking the cints4 and cints3 bits of the cnints register, and the type of the error can be identified by reading the le c[2:0] bits of the cnlec register. upon successful transmission of the message frame, the tr ansmit completion interrupt bit cints0 of the cnints register is set to 1. if the cie0 bit of the cnie register is set to 1 at this time, an in terrupt request signal is output. the single-shot mode can be used when emulating time-t riggered communication methods (e.g., ttcan level 1). caution the al bit is only valid in single-shot mode. it does not influence the operation of re- transmission upon arbitration loss in the other operation modes. chapter 15 can controller 719 user?s manual u17830ee1v0um00 15.13.3 self-test mode in the self-test mode, message frame transmission and message frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the self-test mode, the can m odule is completely di sconnected from the can bus, but transmission and reception are internally looped back. the can transmi ssion pin (ctxdn) is fixed to the recessive level. if the falling edge on the can reception pin (crxdn) is detected after the can modul e has entered the can sleep mode from the self-test mode, however, the module is released from the can sl eep mode in the same manner as the other operation modes. to keep the m odule in the can sleep mode, use the ca n reception pin (crxdn) as a port pin. figure 15-33. can module terminal connection in self-test mode can macro rx tx ctxdn crxdn fixed to the recessive level chapter 15 can controller 720 user?s manual u17830ee1v0um00 15.14 time stamp function can is an asynchronous, serial protocol. all nodes connect ed to the can bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relati on (i.e., the clocks are asynchronous and may even have different frequencies). in some applications, however, a common time base over the network (= global time base) is needed. in order to build up a global time base, a time stam p function is used. the essential mechan ism of a time stamp function is the capture of timer values triggered by signals on the can bus. 15.14.1 time stamp function the can controller supports t he capturing of timer values triggered by su ccessful reception of a data frame. an on-chip 16-bit capture timer unit in a microcontroller syst em is used in addition to the can controller. the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) for c apturing that is output when a data frame is received from the can controller. the cpu can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the can bus, by reading the captured value. tsout can be selected from the following two event sources and is specified by the tssel bi t of the cnts register. ? sof event (start of frame) (tssel = 0) ? eof event (last bit of end of frame) (tssel = 1) the tsout signal is enabled by setting the t sen bit of the cnts register to 1. figure 15-34. timing diagram of capture signal tsout t tsout sof sof sof sof tsout toggles its level upon occurrence of the selected event during data frame reception (in the above timing diagram, the sof is used as the trigger event source). to capture a timer value by using tsout, the capture timer unit must detect the capture signal at both the rising edge and falling edge. this time stamp function is controlled by the tslock bi t of the cnts register. when tslock is cleared to 0, tsout toggles upon occurrence of the selected event. if ts lock is set to 1, tsout toggles upon occurrence of the selected event, but the toggle is stopped as the tsen bit is automatica lly cleared to 0 when a data frame is received and stored in message buffer 0. this suppresses the subsequent toggle occurrenc e by tsout, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. chapter 15 can controller 721 user?s manual u17830ee1v0um00 caution the time stamp function us ing tslock stops toggle of tsout by receiving a data frame in message buffer 0. therefore, message buffer 0 mu st be set as a receive message buffer. since a receive message buffer cannot r eceive a remote frame, toggle of tsout cannot be stopped by reception of a remote frame. toggle of tsout do es not stop when a data frame is received in a message buffer other th an message buffer 0. for these reasons, a data frame ca nnot be received in message buffer 0 when the can module is in the normal operation mode with abt, because message buffer 0 must be set as a transmit message buffer. in this operati on mode, therefore, the function to stop toggle of tsout by tslock cannot be used. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 chapter 15 can controller 722 user?s manual u17830ee1v0um00 15.15 baud rate settings 15.15.1 bit rate setting conditions make sure that the settings are within the range of limit values for ensuring co rrect operation of the can controller, as follows. (a) 5tq spt (sampling point) 17 tq spt = tseg1 + 1 (b) 8 tq dbt (data bit time) 25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt (c) 1 tq sjw (synchronization jump width) 4tq sjw dbt ? spt (d) 4 tseg1 16 [3 setting value of tseg1[3:0] 15] (e) 1 tseg2 8 [0 setting value of tseg2[2:0] 7] remark tq = 1/f tq (f tq : can protocol layer basic system clock) tseg1[3:0] (bits 3 to 0 of ca nn bit rate register (cnbtr)) tseg2[2:0] (bits 10 to 8 of ca nn bit rate register (cnbtr)) table 15-21 shows the combinations of bi t rates that satisfy the above conditions. chapter 15 can controller 723 user?s manual u17830ee1v0um00 table 15-21. settable bit ra te combinations (1/3) valid bit rate setting cnbtr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg1[3:0] tseg2[2:0] sampling point (unit %) 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 chapter 15 can controller 724 user?s manual u17830ee1v0um00 table 15-21. settable bit ra te combinations (2/3) valid bit rate setting cnbtr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg1[3:0] tseg2[2:0] sampling point (unit %) 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 chapter 15 can controller 725 user?s manual u17830ee1v0um00 table 15-21. settable bit ra te combinations (3/3) valid bit rate setting cnbtr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg1[3:0] tseg2[2:0] sampling point (unit %) 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 note 1 2 2 2 0011 001 71.4 7 note 1 4 1 1 0100 000 85.7 6 note 1 1 2 2 0010 001 66.7 6 note 1 3 1 1 0011 000 83.3 5 note 1 2 1 1 0010 000 80.0 4 note 1 1 1 1 0001 000 75.0 note setting with a dbt value of 7 or less is valid only wh en the value of the cnbrp r egister is other than 00h. caution the values in table 15-21 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 726 user?s manual u17830ee1v0um00 15.15.2 representative examples of baud rate settings tables 15-22 and 15-23 show representative examples of baud rate settings. table 15-22. representative examples of baud rate settings (f canmod = 8 mhz) (1/2) valid bit rate setting (unit: kbps) cnbtr register setting value set baud rate value (unit: kbps) division ratio of cnbrp cnbrp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] sampling point (unit: %) 1000 1 00000000 8 1 1 3 3 0011 010 62.5 1000 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 caution the values in table 15-22 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. chapter 15 can controller 727 user?s manual u17830ee1v0um00 table 15-22. representative examples of baud rate settings (f canmod = 8 mhz) (2/2) valid bit rate setting (unit: kbps) cnbtr register setting value set baud rate value (unit: kbps) division ratio of cnbrp cnbrp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] sampling point (unit: %) 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3 100 8 00000111 10 1 3 3 3 0101 010 70.0 100 8 00000111 10 1 5 2 2 0110 001 80.0 100 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 caution the values in table 15-22 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 728 user?s manual u17830ee1v0um00 table 15-23. representative examples of baud rate settings (f canmod = 16 mhz) (1/2) valid bit rate setting (unit: kbps) cnbtr register setting value set baud rate value (unit: kbps) division ratio of cnbrp cnbrp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] sampling point (unit: %) 1000 1 00000000 16 1 1 7 7 0111 110 56.3 1000 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 caution the values in table 15-23 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 729 user?s manual u17830ee1v0um00 table 15-23. representative examples of baud rate settings (f canmod = 16 mhz) (2/2) valid bit rate setting (unit: kbps) cnbtr register setting value set baud rate value (unit: kbps) division ratio of cnbrp cnbrp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] sampling point (unit: %) 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0 83.3 8 00000111 24 1 7 8 8 1110 111 66.7 83.3 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 caution the values in table 15-23 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) chapter 15 can controller 730 user?s manual u17830ee1v0um00 15.16 operation of can controller remark . n = 0 ( pd70f3231, pd70f3232, pd70f3233) n = 0, 1( pd70f3234, pd70f3235, pd70f3236, pd70f3237) n = 0 to 3 ( pd70f3238, pd70f3239) m = 0 to 31 figure 15-35. initialization start set cngmcs register. set cngmctrl register (set gom = 1). set cnie register. set cnmask register. end initialize message buffers. set cnbrp register, cnbtr register. set cnctrl register (set opmode). remark opmode: normal operation mode, normal operati on mode with abt, receive-only mode, single- shot mode, self-test mode chapter 15 can controller 731 user?s manual u17830ee1v0um00 figure 15-36. re-initialization start set cnbrp register, cnbtr register. set cnie register. set cnmask register. set cnctrl register. (set opmode) end clear opmode. init mode? no yes set ccerc bit. set ccerc = 1 clear ccerc = 0 yes no initialize message buffers. cnerc and cninfo register clear? caution after setting the can module to the initializ ation mode, avoid setting the module to another operation mode immediately after. if it is necessary to immediat ely set the module to another operation mode, be sure to access registers other than the cnctrl and cngmctrl registers (e.g., set a message buffer). remark opmode: normal operation mode, normal operati on mode with abt, receive-only mode, single- shot mode, self-test mode chapter 15 can controller 732 user?s manual u17830ee1v0um00 figure 15-37. message buffer initialization start set cnmconfm register. end rdy = 1? no yes clear rdy bit. set rdy bit = 0 clear rdy bit = 1 rdy = 0? set cnmidhm register, cnmidlm re g ister transmit message buffer? clear cnmdatam register. set cnmctrlm register. set rdy bit. set rdy bit = 1 clear rdy bit = 0 set cnmdlcm register. no yes yes no cautions 1. before a message buffer is in itialized, the rdy bit must be cleared. 2. make the following settings for message buffers not u sed by the application. ? clear the rdy, trq, and dn bits of the cnmctrlm register to 0. ? clear the ma0 bit of the cnmconfm register to 0. chapter 15 can controller 733 user?s manual u17830ee1v0um00 figure 15-38 shows the processing for a receive message buffer (mt[2:0] bits of cnmconfm register = 001b to 101b). figure 15-38. message buffer redefinition start set message buffers end rdy = 1? no ye s clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? rstat = 0 or valid = 1? note no clear valid bit cnctrlclear_valid =1 set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s ye s no wait for 4 can data bits start set message buffers end rdy = 1? no ye s clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? rstat = 0 or valid = 1? note no clear valid bit cnctrlclear_valid =1 set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s ye s no wait for 4 can data bits note if redefinition is performed during a message recept ion, confirm that a message is being received because the rdy bit must be set after a message is completely received. chapter 15 can controller 734 user?s manual u17830ee1v0um00 figure 15-39 shows the processing for a transmit message buffe r during transmission (mt2 to mt0 bits of cnmconfm register = 000b). figure 15-39. transmitting m essage buffer redefinition start end rdy = 0? no ye s data frame or remote frame? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers remote frame data frame transmit abort process clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 transmit? set trq bit cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 ye s wait for 1can data bits no start end rdy = 0? no ye s data frame or remote frame? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers remote frame data frame transmit abort process clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 transmit? set trq bit cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 ye s wait for 1can data bits no chapter 15 can controller 735 user?s manual u17830ee1v0um00 figure 15-40 shows the processing for a transmit message buffer (mt[2:0] bits of cnmconfm register = 000b). figure 15-40. message transmit pr ocessing (normal operation mode) start end trq = 0? no ye s clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? data frame or remote frame? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set trq bit cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 remote frame data frame start end trq = 0? no ye s clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? data frame or remote frame? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set trq bit cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 remote frame data frame caution the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. chapter 15 can controller 736 user?s manual u17830ee1v0um00 figure 15-41 shows the processing for a transmit message buffer (mt[2:0] bits of cnmconfm register = 000b). figure 15-41. message transmit proces sing (normal operation mode with abt) start set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers end abttrg = 0? no ye s clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s no set abttrg bit cngmabt.set_abttrg = 1 cngmabt.clear_abttrg = 0 set all abt transmit messages? tstat = 0? ye s no ye s no start set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers end abttrg = 0? no ye s clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s no set abttrg bit cngmabt.set_abttrg = 1 cngmabt.clear_abttrg = 0 set all abt transmit messages? tstat = 0? ye s no ye s no remark this processing (normal operation mode with abt) can only be applied to message buffers 0 to 7. for message buffers other than t he abt message buffers, refer to figure 15-40 . caution set (1) abttrg bit after ts tat bit is clear (0) check tstat bit and set abttrg bit, must be processing successively. chapter 15 can controller 737 user?s manual u17830ee1v0um00 figure 15-42. transmission via in terrupt (using cnlopt register) start end clear rdy bit cnmcrtlm.set_rdy = 0 cnmcrtlm.clear_rdy = 1 rdy = 0? data frame or remote frame? set rdy bit cnmcrtlm.set_rdy = 1 cnmcrtlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register, clear rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set trq bit cnmcrtlm.set_trq = 1 cnmcrtlm.clear_trq = 0 remote frame data frame transmit completion interrupt processing read cnlopt register start end clear rdy bit cnmcrtlm.set_rdy = 0 cnmcrtlm.clear_rdy = 1 rdy = 0? data frame or remote frame? set rdy bit cnmcrtlm.set_rdy = 1 cnmcrtlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register, clear rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set trq bit cnmcrtlm.set_trq = 1 cnmcrtlm.clear_trq = 0 remote frame data frame transmit completion interrupt processing transmit completion interrupt processing read cnlopt register caution the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. chapter 15 can controller 738 user?s manual u17830ee1v0um00 figure 15-43. transmission via in terrupt (using cntgpt register) start end tovf = 1? data frame or remote frame? set rdy bit cnmcrtlm.set_rdy = 1 cnmcrtlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set trq bit cnmcrtlm.set_trq = 1 cnmcrtlm.clear_trq = 0 remote frame data frame transmit completion interrupt processing read cntgpt register clear tovf bit cntgpt.clear_tovf = 1 clear rdy bit cnmcrtlm.set_rdy = 0 cnmcrtlm.clear_rdy = 1 rdy = 0? thpm = 1? no ye s no ye s start end tovf = 1? data frame or remote frame? set rdy bit cnmcrtlm.set_rdy = 1 cnmcrtlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set trq bit cnmcrtlm.set_trq = 1 cnmcrtlm.clear_trq = 0 remote frame data frame transmit completion interrupt processing transmit completion interrupt processing read cntgpt register clear tovf bit cntgpt.clear_tovf = 1 clear rdy bit cnmcrtlm.set_rdy = 0 cnmcrtlm.clear_rdy = 1 rdy = 0? thpm = 1? no ye s no ye s caution the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. chapter 15 can controller 739 user?s manual u17830ee1v0um00 figure 15-44. transmi ssion via software polling start end tovf = 1? data frame or remote frame? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm set cnmidlm and cnmidhm registers set trq bit cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 remote frame data frame read cntgpt register clear tovf bit cntgpt.clear_tovf bit = 1 clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? thpm = 1? no ye s no ye s cints0 = 1? no clear cints0 bit cnints.clear_cints0 = 1 ye s start end tovf = 1? data frame or remote frame? set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 ye s no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm set cnmidlm and cnmidhm registers set trq bit cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 remote frame data frame read cntgpt register clear tovf bit cntgpt.clear_tovf bit = 1 clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? thpm = 1? no ye s no ye s cints0 = 1? no clear cints0 bit cnints.clear_cints0 = 1 ye s caution the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. chapter 15 can controller 740 user?s manual u17830ee1v0um00 figure 15-45. transmission abort processi ng (except normal operation mode with abt) start read cnlopt register end no ye s clear trq bit cnmctrlm.set_trq = 0 cnmctrlm.clear_trq = 1 tstat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmit abort request was successful ye s start read cnlopt register end no ye s clear trq bit cnmctrlm.set_trq = 0 cnmctrlm.clear_trq = 1 tstat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmission successful transmit abort request was successful transmit abort request was successful ye s cautions 1. execute transmission request abort pr ocessing by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition request, confirm th at there is no transmission request left using this processing. 3. the tstat bit can be periodica lly checked by a user application. 4. in the aborting the tr ansmission progressing, do not make a new transmission request including other message buffer. chapter 15 can controller 741 user?s manual u17830ee1v0um00 in the normal operation with abt, to abort transmit e xcept transmission with abt, using this processing flow. figure 15-46. transmission abort pr ocessing except for abt transmission (normal operation mode with abt) start read cnlopt register end no ye s clear trq bit cnmctrlm.set_trq = 0 cnmctrlm.clear_trq = 1 tstat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmit abort request was successful ye s no abttrg = 0? clear abttrg bit cngmabt.set_abttrg = 0 cngmabt.clear_abttrg = 1 ye s start read cnlopt register end no ye s clear trq bit cnmctrlm.set_trq = 0 cnmctrlm.clear_trq = 1 tstat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmission successful transmit abort request was successful transmit abort request was successful ye s no abttrg = 0? clear abttrg bit cngmabt.set_abttrg = 0 cngmabt.clear_abttrg = 1 ye s chapter 15 can controller 742 user?s manual u17830ee1v0um00 figure 15-47 (a) shows the processing to skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 15-47. (a) transmission abort pr ocessing (normal operation mode with abt) start end no clear abttrg bit. set abttrg bit = 0 clear abttrg bit = 1 abttrg = 0? transmission start pointer clear? no clear trq bit of message buffer whose transmission was aborted. transmit abort yes set abtclr bit. set abtclr bit = 1 clear abttrg bit = 0 yes cautions 1. do not set any tr ansmission requests while abt tran smission abort processing is in progress. 2. make a can sleep mode/can stop mode tr ansition request afte r abttrg is cleared following the procedure shown in figure 15-47 (a ) or (b). when clearing a transmission request in an area other than the abt area, follow the pr ocedure shown in figure 15-46. chapter 15 can controller 743 user?s manual u17830ee1v0um00 figure 15-47 (b) shows the processing to not skip resu mption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 15-47. (b) transmission request abor t processing (normal operation mode with abt) start end no clear abttrg bit. set abttrg bit = 0 clear abttrg bit = 1 abttrg = 0? transmission start pointer clear? no transmit abort yes set abtclr bit. set abtclr bit = 1 clear abttrg bit = 0 yes clear trq bit of message buffer undergoing transmission. cautions 1. do not set any tr ansmission requests while abt tran smission abort processing is in progress. 2. make a can sleep mode/can stop mode requ est after abttrg is cleared following the procedure shown in figure 15-47 (a) or (b). when clearing a transm ission request in an area other than the abt area, follow the procedure shown in figure 15-46. chapter 15 can controller 744 user?s manual u17830ee1v0um00 figure 15-48. reception via inte rrupt (using cnlipt register) start clear cints1 bit. clear cints1 bit = 1 end no read cnmdataxm, cnmdlcm, cnmidlm, and cnmidhm registers. dn = 0 and muc = 0 note read cnlipt register. yes transmit abort clear dn bit. clear dn bit = 1 note check the muc and dn bits using one read access. chapter 15 can controller 745 user?s manual u17830ee1v0um00 figure 15-49. reception via inte rrupt (using cnrgpt register) start receive completion interrupt clear rovf bit cnrgpt.clear rovf bit = 1 no dn = 0 and muc = 0 note rovf = 1? read cnrgpt register no yes clear dn bit cnmctrlm.clear dn bit = 1 read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers rhpm = 1? end yes no yes read of normal data read of illegal data note check the muc and dn bits using one read access. chapter 15 can controller 746 user?s manual u17830ee1v0um00 figure 15-50. reception via software polling start no cints1 = 1? yes clear cints1 bit cnints.clear cints1 bit = 1 clear rovf bit cnrgpt.clear rovf bit = 1 no dn = 0 and muc = 0 note rovf = 1? read cnrgpt register yes no clear dn bit cnmctrlm.clear dn bit = 1 read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers rhpm = 1? end yes no yes read of normal data read of illegal data note check the muc and dn bits using one read access. chapter 15 can controller 747 user?s manual u17830ee1v0um00 figure 15-51. setting can sleep mode/stop mode start (when psmode[1:0] = 00b) psmode0 = 1? set psmode0 bit cnctrl.set_psmode1 = 1 cnctrl.clear_psmode1 = 0 can sleep mode can sleep mode end ye s no set psmode1 bit cnctrl.set_psmode1 = 1 cnctrl.clear_psmode1 = 0 psmode1 = 1? can stop mode can stop mode request can sleep mode again? ye s no ye s no access to registers other than the cnctrl and cngmctrl registers init mode? ye s no clear cints5 bit cnints .clear_cints5 = 1 clear cints5 bit cnints .clear_cints5 = 1 clear opmode set cnctrl register (set opmode) caution to abort transmission before making a request for the can sleep mode, perform processing according to figures 15-46 and 15-47. chapter 15 can controller 748 user?s manual u17830ee1v0um00 figure 15-52. clear can sleep/stop mode start can sleep mode end clear psmode1 bit. set psmode1 bit = 0 clear psmode1 bit = 1 can stop mode clear psmode0 bit. set psmode0 bit = 0 clear psmode0 bit = 1 releasing can sleep mode by user releasing can sleep mode by can bus active bus activity = 0 psmode0 = 0 cints5 = 1 clear cints5 bit. clear cints5 bit = 1 chapter 15 can controller 749 user?s manual u17830ee1v0um00 figure 15-53. bus-off recovery start access to register other than cnctrl and cngmctrl registers set cnctrl register (clear opmode) no boff = 1? yes clear all trq bits no forced recovery from bus off? end set ccerc bit cnctrl.set_ccerc bit = 1 set cnctrl register (set opmode) wait for recorvery from bus off yes set cnctrl register (set opmode) chapter 15 can controller 750 user?s manual u17830ee1v0um00 figure 15-54. normal shutdown process start gom = 0? clear gom bit. set gom bit = 0 clear gom bit = 1 end yes no iinit mode shutdown successful gom = 0, efsd = 0 chapter 15 can controller 751 user?s manual u17830ee1v0um00 figure 15-55. forced shutdown process start gom = 0? clear gom bit. set gom bit = 0 clear gom bit = 1 end yes no shutdown successful gom = 0, efsd = 0 set efsd bit. set efsd bit = 1 must be a continuous write. caution do not read- or write- access any registers by software be tween setting th e efsd bit and clearing the gom bit. remark opmode: normal operation mode, normal operati on mode with abt, receive-only mode, single- shot mode, self-test mode chapter 15 can controller 752 user?s manual u17830ee1v0um00 figure 15-56. error handling start clear cints2 bit. clear cints2 bit = 1 cints2 = 1? cints3 = 1? end yes check can protocol error state. (read cnlec register) no yes no error interrupt check can module state. (read cninfo register) clear cints3 bit. clear cints3 bit = 1 cints4 = 1? clear cints4 bit. clear cints4 bit = 1 no yes chapter 15 can controller 753 user?s manual u17830ee1v0um00 figure 15-57. setting cpu standby (from can sleep mode) start psmode0 = 1? psmode = 01b? end ye s set cpu standby mode no ye s no can sleep mode enable interrupts set psmode0 bit cnctrl.set_psmode0 = 1 cnctrl.clear_psmode0 = 0 disable interrupts start psmode0 bit = 1? psmode[1:0] bits = 01b? end ye s set cpu standby mode. no ye s no can sleep mode can sleep mode enable interrupts. set psmode0 bit. cnctrl.set_psmode0 = 1 cnctrl.clear_psmode0 = 0 disable interrupts. caution check the can sleep mode or not, before cp u is set to standby mode. otherwise, until cpu is set to standby mode, can sleep m ode may be released by wake-up. chapter 15 can controller 754 user?s manual u17830ee1v0um00 figure 15-58. setting cpu st andby (from can stop mode) start end set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 psmode0 bit = 1? psmode[1:0] = 11? yes no psmode1 bit = 1? no yes can stop mode yes no set psmode1 bit. set psmode1 bit = 1 clear psmode1 bit = 0 clear cints5 bit. clear cints5 bit = 1 note set cpu standby mode. can sleep mode note during wakeup interrupts caution the can stop mode can only be released by writing 01 to th e cnctrl.psmode1 and cnctrl.psmode0 bits. h cannot be released by changing the can bus. user?s manual u17830ee1v0um00 755 chapter 16 dma function (dma controller) the v850es/fg2 and v850es/fj2 include a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the v850es/fe2 and v850es/ff2 do not include a direct memory access (dma) controller. the dmac controls data transfer between memory and i/o, between memo ries, or between i/os based on dma requests issued by the on-chip peripheral i/o (serial in terface, timer/counter, and a/d converter), interrupts from external input pins, or software triggers (memory refers to internal ram or external memory). 16.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (seria l interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer targets ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o ? internal ram ? external memory ? external memory ? peripheral i/o ? external memory ? external memory chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 756 16.2 configuration figure 16-1. block diagram of dma controller cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/sj2 bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) remark n = 0 to 3 chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 757 16.3 registers (1) dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresse s (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer source set the address (a25 to a16) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa25 to sa16 set the address (a15 to a0) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa15 to sa0 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah, dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h dsanl (n = 0 to 3) sa15 sa14 sa13 sa12 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa7 sa8 sa9 sa10 sa11 dsanh (n = 0 to 3) ir 000 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa23 sa24 sa25 0 0 cautions 1. be sure to clear bits 14 to 10 of the dsanh register to 0. 2. set the dsanh and dsanl re gisters at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the dsan register is read, two 16-bit re gisters, dsanh and dsanl, are read. if reading and updating conflict, the value being updated may be read (see 16.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 758 (2) dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma destination addre ss (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer destination set an address (a25 to a16) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da25 to da16 set an address (a15 to a0) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da15 to da0 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh, dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch ddanl (n = 0 to 3) da15 da14 da13 da12 da6 da5 da4 da3 da2 da1 da0 da7 da8 da9 da10 da11 ddanh (n = 0 to 3) ir 000 da22 da21 da20 da19 da18 da17 da16 da23 da24 da25 0 0 cautions 1. be sure to clear bits 14 to 10 of the ddanh register to 0. 2. set the ddanh and ddanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a value being updated may be read (see 16.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 759 (3) dma byte count registers 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer c ount for dma channel n (n = 0 to 3). these registers hold the remaining tr ansfer count during dma transfer. these registers are decremented by 1 per one transfer regardless of the trans fer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. these registers can be read or written in 16-bit units. byte transfer count 1 or remaining byte transfer count byte transfer count 2 or remaining byte transfer count : byte transfer count 65,536 (2 16 ) or remaining byte transfer count bc15 to bc0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h dbcn (n = 0 to 3) 15 bc15 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 the number of transfer data set first is held when dma transfer is complete. cautions 1. set the dbcn register at the follow ing timing when dma transf er is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 760 (4) dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers can be read or written in 16-bit units. reset sets these registers to 0000h. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the transfer source address increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 cautions 1. be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to 0. 2. set the dadcn register at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. the ds0 bit specifies the size of the transfer data, and does not control bus sizing. if 8-bit data (ds0 bit = 0) is set, therefore, the lower data bus is not always used. 4. if the transfer data size is set to 16 bits (ds0 bit = 1), transfer cannot be started from an odd address. transfer is always started from an address with the first bit of the lower address aligned to 0. 5. if dma transfer is executed on an on-chip peripheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as the re gister size. for example, to execute dma transfer on an 8-bit register , be sure to specify 8-bit transfer. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 761 (5) dma channel control registers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers t hat control the dma transfer operating mode for dma channel n. these registers can be read or written in 8-bit or 1-bit units. (however, bit 7 is read-only and bits 1 and 2 are write-only. if bit 1 or 2 is read, the read value is always 0.) reset sets these registers to 00h. dchcn (n = 0 to 3) dma transfer had not completed. dma transfer had completed. it is set to 1 on the last dma transfer completed and cleared to 0 when it is read. tcn 0 1 status flag indicates whether dma transfer through dma channel n has completed or not dma transfer disabled dma transfer enabled dma transfer is enabled when the enn bit is set to 1. when dma transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. to abort dma transfer, clear the enn bit to 0 by software. to resume, set the enn bit to 1 again. when aborting or resuming dma transfer, however, be sure to observe the procedure described in 16.11 cautions. enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn 0 1 2 3 4 5 6 7 set the init bit to 1 when the enn bit = 0. initn if the initn bit is set to 1 with dma transfer disabled (enn bit = 0), the dma transfer status can be initialized. when re-setting the dma transfer status (re-setting the ddanh, ddanl, dsanh, dsanl, dbcn, and dadcn registers) before dma transfer is completed (before the tcn bit is set to 1), be sure to initialize the dma channel. when initializing the dma controller, however, be sure to observe the procedure described in 16.11 cautions. notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. be sure to clear bits 6 to 3 of the dchcn register to 0. 2. before generating a dma transfer request by software, make sure that the tcn bit is set to 1 and then clear the tcn bit to 0. 3. if the init bit setting and the dma transfer of another cha nnel conflict, initialization may not perform. 4. when dma transfer is completed (when a terminal count is generated), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn regist er is read while its bits are being updated, a value indicating ?transfer not co mpleted and transfer is disabled? (tcn bit chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 762 = 0 and enn bit = 0) may be read. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 763 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that control the dma transfer start trigger via interrupt request signals from on-chip peripheral i/o. the interrupt request signals set by these re gisters serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, dfn bit can be read or written in 1-bit units. reset sets these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 dma transfer request flag after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note the dfn bit is a write-only bit. write 0 to this bi t to clear a dma transfer request if an interrupt that is specified as the cause of starting dma trans fer occurs while dma transfer is disabled. cautions 1. set the ifcn5 to if cn0 bits at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. an interrupt request that is generated in the standby mode (idel1, idle2, stop, or sub- idle mode) does not start the dma transfer cycle (nor is the dfn bit set to 1). 3. if a dma start factor is selected by the ifcn 5 to ifcn0 bits, the dfn bi t is set to 1 when an interrupt occurs from the selected on-chip pe ripheral i/o, regardless of whether the dma transfer is enabled or disable d. if dma is enabled in this status, dma transfer is immediately started. 4. the number of supported dma start factors differs depending on the product as shown in table 16-1. for details of the ifcn5 to if cn0 bits, see table 16-2 dma start factors. table 16-1. number of dma start factors in each product part number number of dma start factors range of ifcn5 to ifcn0 note pd70f3237 59 000000b to 111011b (intlvi to intcb2t) pd70f3238 63 000000b to 111111b (intlvi to intc3trx) pd70f3239 63 000000b to 111111b (intlvi to intc3trx) note setting a value other than the value shown in the range of ifcn5 to ifcn0 is prohibited. chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 764 table 16-2. dma start factors (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intlvi 0 0 0 0 1 0 intp0 0 0 0 0 1 1 intp1 0 0 0 1 0 0 intp2 0 0 0 1 0 1 intp3 0 0 0 1 1 0 intp4 0 0 0 1 1 1 intp5 0 0 1 0 0 0 intp6 0 0 1 0 0 1 intp7 0 0 1 0 1 0 inttq0ov 0 0 1 0 1 1 inttq0cc0 0 0 1 1 0 0 inttq0cc1 0 0 1 1 0 1 inttq0cc2 0 0 1 1 1 0 inttq0cc3 0 0 1 1 1 1 inttp0ov 0 1 0 0 0 0 inttp0cc0 0 1 0 0 0 1 inttp0cc1 0 1 0 0 1 0 inttp1ov 0 1 0 0 1 1 inttp1cc0 0 1 0 1 0 0 inttp1cc1 0 1 0 1 0 1 inttp2ov 0 1 0 1 1 0 inttp2cc0 0 1 0 1 1 1 inttp2cc1 0 1 1 0 0 0 inttp3ov 0 1 1 0 0 1 inttp3cc0 0 1 1 0 1 0 inttp3cc1 0 1 1 0 1 1 inttm0eq0 0 1 1 1 0 0 intcb0r 0 1 1 1 0 1 intcb0t 0 1 1 1 1 0 intcb1r 0 1 1 1 1 1 intcb1t 1 0 0 0 0 0 intua0r 1 0 0 0 0 1 intua0t 1 0 0 0 1 0 intua1r 1 0 0 0 1 1 intua1t 1 0 0 1 0 0 intad 1 0 0 1 0 1 intc0err 1 0 0 1 1 0 intc0wup 1 0 0 1 1 1 intc0rec remark n = 0 to 3 chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 765 table 16-2. dma start factors (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 1 0 0 0 intc0trx 1 0 1 0 0 1 intkr 1 0 1 0 1 0 inttq1ov 1 0 1 0 1 1 inttq1cc0 1 0 1 1 0 0 inttq1cc1 1 0 1 1 0 1 inttq1cc2 1 0 1 1 1 0 inttq1cc3 1 0 1 1 1 1 intua2r 1 1 0 0 0 0 intua2t 1 1 0 0 0 1 intc1err 1 0 0 1 0 intc1ewup 1 1 0 0 1 1 intc1rec 1 1 0 1 0 0 intc1trx 1 1 0 1 0 1 inttq2ov 1 1 0 1 1 0 inttq2cc0 1 1 0 1 1 1 inttq2cc1 1 1 1 0 0 0 inttq2cc2 1 1 1 0 0 1 inttq2cc3 1 1 1 0 1 0 intcb2r 1 1 1 0 1 1 intcb2t 1 1 1 1 0 0 intc2rec note 1 1 1 1 0 1 intc2trx note 1 1 1 1 1 0 intc3rec note 1 1 1 1 1 1 intc3trx note note pd70f3238 and pd70f3239 only remark n = 0 to 3 chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 766 16.4 dma bus states 16.4.1 types of bus states the dmac bus states consis t of the following 10 states. (1) ti state the ti state is an idle state, duri ng which no access request is issued. the dma request signals are sampled at the rising edge of the clkout signal. (2) t0 state dma transfer ready state (state in which a dma transfe r request has been issued and the bus mastership is acquired for the first dma transfer). (3) t1r state the bus enters the t1r state at the beginning of a read operation in two-cycle transfer. address driving starts. after entering the t1r state, the bus ent ers the t2r state. (4) t1ri state the t1ri state is a state in whic h the bus waits for the acknowledge signal corresponding to an external memory read request. after entering the last t1ri state, t he bus invariably enters the t2r state. (5) t2r state the t2r state corresponds to the last state of a read operation in two-cycl e transfer, or to a wait state. in the last t2r state, read data is sa mpled. after entering the last t2r st ate, the bus enters the t1w state or t2ri state. (6) t2ri state state in which the bus is ready for dma transfer to on-chip peripheral i/o or internal ram (state in which the bus mastership is acquired for dma transfer to on-chip peripheral i/o or internal ram). after entering the last t2ri state, t he bus invariably enters the t1w state. (7) t1w state the bus enters the t1w state at the beginning of a write oper ation in two-cycle transfer. address driving starts. after entering the t1w state, the bus ent ers the t2w state. (8) t1wi state state in which the bus waits for the acknowledge signal corresponding to an external memory write request. after entering the last t1wi state, t he bus invariably enters the t2w state. (9) t2w state the t2w state corresponds to the last state of a write operation in two-cy cle transfer, or to a wait state. in the last t2w state, the writ e strobe signal is made inactive. (10) te state the te state corresponds to dma transfer completion. the dmac generates the internal dma transfer completion signal and various internal signals are initialized. after entering the te state, the bus invariably enters the ti state. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 767 16.4.2 dmac bus cycle state transition each time the processing for a dma transfer is completed, the bus mastership is released. figure 16-2. dmac bus cycle state transition ti t0 t1r t1ri t2r t1w t2w te ti t2ri t1wi chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 768 16.5 transfer targets table 16-3 shows the relationship between the transfer targets ( : transfer enabled, : transfer disabled). table 16-3. relationship between transfer targets transfer destination internal rom on-chip peripheral i/o internal ram external memory on-chip peripheral i/o internal ram external memory source internal rom caution the operation is not guaranteed for combinat ions of transfer destination and source marked with ? ? in table 16-3. 16.6 transfer modes single transfer is supported as the transfer mode. in single transfer mode, the bus is released at each byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer r equest is issued, the higher priority dma request always takes precedence. if a new transfer request of the same channel and a transfer request of another channel with a lower priority are generated in a transfer cycle, dma transfer of the channel with t he lower priority is executed after the bus is released to the cpu (the new transfer request of the same channel is ignored in the transfer cycle). chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 769 16.7 transfer types as a transfer type, the 2-cycle transfer is supported. in two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. in the read cycle, the transfer source address is output and reading is performed from the source to the dmac. in the write cycle, the transfer destination addr ess is output and writing is performed from the dmac to the destination. an idle cycle of one clock is always inserted between a read cycle and a write cycle. if the data bus width differs between the transfer source and destination for dma transfe r of two cycles, the operation is performed as follows. <16-bit data transfer> <1> transfer from 32-bit bus 16-bit bus a read cycle (the higher 16 bits are in a high-impedan ce state) is generated, followed by generation of a write cycle (16 bits). <2> transfer from 16-/32-bit bus to 8-bit bus a 16-bit read cycle is generated once, and t hen an 8-bit write cycle is generated twice. <3> transfer from 8-bit bus to 16-/32-bit bus an 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> transfer between 16-bit bus and 32-bit bus a 16-bit read cycle is generated once, and t hen a 16-bit write cycle is generated once. for dma transfer executed to an on-chip peripheral i/o register (tr ansfer source/destination), be sure to specify the same transfer size as the register size. for example, for dma transfer to an 8-bit register, be sure to specify byte (8- bit) transfer. remark the bus width of each transfer target (tr ansfer source/destination) is as follows. ? on-chip peripheral i/o: 16-bit bus width ? internal ram: 32-bit bus width ? external memory: 8-bit or 16-bit bus width chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 770 16.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 the priorities are checked for every transfer cycle. 16.9 time related to dma transfer the time required responding to a dma request, and the mi nimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) dma cycle minimum number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory. internal ram access 2 clocks note 3 <2> memory access peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 0 to 7). 3. two clocks are required for a dma cycle. 4. more wait cycles are necessary for accessing a specific peripheral i/o register (for details, see 3.4.10 (2) ). chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 771 16.10 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request by software if the stgn bit is set to 1 while the dchcn.tcn bit = 1 and enn bit = 1 (dma transfer enabled), dma transfer is started. to request the next dma transfer cycle immediately after that, confirm, by using th e dbcn register, that the preceding dma transfer cycle has been completed, and set the stgn bit to 1 again (n = 0 to 3). tcn bit = 0, enn bit = 1 stgn bit = 1 ? starts the first dma transfer. confirm that the contents of the dbcn register have been updated. stgn bit = 1 ? starts the second dma transfer. : generation of terminal count ? enn bit = 0, tc n bit = 1, and intdman signal is generated. (2) request by on-chip peripheral i/o if an interrupt request is generated from the on-chip peripheral i/o set by the dtfrn register when the dchcn.tcn bit = 0 and enn bit = 1 (dma transf er enabled), dma transfer is started. cautions 1. two start factors (software trigger a nd hardware trigger) cannot be used for one dma channel. if two start factors are simultane ously generated for one dma channel, only one of them is valid. the start factor that is valid cannot be identified. 2. a new transfer request that is generate d after the preceding dma transfer request was generated or in the preceding dma tran sfer cycle is ignored (cleared). 3. the transfer request interval of the sam e dma channel varies depending on the setting of bus wait in the dma transfer cycle, the start status of the other channels, or the external bus hold request. in particular, as described in caution 2, a new transfer request that is generated for the same channel before the dma transfer cycle or during the dma transfer cycle is ignored. therefore, the transfer re quest intervals for the same dma channel must be sufficiently separated by th e system. when the software tr igger is used, completion of the dma transfer cycle that was generated before can be checked by updating the dbcn register. chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 772 16.11 dma abort factors dma transfer is aborted if a bus hold occurs. the same applies if transfer is ex ecuted between the intern al memory/on-chip peripheral i/o and internal memory/on-chip peripheral i/o. when the bus hold is cleared, dma transfer is resumed. 16.12 end of dma transfer when dma transfer has been completed the number of ti mes set to the dbcn register and when the dchcn.enn bit is cleared to 0 and tcn bit is set to 1, a dma transfer end interrupt request signal (intdman) is generated for the interrupt controller (intc) (n = 0 to 3). the v850es/fg2 and v850es/fj2 do not output a terminal c ount signal to an external device. therefore, confirm completion of dma transfer by using the dma transfer end interrupt or polling the tcn bit. 16.13 operation timing figures 16-3 to 16-6 show dma operation timing. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 773 figure 16-3. priority of dma (1) preparation for transfer read write idle end processing dma2 processing cpu processing dma1 processing cpu processing cpu processing dma0 processing dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit preparation for transfer read write idle end processing preparation for transfer read remarks 1. transfer in the order of dma0 dma1 dma2 2. in the case of transfer between external memory spaces (multiplexed bus, no wait) chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 774 figure 16-4. priority of dma (2) preparation for transfer read write idle dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing read write idle end processing read preparation for transfer preparation for transfer end processing remarks 1. transfer in the order of dma0 dma1 dma0 (dma2 is held pending.) 2. in the case of transfer between external memory spaces (multiplexed bus, no wait) chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 775 figure 16-5. period in which dma transfer request is ignored (1) preparation for transfer read cycle write cycle idle end processing dma transfer mode of processing dfn bit system clock transfer request generated after this can be acknowledged dma0 processing cpu processing cpu processing note 2 note 2 dman transfer request note 1 note 2 notes 1. interrupt from on-chip peripheral i/o , or software trigger (stgn bit) 2. new dma request of the same channel is ignor ed between when the first request is generated and the end processing is complete. remark in the case of transfer between external memory spaces (multiplexed bus, no wait) chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 776 figure 16-6. period in which dma transfer request is ignored (2) preparation for transfer read write idle <1> <2> <3> <4> cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit preparation for transfer read write idle preparation for transfer read end processing end processing <1> dma0 transfer request <2> new dma0 transfer request is generated during dma0 transfer. a dma transfer request of the same channel is ignored during dma transfer. <3> requests for dma0 and dma1 are generated at the same time. dma0 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma1 request is acknowledged. <4> requests for dma0, dma1, and dma2 are generated at the same time. dma1 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma0 request is acknowledged according to priority. dma2 request is held pending (transfer of dma2 occurs next). chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 777 16.14 cautions (1) caution for vswc register when using the dmac, be sure to set an appropriate val ue, in accordance with the operating frequency, to the vswc register. when the default value (77h) of the vsw c register is used, or if an inappr opriate value is set to the vswc register, the operation is not correctly performed (for deta ils of the vswc register, see 3.4.10 (1) (a) system wait control register (vswc) ). (2) caution for dma transfer executed on internal ram when executing the following instructions located in th e internal ram, do not ex ecute a dma transfer that transfers data to/from the internal ram (transfer source/destination), because the cpu may not operate correctly afterward. ? bit manipulation instruction located in internal ram (set1, clr1, or not1) ? data access instruction to misaligned address located in internal ram conversely, when executing a dma transfer to tran sfer data to/from the in ternal ram (transfer source/destination), do not execut e the above two instructions. (3) caution for reading dchcn .tcn bit (n = 0 to 3) the tcn bit is cleared to 0 when it is read, but it is not automat ically cleared even if it is read at a specific timing. to accurately clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bit = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt servicing routine execute reading the tcn bit three times. chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 778 (4) dma transfer initialization pro cedure (setting dchcn.initn bit to 1) even if the initn bit is set to 1 when the channel exec uting dma transfer is to be initialized, the channel may not be initialized. to accurately initialize the c hannel, execute either of the following two procedures. (a) temporarily stop transfer of all dma channels initialize the channel executing dma transfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when st ep <5> is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit of dm a channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit of the dma channels used (including the channel to be forcibly terminated) to 0. to clear the enn bit of the last dma channel, execute th e clear instruction twice. if the target of dma transfer (transfer source/destination) is the inte rnal ram, execute the instruction three times. example: execute instructions in t he following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal ram). ? clear dchc0.e00 bit to 0. ? clear dchc1.e11 bit to 0. ? clear dchc2.e22 bit to 0. ? clear dchc2.e22 bit to 0 again. <4> set the initn bit of the channel to be forcibly terminated to 1. <5> read the tcn bit of each channel not to be forcib ly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). caution be sure to execute step <5> above to pr event illegal setting of the enn bit of the channels whose dma transfer has been normall y completed between <2> and <3>. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 779 (b) repeatedly execute setting initn bit until transfer is forcibly terminated correctly <1> suppress a request from the dma request source of the channel to be forcibly terminated (stop operation of the on-ch ip peripheral i/o). <2> check that the dma transfer request of the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer reques t is held pending, wait until execution of the pending request is completed. <3> when it has been confirmed that t he dma request of the channel to be fo rcibly terminated is not held pending, clear the enn bit to 0. <4> again, clear the enn bit of the channel to be forcibly terminated. if the target of transfer for the channel to be forc ibly terminated (transfer source/destination) is the internal ram, execute th is operation once more. <5> copy the initial number of trans fers of the channel to be forcibly terminated to a general-purpose register. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn regist er of the channel to be forcibly terminated, and compare it with the value copied in <5>. if the two values do not match, repeat operations <6> and <7>. remarks 1. when the value of the dbcn regist er is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. if not, the remaining number of transfers is read. 2. note that method (b) may take a long time if the application frequently uses dma transfer for a channel other than the dma channel to be forcibly terminated. (5) procedure of temporarily stoppi ng dma transfer (clearing enn bit) stop and resume the dma transfer under ex ecution using the following procedure. <1> suppress a transfer request from the dma request s ource (stop the operation of the on-chip peripheral i/o). <2> check the dma transfer request is not held pending , by using the dfn bit (check if the dfn bit = 0). if a request is pending, wait until execution of the pending dma transfer request is completed. <3> if it has been confirmed that no dma transfer requ est is held pending, clear the enn bit to 0 (this operation stops dma transfer). <4> set the enn bit to 1 to resume dma transfer. <5> resume the operation of the dma request source that has been stopped (start the operation of the on- chip peripheral i/o). (6) memory boundary the operation is not guaranteed if th e address of the transfer source or destination exceeds the area of the dma target (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (7) transferring misaligned data dma transfer of misaligned data with a 16-bit bus width is not supported. if an odd address is specified as the trans fer source or destination, the leas t significant bit of the address is forcibly assumed to be 0. chapter 20 dma function (dma controller) user?s manual u17830ee1v0um00 780 (8) bus arbitration for cpu because the dma controller has a higher priority bus ma stership than the cpu, a cpu access that takes place during dma transfer is held pending unt il the dma transfer cycle is complete d and the bus is released to the cpu. however, the cpu can access the external memory, on- chip peripheral i/o, and inte rnal ram to/from which dma transfer is not being executed. ? the cpu can access the internal ram when dma trans fer is being executed between the external memory and on-chip peripheral i/o. ? the cpu can access the internal ram and on-chip peripheral i/o wh en dma transfer is being executed between the external memory and external memory. (9) registers/bits that must not be rewritten during dma operation set the following registers at the following ti ming when a dma operation is not under execution. [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [timing of setting] ? period from after reset to start of the first dma transfer ? time after channel initializ ation to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer (10) be sure to set the foll owing register bits to 0. ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register (11) dma start factor do not start two or more dma channels with the same st art factor. if two or more channels are started with the same factor, a dma channel with a lower priority may be acknowledged earlier than a dma channel with a higher priority. chapter 16 dma function (dma controller) user?s manual u17830ee1v0um00 781 (12) read values of dsan and ddan registers values in the middle of updating may be read from t he dsan and ddan registers during dma transfer (n = 0 to 3). for example, if the dsanh regist er and then the dsanl register ar e read when the dma transfer source address (dsan register) is 0000ffffh and the count direction is incremental (dadcn.sad1 and dadcn.sad0 bits = 00), the value of the dsan regist er differs as follows, depending on whether dma transfer is executed immediately after the dsanh register is read. (a) if dma transfer does not occu r while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> read value of dsanl register: dsanl = ffffh (b) if dma transfer occurs while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan = 00100000h <4> read value of dsanl register: dsanl = 0000h (13) dma trigger change when the interrupt request signal selection in the dtfr register is changed and t he original interrupt request selection is also the selection for another dma chann el, there is the possibilit y that a dma transfer will inadvertently occur. when the setting of dtfrn register is changed, please make sure to follow the procedure shown below: (a). in the case that the desired setting of th e ifc is not set to a different dma channel <1> dma operation of target channel, which is re-written, should be stopped (dchcn.enn=0) <2> change the setting of dtfrn register (by 8 bit operation) <3> confirm dtfrn.dfn=0 (the oper ation of the interrupt generat ion factor should be stopped previously) <4> dma operation can be enabled (dchcn.enn=1) (b). in the case that the desired setting of the ifc (dman) is set to another dma channel (dmam) <1> dma operation of target channel, (dman) whic h is re-written, should be stopped (dchcn.enn=0). <2> dma operation of the channel, which has the sa me value for the ifcm5-0bits, should be stopped (dchcm.emm=0). <3> change the setting of dtfrn register (by 8 bit operation) <4> confirm dtfrn.dfn=0 and dtfrm. dfm=0 (the operation of the interr upt generation factor should be stopped previously) <5> dma operation can be enabled (dchcn.enn=1 and dchcm.enn=1) user?s manual u17830ee1v0um00 782 chapter 17 interrupt/exception processing function remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. the v850es/fx2 is provided with a dedicated interru pt controller (intc) for interrupt servicing. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/fx2 can process interrupt request signals from the on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). the number of supported maskable interrupt sources diffe rs depending on the product, as shown in table 17-1. table 17-1. number of maskable interrupt sources part number number of maskable interrupt sources maskable interrupts note v850es/fe2 v850es/ff2 43 intlvi to intwt v850es/fg2 61 intlvi to intma3 pd70f3237 72 intlvi to intcb2t v850es/fj2 pd70f3238, 70f3239 82 intlvi to intc3trx note refer to table 17-2 for the maskable interrupts. caution the explanations in this chapter use th e maximum of 82 maskable interrupt sources. 17.1 features interrupts non-maskable interrupts: 2 sources maskable interrupts: external: 15, internal: 67 sources (number of sources varies depending on the product.) 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for eac h maskable interrupt request noise elimination, edge detection, and valid edge s pecification for external interrupt request signals exceptions software exceptions: 32 sources exception trap: 2 sources (illegal opcode exception, debug trap) the interrupt/exception sources are listed in table 17-2. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 783 table 17-2. interrupt source list (1/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset interrupt ? reset reset pin input reset input by internal source reset 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt2 wdt2 overflow wdt2 0020h 00000020h nextpc note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/ dbtrap instruction ? 0060h 00000060h nextpc ? 0 intlvi low voltage detection poclvi 0080h 00000080h nextpc lviic 1 intp0 external interrupt pin input edge detection (intp0) pin 0090h 00000090h nextpc pic0 2 intp1 external interrupt pin input edge detection (intp1) pin 00a0h 000000a0h nextpc pic1 3 intp2 external interrupt pin input edge detection (intp2) pin 00b0h 000000b0h nextpc pic2 4 intp3 external interrupt pin input edge detection (intp3) pin 00c0h 000000c0h nextpc pic3 5 intp4 external interrupt pin input edge detection (intp4) pin 00d0h 000000d0h nextpc pic4 6 intp5 external interrupt pin input edge detection (intp5) pin 00e0h 000000e0h nextpc pic5 7 intp6 external interrupt pin input edge detection (intp6) pin 00f0h 000000f0h nextpc pic6 8 intp7 external interrupt pin input edge detection (intp7) pin 0100h 00000100h nextpc pic7 9 inttq0ov tmq0 overflow tmq0 0110h 00000110h nextpc tq0ovic 10 inttq0cc0 tmq0 capture 0/compare 0 match tmq0 0120h 00000120h nextpc tq0ccic0 11 inttq0cc1 tmq0 capture 1/compare 1 match tmq0 0130h 00000130h nextpc tq0ccic1 12 inttq0cc2 tmq0 capture 2/compare 2 match tmq0 0140h 00000140h nextpc tq0ccic2 13 inttq0cc3 tmq0 capture 3/compare 3 match tmq0 0150h 00000150h nextpc tq0ccic3 14 inttp0ov tmp0 overflow tmp0 0160h 00000160h nextpc tp0ovic 15 inttp0cc0 tmp0 capture 0/compare 0 match tmp0 0170h 00000170h nextpc tp0ccic0 16 inttp0cc1 tmp0 capture 1/compare 1 match tmp0 0180h 00000180h nextpc tp0ccic1 17 inttp1ov tmp1 overflow tmp1 0190h 00000190h nextpc tp1ovic 18 inttp1cc0 tmp1 capture 0/compare 0 match tmp1 01a0h 000001ah nextpc tp1ccic0 19 inttp1cc1 tmp1 capture 1/compare 1 match tmp1 01b0h 000001b0h nextpc tp1ccic1 20 inttp2ov tmp2 overflow tmp2 01c0h 000001c0h nextpc tp2ovic maskable interrupt 21 inttp2cc0 tmp2 capture 0/compare 0 match tmp2 01d0h 000001d0h nextpc tp2ccic0 notes 1. for the restoring in the case of intwdt 2, see "17.2.3 (2) from intwdt2 signal". 2. n = 0h to fh chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 784 table 17-2. interrupt source list (2/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 22 inttp2cc1 tmp2 capture 1/compare 1 match tmp2 01e0h 000001e0h nextpc tp2ccic1 23 inttp3ov tmp3 overflow tmp3 01f0h 000001f0h nextpc tp3ovic 24 inttp3cc0 tmp3 capture 0/compare 0 match tmp3 0200h 00000200h nextpc tp3ccic0 25 inttp3cc1 tmp3 capture 1/compare 1 match tmp3 0210h 00000210h nextpc tp3ccic1 26 inttm0eq0 tmm0 compare match tmm0 0220h 00000220h nextpc tm0eqic0 27 intcb0r csib0 reception completion csib0/iic1 0230h 00000230h nextpc cb0ric 28 intcb0t csib0 consecutive transmission write enable csib0 0240h 00000240h nextpc cb0tic 29 intcb1r csib1 reception completi on csib1 0250h 00000250h nextpc cb1ric 30 intcb1t csib1 consecutive transmission write enable csib1 0260h 00000260h nextpc cb1tic 31 intua0r uarta0 reception completion uarta0/ csib4 0270h 00000280h nextpc ua0ric 32 intua0t uarta0 transmission enable uarta0/ csib4 0280h 00000280h nextpc ua0tic 33 intua1r uarta1 reception completion/uarta1 reception error uarta1/ iic2 0290h 00000290h nextpc ua1ric 34 intua1t uarta1 transmission enable uarta1 02a0h 000002a0h nextpc ua1tic 35 intad a/d conversion completi on a/d 02bh 000002b0h nextpc adic 36 intc0err afcan0 error afcan0 02c0h 000002c0h nextpc c0erric 37 intc0wup afcan0 wakeup afca n0 02d0h 000002d0h nextpc c0wupic 38 intc0rec afcan0 reception completion afcan0 02e0h 000002e0h nextpc c0recic 39 intc0trx afcan0 transmission completion afcan0 02f0h 000002f0h nextpc c0trxic 40 intkr key return interrupt r equest kr 0300h 00000300h nextpc kric 41 intwti watch timer interval wt 0310h 00000310h nextpc wtiic 42 intwt watch timer reference ti me wt 0320h 00000320h nextpc wtic 43 intp8 external interrupt pin input edge detection (intp8) pin 0330h 00000330h nextpc pic8 44 intp9 external interrupt pin input edge detection (intp9) pin 0340h 00000340h nextpc pic9 45 intp10 external interrupt pin input edge detection (intp10) pin 0350h 00000350h nextpc pic10 46 inttq1ov tmq1 overflow tm q1 0360h 00000360h nextpc tq1ovic 47 inttq1cc0 tmq1 capture 0/compare 0 match tmq1 0370h 00000370h nextpc tq1ccic0 48 inttq1cc1 tmq1 capture 1/compare 1 match tmq1 0380h 00000380h nextpc tq1ccic1 49 inttq1cc2 tmq1 capture 2/compare 2 match tmq1 0390h 00000390h nextpc tq1ccic2 maskable interrupt 50 inttq1cc3 tmq1 capture 3/compare 3 match tmq1 03a0h 000003a0h nextpc tq1ccic3 chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 785 table 17-2. interrupt source list (3/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 51 intua2r uarta2 reception completion/error uarta2 03b0h 000003b0h nextpc ua2ric 52 intua2t uarta2 transmission enable ua rta2 03c0h 000003c0h nextpc ua2tic 53 intc1err afcan1 error afcan1 03d0h 000003d0h nextpc c1erric 54 intc1wup afcan1 wakeup afcan1 03e0h 000003e0h nextpc c1wupic 55 intc1rec afcan1 recept ion completion afcan1 03f0h 000003f0h nextpc c1recic 56 intc1trx afcan1 transmission completion afcan1 0400h 00000400h nextpc c1trxic 57 intdma0 dma0 transfer end dma 0410h 00000410h nextpc dmaic0 58 intdma1 dma1 transfer end dma 0420h 00000420h nextpc dmaic1 59 intdma2 dma2 transfer end dma 0430h 00000430h nextpc dmaic2 60 intdma3 dma3 transfer end dma 0440h 00000440h nextpc dmaic3 61 intp11 external interrupt pin input edge detection (intp11) pin 0450h 00000450h nextpc pic11 62 intp12 external interrupt pin input edge detection (intp12) pin 0460h 00000460h nextpc pic12 63 intp13 external interrupt pin input edge detection (intp13) pin 0470h 00000470h nextpc pic13 64 intp14 external interrupt pin input edge detection (intp14) pin 0480h 00000480h nextpc pic14 65 inttq2ov tmq2 overflow tm q2 0490h 00000490h nextpc tq2ovic 66 inttq2cc0 tmq2 capture 0/compare 0 match tmq2 04a0h 000004a0h nextpc tq2ccic0 67 inttq2cc1 tmq2 capture 1/compare 1 match tmq2 04b0h 000004b0h nextpc tq2ccic1 68 inttq2cc2 tmq2 capture 2/compare 2 match tmq2 04c0h 000004c0h nextpc tq2ccic2 69 inttq2cc3 tmq2 capture 3/compare 3 match tmq2 04d0h 000004d0h nextpc tq2ccic3 70 intcb2r csib2 reception completion/error csib2 04e0h 000004e0h nextpc cb2ric 71 intcb2t csib2 continuous transmission write enable csib2 04f0h 000004f0h nextpc cb2tic 72 intua3r uarta3 reception completion/error uarta3 0500h 00000500h nextpc ua3ric 73 intua3t uarta3 transmission enable uarta3 0510h 00000510h nextpc ua3tic 74 intc2err afcan2 error afcan2 0520h 00000520h nextpc c2erric 75 intc2wup afcan2 wakeup afca n2 0530h 00000530h nextpc c2wupic 76 intc2rec afcan2 reception comple tion afcan2 0540h 00000540h nextpc c2recic 77 intc2trx afcan2 transmission completion afcan2 0550h 00000550h nextpc c2trxic 78 intc3err afcan3 error afcan3 0560h 00000560h nextpc c3erric 79 intc3wup afcan3 wakeup afca n3 0570h 00000570h nextpc c3wupic 80 intc3rec afcan3 reception comple tion afcan3 0580h 00000580h nextpc c3recic maskable interrupt 81 intc3trx afcan3 transmission completion afcan3 0590h 00000590h nextpc c3trxic chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 786 remarks 1. default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. restored pc: the value of t he program counter (pc) saved to eipc or fepc when interrupt servicing is started. note, however, t hat the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (i f an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, and sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value from which the pr ocessing starts following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 787 17.2 non-maskable interrupts 17.2.1 non-maskable interrupt request signal a non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) state. an nmi is not s ubject to priority control and takes precede nce over all the other interrupt request signals. this product has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generated by overflow of watchdog timer (intwdt2) the valid edge of the nmi pin can be selected from four types: ?rising edge? , ?falling edge?, ?both edges?, and ?no edge detection?. nmi function becomes valid when the pmc02 bit of the pmc0 register is set to 1 and the intf02/intr02 bits of the intf0 register is set to any value. the non-maskable interrupt request signal generated by over flow of watchdog timer 2 (intwdt2) functions when the wdm21 and wdm20 bits of the wd tm2 register are set to ?01?. if two or more non-maskable interrupt request signals are g enerated at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). intwdt2 > nmi if a new nmi or intwdt2 request signal is issued while a nmi is being serviced, it is serviced as follows. (1) if new nmi request signal is i ssued while nmi is being serviced the new nmi request signal is held pending, regardless of the value of the np bit of the psw in the cpu. the pending nmi request signal is acknowledged after t he nmi currently under execution has been serviced (after the reti instruction has been executed). (2) if intwdt2 request signal is issued while nmi is being serviced the intwdt2 request signal is held pending if the np bit of the psw remains set (1) while the nmi is being serviced. the pending intwdt2 request signal is ac knowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). if the np bit of the psw is cleared (0) while the nmi is being serviced, the newly generated intwdt2 request signal is executed (the nmi servicing is stopped). caution if a non-maskable interrupt request signal is generated, the va lues of the pc and psw are saved to the nmi status save registers (fepc and fepsw). at this time, execution can be returned by the reti instruction only if the interrupt was ge nerated by the nmi signal. execution cannot be returned while an interrupt generated by the in twdt2 signal is being serviced. therefore, reset the system after the inte rrupt has been serviced. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 788 figure 17-1. non-maskable interrupt re quest signal acknowledgment operation (a) nmi and intwdt2 request signa ls generated at the same time main routine system reset nmi and intwd t2 requests (generated simultaneously) intwd t2 servicing (b) non-maskable interrupt request signal ge nerated during non-maskab le interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt2 nmi ? nmi request generated during nmi servicing ? intwdt2 request generated during nmi servicing (np = 1 retained before intwdt2 request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt2 servicing intwdt2 request ? intwdt2 request generated during nmi servicing (np = 0 set before intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing intwdt2 request np = 0 ? intwdt2 request generated during nmi servicing (np = 0 set after intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing np = 0 ? intwdt2 request generated during intwdt2 servicing main routine system reset intwdt2 request intwdt2 servicing (invalid) ? nmi request generated during intwdt2 servicing intwdt2 main routine system reset intwdt2 request intwdt2 servicing (invalid) nmi request (held pending) intwdt2 request intwdt2 request chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 789 17.2.2 operation if a non-maskable interrupt request signal is generated, th e cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes an exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> sets the handler address (00000010h, 00000020h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-maska ble interrupt is shown in figure 17-2. figure 17-2. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h, 0020h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 790 17.2.3 restore (1) from nmi input execution is restored from nmi serv icing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and f epsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 17-3 illustrates how the reti instruction is processed. figure 17-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw .ep back to 0 and psw.np back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 791 (2) from intwdt2 signal execution cannot be returned from intwdt2 by the re ti instruction. execute the following software reset processing. figure 22-4. software reset processing intwdt2 occurs. fepc software reset processing address fepsw value that sets np bit = 1, ep bit = 0 reti reti 10 times (fepc and fepsw note must be set.) psw psw default value setting initialization processing intwdt2 servicing routine software reset processing routine note fepsw value that sets np bit = 1, ep bit = 0 chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 792 17.2.4 np flag the np flag is a status flag that indicates that non -maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request signal has been acknowledged, and after that, non- maskable interrupt request is reserved. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt currently being serviced np 0 1 non-maskable interrupt servicing status after reset: 00000020h 17.2.5 eliminating noise on nmi pin the nmi pin has a noise eliminator that eliminates noise using analog delay. unless the level input to the nmi pin is held for a specific time, therefore, it cannot be detected as an edge (i.e., the edge is detected after a specific time). the nmi pin is used to release the software stop mode. because the internal system clock is stopped in the software stop mode, noise elimination us ing the system clock is not performed. 17.2.6 function to detect edge of nmi pin the valid edge of the nmi pin can be selected from four types: ?rising edge? , ?falling edge?, ?both edges?, and ?no edge detection?. specify the valid edge of the nmi pin by using the intr0 and intf0 registers. after reset, nmi function is not valid unless the pmc02 bit of the pmc0 register is set to 1 and the intf02/intr02 bits of the intf0 register is set to any value. to use the p00/nmi pin as an i/o port pin, specify that the valid edge of the nmi pin is ?no edge detection?. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 793 (1) external interrupt falling edge specification register 0 (intf0) the intf0 register is an 8-bit regist er that specifies detection of t he falling edge of an nmi via bit 2. this register can be read or written in 8-bit or 1-bit units. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for how to specify a valid edge, see table 17-3 . (2) external interrupt rising edge specification register 0 (intr0) the intr0 register is an 8-bit register that specifies detection of the ri sing edge of the nmi pin via bit 2. this register can be read or written in 8-bit or 1-bit units. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for how to specify a valid edge, see table 17-3 . table 17-3. nmi valid edge specification intf02 intr02 nmi valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 794 17.3 maskable interrupts maskable interrupt request signals can be masked by interr upt control registers. the v850es/fx2 has up to 82 maskable interrupt sources. if two or more maskable interrupt request signals ar e generated at the same ti me, they are acknowledged according to the default priority. in addition to the default prio rity, eight levels of priorities can be specified by using the interrupt control registers (p rogrammable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interr upt enabled (ei) status is set, which enables servicing of interrupts having a higher priority t han the interrupt request signal in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be serviced as multiple interrupts. to enable multiple interrupt servicing, however, save ei pc and eipsw to memory or registers before executing the ei instruction, and ex ecute the di instruction before the reti instruction to restor e the original values of eipc and eipsw. 17.3.1 operation if a maskable interrupt occurs, the cpu performs the foll owing processing, and transfer s control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to t he lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal generated while another interrupt is being serviced (while psw.np = 1 or psw.id = 1) are held pending inside the intc. in this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or psw.np and psw.id are cleared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 795 figure 17-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address interrupt requested? note for details of the ispr register, see 17.3.6 in-service priority register (ispr) . chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 796 17.3.2 restore execution is restored from maskable interrupt servicing by the reti instruction. when the reti instruction is executed , the cpu performs the following steps, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and eipsw be cause the ep bit of the psw is 0 and the np bit of the psw is 0. <2> transfers control to the address of the restored pc and psw. figure 17-5 illustrates the proce ssing of the reti instruction. figure 17-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for details of the ispr register, see 17.3.6 in-service priority register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw .ep back to 0 and psw.np back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 797 17.3.3 priorities of maskable interrupts the intc performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupt servicing can be controlled by priority levels. there are two types of priority level c ontrol: control based on the default pr iority levels, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts hav ing the same priority level specified by the xxprn bit are generated at the same time, interrupt request signals are serv iced in order depending on the priority level allocated to each interrupt request type (default priority le vel) beforehand. for more information, see table 17-2 interrupt source list . programmable priority control customizes interr upt request signals into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowledged, the id flag of the psw is automatically set to 1. therefore, when multiple interrupt servic ing is to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt servici ng program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 17-4 interrupt control registers (xxicn) ) n: peripheral unit number (see table 17-4 interrupt control registers (xxicn) ) chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 798 figure 17-6. example of processing in whic h interrupt request signal is issued while another interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei in struction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. ? a? to ?u? in the figure are assumed names given to interrupt request signals for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 799 figure 17-6. example of processing in whic h interrupt request signal is issued while another interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 800 figure 17-7. example of servicing interrupt request signals genera ted simultaneously default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. ? a? to ?c? in the figure are assumed names given to interrupt request signals for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 801 17.3.4 interrupt control registers (xxicn) an xxicn register is assigned to each interrupt request si gnal (maskable interrupt) and sets the control conditions for each maskable interrupt request. these registers can be read or wri tten in 8-bit or 1-bit units. reset input sets these registers to 47h. caution disable interrupts (di) to read the xxifn bit of the xxi cn register. if the xxi fn bit is read while interrupts are enabled (ei), the correct value may not be read when ackn owledging an interrupt and reading the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff112h to fffff1b2h 6 7 note the flag xxlfn is reset automatically by the hardwa re if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 17-4 interrupt control registers (xxicn) ) n: peripheral unit number (see table 17-4 interrupt control registers (xxicn) ). the addresses and bits of the interrupt control registers are as follows. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 802 table 17-4. interrupt control registers (xxicn) (1/2) bit address register 7 6 5 4 3 2 1 0 fffff110h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff122h tq0ovic tq0ovif tq0ovmk 0 0 0 tq0ovpr2 tq0ovpr1 tq0ovpr0 fffff124h tq0ccic0 tq0ccif0 tq0ccmk0 0 0 0 tq0ccpr02 tq0ccpr01 tq0ccpr00 fffff126h tq0ccic1 tq0ccif1 tq0ccmk1 0 0 0 tq0ccpr12 tq0ccpr11 tq0ccpr10 fffff128h tq0ccic2 tq0ccif2 tq0ccmk2 0 0 0 tq0ccpr22 tq0ccpr21 tq0ccpr20 fffff12ah tq0ccic3 tq0ccif3 tq0ccmk3 0 0 0 tq0ccpr32 tq0ccpr31 tq0ccpr30 fffff12ch tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff12eh tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff130h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 fffff132h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff134h tp1ccic0 tp1ccif0 tp1ccmk0 0 0 0 tp1ccpr02 tp1ccpr01 tp1ccpr00 fffff136h tp1ccic1 tp1ccif1 tp1ccmk1 0 0 0 tp1ccpr12 tp1ccpr11 tp1ccpr10 fffff138h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff13ah tp2ccic0 tp2ccif0 tp2ccmk0 0 0 0 tp2ccpr02 tp2ccpr01 tp2ccpr00 fffff13ch tp2ccic1 tp2ccif1 tp2ccmk1 0 0 0 tp2ccpr12 tp2ccpr11 tp2ccpr10 fffff13eh tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff140h tp3ccic0 tp3ccif0 tp3ccmk0 0 0 0 tp3ccpr02 tp3ccpr01 tp3ccpr00 fffff142h tp3ccic1 tp3ccif1 tp3ccmk1 0 0 0 tp3ccpr12 tp3ccpr11 tp3ccpr10 fffff144h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff146h cb0ric cb0rif cb0rmk 0 0 0 cb0rpr2 cb0rpr1 cb0rpr0 fffff148h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff14ah cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff14ch cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff14eh ua0ric ua0rif ua0rmk 0 0 0 ua0rpr2 ua0rpr1 ua0rpr0 fffff150h ua0tic ua0tif ua0tmk 0 0 0 ua0tpr2 ua0tpr1 ua0tpr0 fffff152h ua1ric ua1rif ua1rmk 0 0 0 ua1rpr2 ua1rpr1 ua1rpr0 fffff154h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff156h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff158h c0erric c0errif c0errmk 0 0 0 c0errpr2 c0errpr1 c0errpr0 fffff15ah c0wupic c0wupif c0wupmk 0 0 0 c0wuppr2 c0wuppr1 c0wuppr0 fffff15ch c0recic c0recif c0recmk 0 0 0 c0recpr2 c0re cpr1 c0recpr0 fffff15eh c0trxic c0trxif c0trxmk 0 0 0 c0trxpr2 c0trxpr1 c0trxpr0 fffff160h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff162h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 803 table 17-4. interrupt control registers (xxicn) (2/2) bit address register 7 6 5 4 3 2 1 0 fffff164h wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff166h pic8 pif8 pmk8 0 0 0 ppr82 ppr81 ppr80 fffff168h pic9 pif9 pmk9 0 0 0 ppr92 ppr91 ppr90 fffff16ah pic10 pif10 pmk10 0 0 0 ppr102 ppr101 ppr100 fffff16ch tq1ovic tq1ovif tq1ovmk 0 0 0 tq1ovpr2 tq1ovpr1 tq1ovpr0 fffff16eh tq1ccic0 tq1ccif0 tq1ccmk0 0 0 0 tq1ccpr02 tq1ccpr01 tq1ccpr00 fffff170h tq1ccic1 tq1ccif1 tq1ccmk1 0 0 0 tq1ccpr12 tq1ccpr11 tq1ccpr10 fffff172h tq1ccic2 tq1ccif2 tq1ccmk2 0 0 0 tq1ccpr22 tq1ccpr21 tq1ccpr20 fffff174h tq1ccic3 tq1ccif3 tq1ccmk3 0 0 0 tq1ccpr32 tq1ccpr31 tq1ccpr30 fffff176h ua2ric ua2rif ua2rmk 0 0 0 ua2rpr2 ua2rpr1 ua2rpr0 fffff178h ua2tic ua2tif ua2tmk 0 0 0 ua2tpr2 ua2tpr1 ua2tpr0 fffff17ah c1erric c1errif c1errmk 0 0 0 c1errpr2 c1errpr1 c1errpr0 fffff17ch c1wupic c1wupif c1wupmk 0 0 0 c1wuppr2 c1wuppr1 c1wuppr0 fffff17eh c1recic c1recif c1recmk 0 0 0 c1recpr2 c1re cpr1 c1recpr0 fffff180h c1trxic c1trxif c1trxmk 0 0 0 c1trxpr2 c1trxpr1 c1trxpr0 fffff182h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff184h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff186h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff188h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff18ah pic11 pif11 pmk11 0 0 0 ppr112 ppr111 ppr110 fffff18ch pic12 pif12 pmk12 0 0 0 ppr122 ppr121 ppr120 fffff18eh pic13 pif13 pmk13 0 0 0 ppr132 ppr131 ppr130 fffff190h pic14 pif14 pmk14 0 0 0 ppr142 ppr141 ppr140 fffff192h tq2ovic tq2ovif tq2ovmk 0 0 0 tq2ovpr2 tq2ovpr1 tq2ovpr0 fffff194h tq2ccic0 tq2ccif0 tq2ccmk0 0 0 0 tq2ccpr02 tq2ccpr01 tq2ccpr00 fffff196h tq2ccic1 tq2ccif1 tq2ccmk1 0 0 0 tq2ccpr12 tq2ccpr11 tq2ccpr10 fffff198h tq2ccic2 tq2ccif2 tq2ccmk2 0 0 0 tq2ccpr22 tq2ccpr21 tq2ccpr20 fffff19ah tq2ccic3 tq2ccif3 tq2ccmk3 0 0 0 tq2ccpr32 tq2ccpr31 tq2ccpr30 fffff19ch cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff19eh cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff1a0h ua3ric ua3rif ua3rmk 0 0 0 ua3rpr2 ua3rpr1 ua3rpr0 fffff1a2h ua3tic ua3tif ua3tmk 0 0 0 ua3tpr2 ua3tpr1 ua3tpr0 fffff1a4h c2erric c2errif c2errmk 0 0 0 c2errpr2 c2errpr1 c2errpr0 fffff1a6h c2wupic c2wupif c2wupmk 0 0 0 c2wuppr2 c2wuppr1 c2wuppr0 fffff1a8h c2recic c2recif c2recmk 0 0 0 c2recpr2 c2re cpr1 c2recpr0 fffff1aah c2trxic c2trxif c2trxmk 0 0 0 c2trxpr2 c2trxpr1 c2trxpr0 fffff1ach c3erric c3errif c3errmk 0 0 0 c3errpr2 c3errpr1 c3errpr0 fffff1aeh c3wupic c3wupif c3wupmk 0 0 0 c3wuppr2 c3wuppr1 c3wuppr0 fffff1b0h c3recic c3recif c3recmk 0 0 0 c3recpr2 c3re cpr1 c3recpr0 fffff1b2h c3trxic c3trxif c3trxmk 0 0 0 c3trxpr2 c3trxpr1 c3trxpr0 chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 804 17.3.5 interrupt mask registers 0 to 5 (imr0 to imr4, imr5l) the imr0 to imr4, imr5l registers set the interrupt mask state for the maskabl e interrupts. the xxmkn bit of the imr0 to imr4 and imr5l registers is equivalent to the xxmkn bit of the xxicn register. the imrm register can be read or written in 16-bit units (m = 0 to 4). the imr5l register can be read or wr itten in 8-bit or 1-bit units. if the higher 8 bits of the imrm register are used as the imrmh register and t he lower 8 bits as the imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 4). reset input sets these registers to ffffh. bits 7 to 2 of the imr5l register are fixed to 1. if these bits are not 1, the o peration cannot be guaranteed. reset input sets these registers to ffffh. caution the device file defines the xxmkn bit of the xxicn register as a reserved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register , instead of the imrm register, are rewritten (as a resu lt, the contents of the imrm register are also rewritten). (1/2) after reset: ffh r/w address: ffff10ah 7 6 5 4 3 2 1 0 imr5l 1 1 1 1 1 1 c3trxmk c3recmk caution set bits 7 to 2 of the imr5l register to 1. after reset: ffffh r/w address: ffff108h 15 14 13 12 11 10 9 8 imr4 c3wupmk c3errmk c2trxmk c2recmk c2wupmk c2errmk ua3tmk ua3rmk 7 6 5 4 3 2 1 0 cb2tmk cb2rmk tq2ccmk3 tq2ccmk2 tq2ccmk1 tq2ccmk0 tq2ovmk pmk14 after reset: ffffh r/w address: ffff106h 15 14 13 12 11 10 9 8 imr3 pmk13 pmk12 pmk11 dmamk3 dmam k2 dmamk1 dmamk0 c1trxmk 7 6 5 4 3 2 1 0 c1recmk c1wupmk c1errmk ua2tmk ua 2rmk tq1ccmk3 tq1ccmk2 tq1ccmk1 after reset: ffffh r/w address: ffff104h 15 14 13 12 11 10 9 8 imr2 tq1ccmk0 tq1ovmk pmk10 pmk9 pmk8 wtmk wtimk krmk 7 6 5 4 3 2 1 0 c0trxmk c0recmk c0wupmk c0errmk admk ua1tmk ua1rmk ua0tmk chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 805 (2/2) after reset: ffffh r/w address: ffff102h 15 14 13 12 11 10 9 8 imr1 ua0rmk cb1tmk cb1rmk cb0tmk cb 0rmk tm0eqmk0 tp3ccmk1 tp3ccmk0 7 6 5 4 3 2 1 0 tp3ovmk tp2ccmk1 tp2ccmk0 tp2ovmk tp1ccmk1 tp1ccmk0 tp1ovmk tp0ccmk1 after reset: ffffh r/w address: ffff100h 15 14 13 12 11 10 9 8 imr0 tp0ccmk0 tp0ovmk tq0ccmk3 tq0ccm k2 tq0ccmk1 tq0ccmk0 tq0ovmk pmk7 7 6 5 4 3 2 1 0 pmk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk xxmkn interrupt mask flag setting 0 interrupt servicing enabled 1 interrupt servicing disabled remark xx: identification name of each peripheral unit (see table 17-4 interrupt control registers (xxicn) ). n: peripheral unit number (see table 17-4 interrupt control registers (xxicn) ) chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 806 17.3.6 in-service priority register (ispr) the ispr register holds the priority level of the maskable interrupt curr ently acknowledged. when an interrupt request signal is acknowledged, the bit of this register corresponding to the priori ty level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is execut ed, the bit corresponding to the in terrupt request signal having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non- maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) state, the value of the ispr regist er after the bits of the register have been set by acknowledging the interrupt may be read. to accura tely read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di). ispr7 interrupt request signal with priority n not acknowledged interrupt request signal with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah 7654 3210 remark n = 0 to 7 (priority level) chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 807 17.3.7 id flag this is the interrupt disable flag and controls the ma skable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt request signals. the id flag is assigned to the psw. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 specification of maskable interrupt servicing note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instru ction when referencing the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, the id flag is automatically set to 1 by hardware. an interrupt request signal generated during t he acknowledgment disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0. 17.3.8 watchdog timer mode register 2 (wdtm2) the wdtm2 register is a special register and can only be written in a specific sequence. this register can be read or writt en in 8-bit units (for details, see chapter 11 functions of watchdog timer 2 ). reset input sets this register to 67h. 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode reset mode (initial-value) wdm21 0 0 1 wdm20 0 1 selection of watchdog timer operation mode remark for the wdcs24 to wdcs20 bits refer to chapter 11 functions of watchdog timer 2 . chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 808 17.3.9 eliminating noise on intp0 to intp7 pins the intp0 to intp7 pins have a noise el iminator that eliminates noise using analog delay. unless the level input to each pin is held for a specific time , therefore, it c annot be detected as a signal edge (i.e., the edge is detected after a specific time). noise elimination by analog delay or digital noise elimination can be selected for the intp3 pin. 17.3.10 function to detect edge of intp0 to intp14 pins the valid edge of the intp0 to intp14 pins can be selected from the following four. ? rising edge ? falling edge ? both edges ? no edge detection (1) external interrupt falling edge specification register 0 (intf0) the intf0 register is an 8-bit register that specifies detection of the fa lling edge of the non-maskable interrupt pin (nmi) via bit 2 or external interrupt pi ns (intp0 to intp3) via bits 3 to 6. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for how to specify a valid edge, see table 17-5 . chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 809 (2) external interrupt rising edge specification register 0 (intr0) the intr0 register is an 8-bit regist er that specifies detection of the rising edge of the non-maskable interrupt pin (nmi) via bit 2 or external interrupt pi ns (intp0 to intp3) via bits 3 to 6. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for how to specify a valid edge, see table 17-5 . table 17-5. valid edge sp ecification (intf0n, intr0n) intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 2: nmi pin control n = 3: intp0 pin control n = 4: intp1 pin control n = 5: intp2 pin control n = 6: intp3 pin control caution be sure to clear the intf0n and intr0n bi ts to 00 when these regist ers are not specified as nmi or intp0 to intp3. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 810 (3) external interrupt falling edge specification register 1 (intf1) the intf1 register is an 8-bit regist er that specifies detection of the fa lling edge of external interrupt pins (intp9, intp10) via bits 0 and 1. this register can be read or written in 8-bit or 1-bit units. reset input cleats this register to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf1n and intr1n bits to 0, and then set the port mode. intf1 after reset: 00h r/w address: fffffc02h 0 0 0 0 0 0 intf11 intf10 remark for how to specify a valid edge, see table 17-6 . chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 811 (4) external interrupt rising edge specification register 1 (intr1) the intr1 register is an 8-bit register that specifies detection of the rising edge of external interrupt pins (intp9, intp10) via bits 0 and 1. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf1n and intr1n bits to 0, and then set the port mode. intr1 after reset: 00h r/w address: fffffc22h 0 0 0 0 0 0 intr11 intr10 remark for how to specify a valid edge, see table 17-6 . table 17-6. valid edge sp ecification (intf1n, intr1n) intf1n bit intr1n bit valid edge specification (n = 0, 1) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 0: intp9 pin control n = 1: intp10 pin control caution be sure to clear the intf1n and intr1n bits to 00 when these re gisters are not used as intp9 and intp10. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 812 (5) external interrupt falling edge specification register 3 (intf3) the intf3 register is a 16-bit regist er that specifies detection of the fa lling edge of external interrupt pins (intp7, intp8) via bits 1 and 9. this register can be read or written in 16-bit units. however, when the higher 8 bits of intf3 register are us ed as the intf3h register and the lower 8 bits as the intf3l register, they can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefor e, clear the intf3n and intr3n bits to 0, and then set the port mode. after reset: 0000h r/w address: fffffc06h, fffffc07h 15 14 13 12 11 10 9 8 intf3 (intf3h note ) 0 0 0 0 0 0 intf39 0 7 6 5 4 3 2 1 0 (intf3l) 0 0 0 0 0 0 intf31 0 note when bits 8 to 15 of the intf3 register are read or written in 8-bit or 1-bit units, specify them as bits 0 to 7 of the intf3h register remark for how to specify a valid edge, see table 17-7 . chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 813 (6) external interrupt rising edge specification register 3 (intr3) the intr3 register is a 16-bit register that specifie s detection of the rising edge of external interrupt pins (intp7, intp8) via bits 1 and 9. this register can be read or written in 16-bit units. however, when the higher 8 bits of intr3 register are us ed as the intr3h register an d the lower 8 bits as the intr3l register, they can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefor e, clear the intf3n and intr3n bits to 0, and then set the port mode. after reset: 0000h r/w address: fffffc26h, fffffc27h 15 14 13 12 11 10 9 8 intr3 (intr3h note ) 0 0 0 0 0 0 intr39 0 7 6 5 4 3 2 1 0 (intr3l) 0 0 0 0 0 0 intr31 0 note when bits 8 to 15 of the intr3 register are read or written in 8-bit or 1-bit units, specify them as bits 0 to 7 of the intr3h register remark for how to specify a valid edge, see table 17-7 . table 17-7. valid edge sp ecification (intf3n, intr3n) intf3n bit intr3n bit valid edge specification (n = 1, 9) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 1: intp7 pin control n = 9: intp8 pin control caution be sure to clear the intf3n and intr3n bi ts to 00 when these regist ers are not specified as intp7 and intp8. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 814 (7) external interrupt fa lling edge specification register 6l (intf6l) the intf6l register is an 8-bit register that specifies detection of the falling edge of external interrupt pins (intp11 to intp13) via bits 0 to 2. this regist er can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf6n and intr6n bits to 0, and then set the port mode. after reset: 00h r/w address: fffffc0ch 7 6 5 4 3 2 1 0 intf6l 0 0 0 0 0 intf62 intf61 intf60 remark for how to specify a valid edge, see table 17-8 . (8) external interrupt rising edge specification register 6l (intr6l) the intr6l register is an 8-bit regist er that specifies detection of the ri sing edge of external interrupt pins (intp11 to intp13) via bits 0 to 2. this regist er can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf6n and intr6n bits to 0, and then set the port mode. after reset: 00h r/w address: fffffc2ch 7 6 5 4 3 2 1 0 intr6l 0 0 0 0 0 intr62 intr61 intr60 remark for how to specify a valid edge, see table 17-8 . table 17-8. valid edge sp ecification (intf6n, intr6n) intf6n bit intr6n bit valid edge specification (n = 0 to 2) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 0: intp11 pin control n = 1: intp12 pin control n = 2: intp13 pin control caution be sure to clear the intf6n and intr6n bi ts to 00 when these regist ers are not specified as intp11 to intp13. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 815 (9) external interrupt falling edge specification register 8 (intf8) the intf8 register is an 8-bit register that specifies detection of the falling edge of an external interrupt pin (intp8) via bit 0. this register can be re ad or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefo re, clear the intf80 and intr80 bits to 0, and then set the port mode. after reset: 00h r/w address: fffffc10h 7 6 5 4 3 2 1 0 intf8 0 0 0 0 0 0 0 intf80 remark for how to specify a valid edge, see table 17-9 . (10) external interrupt rising ed ge specification register 8 (intr8) the intr8 register is an 8-bit regist er that specifies detection of the ri sing edge of an external interrupt pin (intp8) using bit 0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefo re, clear the intf80 and intr80 bits to 0, and then set the port mode. after reset: 00h r/w address: fffffc30h 7 6 5 4 3 2 1 0 intr8 0 0 0 0 0 0 0 intr80 remark for how to specify a valid edge, see table 17-9 . table 17-9. valid edge sp ecification (intf80, intr80) intf80 bit intr80 bit valid edge specification 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark intp14 pin control caution be sure to clear the intf80 and intr80 bits to 00 when these register s are not specified as intp14. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 816 (11) external interrupt falling edge specification register 9h (intf9h) the intf9h register is an 8-bit register that specifie s detection of the falling edge of external interrupt pins (intp4 to intp6) via bits 5 to 7. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf9n and intr9n bits to 0, and then set the port mode. intf9h after reset: 00h r/w address: fffffc13h inth915 intf914 intf913 0 0 0 0 0 0 1 2 3 4 5 6 7 remark for how to specify a valid edge, see table 17-10 . (12) external interrupt rising edge specification register 9h (intr9h) the intr9h register is an 8-bit register that specifie s detection of the rising edge of external interrupt pins (intp4 to intp6) via bits 5 to 7. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf9n and intr9n bits to 0, and then set the port mode. intr9h after reset: 00h r/w address: fffffc33h intr915 intr914 intr913 0 0 0 0 0 0 1 2 3 4 5 6 7 remark for how to specify a valid edge, see table 17-10 . table 17-10. valid edge specification (intf9n, intr9n) intf9n bit intr9n bit valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 13: intp4 pin control n = 14: intp5 pin control n = 15: intp6 pin control caution be sure to clear the intf9n and intr9n bits to 00 when these re gisters are not used as intp4 to intp6. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 817 (13) noise elimination control register (nfc) digital noise elimination can be selected for the intp3 pi n. the noise elimination settings are performed using the nfc register. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, and f xt . sampling is performed 2 or 3 times. even when digital noise elimination is selected, using fx t as the sampling clock makes it possible to use the intp3 interrupt request signal to release the idle1, idle2 and software stop modes. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution after the sampling clock has been changed; it takes "set number by nfsts bit" sampling clocks to initialize the digital noise elim inator. therefore, if an intp3 va lid edge is input within these "set number by nfsts bit" sampling clocks after the sampling clock has been changed, an interrupt request signal may be generated. therefore, be car eful about the following points when using the interrupt and dma functions. when using the interrupt function, after the "set number by nfsts bit" sampling clocks have elapsed, enable interrupts after the interrupt request flag (bit 7 of pic3) has been cleared. when using the dma function (started by intp3) , enable dma after "set number by nfsts bit" sampling clocks have elapsed. nfen nfc nfsts 0 0 0 nfc2 nfc1 nfc0 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xt (subclock) nfc2 0 0 0 0 1 1 digital sampling clock setting prohibited nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff318h analog noise elimination (60 ns (typ.)) digital noise elimination nfen 0 1 settings of intp3 pin noise elimination other than above sampling performed = 3 sampling performed = 2 nfsts 0 1 setting of sampling performed for digital noise elimination remarks 1. since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 818 17.4 software exceptions a software exception is generated when the cpu ex ecutes the trap instruction, and can always be acknowledged. 17.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> sets the handler address (00000040h or 00000050h ) corresponding to the software exception to the pc, and transfers control. figure 17-8 illustrates the proce ssing of a software exception. figure 17-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 0 to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 0 to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 819 17.4.2 restore execution is restored from software exceptio n processing by the reti instruction. when the reti instruction is executed, the cpu carries out the following processing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. caution dbpc and dbpsw can be access from executi on of the dbtrap instruction or illegal instruction till execution of the dbret instruction only. figure 17-9 illustrates the proce ssing of the reti instruction. figure 17-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during software exception processing, in order to r estore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 820 17.4.3 ep flag the ep flag is bit 6 of the psw, and is a status flag used to indicate that except ion processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 821 17.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/fx2, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 17.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the followi ng processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) correspondi ng to the exception trap to the pc, and transfers control. figure 17-10 illustrates the processing of the exception trap. chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 822 figure 17-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from an exc eption trap by the dbret instruction. when the dbret instruction is executed, the cpu carries out the following processi ng and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 17-11 illustrates the processing for restoring from an exception trap. figure 17-11. processing of restoration from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 823 17.5.2 debug trap a debug trap is an exception that is generated when the dbtrap instru ction is executed and is always acknowledged. upon occurrence of a debug trap, the cpu pe rforms the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) for the debug trap to the pc and transfers control. figure 17-12 illustrates the processing of the debug trap. figure 17-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 824 (2) restore execution is restored from a debug trap by the dbret instruction. when the dbret instruction is execut ed, the cpu carries out the following processing and transfers control to the address of the restored pc. <1> reads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the fetche d address of the restored pc and psw. table 17-13 illustrates the processing for restoring from a debug trap. figure 17-13. processing of restoration from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 825 17.6 interrupt acknowledgment time of cpu except the following cases, the interrupt acknowledgment time of the cp u is 4 clocks minimum. to input interrupt request signals successively, input the next interrupt req uest signal at least 4 clocks after the preceding interrupt. ? in software stop mode ? when the external bus is accessed ? when interrupt request non-sampling instructions are successively executed (see 17.7 periods in which interrupts are not acknowledged by cpu .) ? when an interrupt control register is accessed figure 17-14. pipeline operation at interr upt request signal acknowledgment (outline) internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt service routine) interrupt request if id ex df wb ifx idx 4 system clocks if if id ex int1 int2 int3 int4 remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledgment time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle1/idle2/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register and programmable peripheral i/o register chapter 17 interrupt/exception processing function user?s manual u17830ee1v0um00 826 17.7 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instructi on and the next instruction (int errupt is held pending). the interrupt request non-sample instructions are as follows. ei instruction di instruction ldsr reg2, 0x5 instruction (for psw) the store, set1, not1, or clr1 inst ructions for the following registers. interrupt-related registers: - interrupt control register (xxicn), inte rrupt mask registers 0 to 4 (imr0 to imr4) - in-service priority register (ispr) - command register (prcmd) - power save control register (psc) - on-chip debug mode register (ocdm) - peripheral emulation register 1 (pemu1) remark xx: identification name of each peripheral unit (see table 17-4 interrupt control registers (xxicn) ) n: peripheral unit number (see table 17-4 interrupt control registers (xxicn) ). user?s manual u17830ee1v0um00 827 chapter 18 key interrupt function 18.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the key return mode register (krm). table 18-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 18-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 18 key interrupt function preliminary user?s manual u17830ee1v0um00 828 18.2 control register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. reset input clears this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 control of key return mode krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution rewrite the krm register after once clearing the krm register to 00h. remark for the alternate-function pin settings, see table 4-25 register settings to use port pins as alternate-function pins (3/7) 18.3 cautions (1) if a low level is input to any of the kr0 to kr7 pins , the intkr signal is not generated even if the falling edge of another pin is input. (2) the rxda1 and kr7 pins must not be used at the same time. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) if the krm register is changed, an interrupt reques t signal (intkr) may be generated. to prevent this, change the krm register after disabling interrupts (di) or masking, then clear the interrupt request flag (kric.krif bit) to 0, and enable interrupts (ei) or clear the mask. (4) to use the key interrupt function, be sure to set the po rt pin to the key return pin and then enable the operation with the krm register. to switch from the key return pin to the port pin, disable the operation with the krm register and then set the port pin. user?s manual u17830ee1v0um00 829 chapter 19 standby function 19.1 overview the power consumption of the system can be effectively reduced by using t he standby modes in combination and selecting the appropriate mode for the applicati on. the available standby modes are listed below. table 19-1. standby modes mode functional outline halt mode mode in which only the operating clock of the cpu is stopped idle1 mode mode in which all the internal operations of the chip except the oscillator, pll note , and flash memory are stopped idle2 mode mode in which all the internal operations of the chip except the oscillator are stopped software stop mode mode in which all the internal operations of the chip except the subclock oscillator are stopped subclock operation mode mode in which the subclock is used as the internal system clock sub-idle mode mode in which all the internal operations of the chip except the oscillator, pll note , and flash memory are stopped, in the subclock operation mode note the pll holds the previous operating st atus (in clock-through mode or pll mode). chapter 19 standby function user?s manual u17830ee1v0um00 830 figure 19-1. status transition diagram reset note 3 note 2 note 1 oscillation stabilization wait x1 main clock-through (pll = on) sub operation (x1 = on) (pll = on) ring operation each stby (halt/idle1/idle2/ software stop) pll operation (pll = on) each stby (halt/idle1/idle2/ software stop) stby (sub idle only) (x1 = on) (pll = on) sub operation (x1 = off) (pll = off) stby (sub idle only) (x1 = off) (pll = off) x1 main through (pll = off) each stby (halt/idle1/idle2/ software stop) sub operation (x1 = on) (pll = off) stby (sub idle only) (x1 = on) (pll = off) notes 1. pll lockup time is required (lock bit of lockr register = 1 0). 2. oscillation stabilization time must be secured by program. each standby -> pll operation (pll=on) each standby -> x1 main clock-through (pll = on) 3. if the watchdog timer overflows (reset) while the o scillation stabilization time is being counted, the cpu starts clock operation with the ring oscillator. remark for plls and osts, refer to chapter 6 clock generation function and chapter 19.8(3) oscillation stabilization time selection function . chapter 19 standby function user?s manual u17830ee1v0um00 831 figure 19-2. standby transition from pll operation (pll = on) pll operation (pll = on) idle2 mode idle1 mode software stop mode halt mode x1 = on, pll = on x1 = off, pll = off x1 = on, pll = on x1 = on, pll = off note 2 note 1 notes 1. after the lapse of the time set by the osts register, the cpu returns to the pll mode. 2. after the lapse of the time set by the osts register, the cpu returns to the pll mode. if the watchdog timer overflows (reset) while the oscillation stabiliz ation time is being counted, the cpu starts clock operation with the ring oscillator. remark for osts, refer to chapter 19.8(3) oscillation stabil ization time selection function . figure 19-3. standby transition from x1 main clock-through operation (pll = on) x1 main clock-through mode (pll = on) idle2 mode idle1 mode software stop mode halt mode x1 = on, pll = on x1 = off, pll = off x1 = on, pll = on x1 = on, pll = off note 2 note 1 notes 1. after the lapse of the time set by the osts register, the cpu returns to the through mode. 2. after the lapse of the time set by the osts regi ster, the cpu returns to the through mode. if the watchdog timer overflows (reset) while the oscillati on stabilization time is c ounted, the cpu starts its clock operation with the ring oscillator. remark for osts, refer to chapter 19.8(3) oscillation stabil ization time selection function . chapter 19 standby function user?s manual u17830ee1v0um00 832 figure 19-4. standby transition from x1 main clock-through operation (pll = off) x1 main clock-through mode (pll = off) idle2 mode idle1 mode software stop mode halt mode x1 = on, pll = off x1 = off, pll = off x1 = on, pll = off x1 = on, pll = off note 2 note 1 notes 1. after the lapse of the time set by the osts register, the cpu returns to the through mode. 2. after the lapse of the time set by the osts regi ster, the cpu returns to the through mode. if the watchdog timer overflows (reset) while the oscillati on stabilization time is c ounted, the cpu starts its clock operation with the ring oscillator. remark for osts, refer to chapter 19.8(3) oscillation stabil ization time selection function . chapter 19 standby function user?s manual u17830ee1v0um00 833 figure 19-5. status transition di agram (during subclock operation) normal operation mode (main clock operation) wait for oscillation stabilization sub-idle mode subclock operation mode end of counting oscillation stabilization time reset note 1 main clock operation setting subclock operation setting idle mode setting interrupt note 2 reset note 1 notes 1. reset by reset pin input, wdt2res signal, low vo ltage detector (lvi), and clock monitor (clm) 2. non-maskable interrupt request signal (nmi or intw dt2), unmasked external interrupt request signal, or internal maskable interrupt request signal that can operate in the sub-idle mode and is not masked chapter 19 standby function user?s manual u17830ee1v0um00 834 19.2 halt mode 19.2.1 setting and operation status when a dedicated instruction (halt instruction) is execut ed in the normal operation mode, the halt mode is set. in this mode, the clock oscillator continues operating, bu t clock supply to the cpu is stopped. clock supply to the other on-chip peripheral functions continues. as a result, program execution is st opped, and the contents of the internal ram before the halt mode was set are retained. however, the on-chip peripheral functions that are not dependent upon the inst ruction processing of the cpu continue operating. table 19-3 shows the operation status in the halt mode. the halt mode can reduce the average curr ent consumption of the system if it is used with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an interrupt request signal is held pending, the halt mode is set but is released immediat ely by the pending interrupt request. 19.2.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked inter nal interrupt request of a peripheral function that can operate in the halt mode, or reset signal (reset by reset pin input, wdt2res signal, low voltage detector (lvi), or clock monitor (clm)). when the halt mode has been released, t he normal operation mode is restored. (1) non-maskable interrupt request signal an d unmasked maskable interrupt request signal the halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the halt mode is set in an interrupt routine, however, the operation is performed as follows. (a) if an interrupt request signal having a priority lowe r than that of the interrupt request currently being serviced is generated, the halt mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held. (b) if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt request currently being se rviced is generated, the halt mode is released, and this interrupt request signal is acknowledged. table 19-2. operation after halt mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed. the next instruction is executed. chapter 19 standby function user?s manual u17830ee1v0um00 835 (2) releasing by reset input the operation is the same as the normal reset operation. table 19-3. operation status in halt mode operation status setting of halt mode item without subclock with subclock main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll operable cpu stops operation dma operable interrupt controller operable timer p (tmp0 to tmp3) operable timer q (tmq0 to tmq3) operable timer m (tmm0) operable when other than f xt is selected as the count clock operable watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable csib0 to csib2 operable serial interface uarta0 to uarta3 operable can controller operable a/d converter operable key interrupt function (kr) operable external bus interface refer to chapter 5 bus control function . port function holds status before halt mode is set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before halt mode was set. chapter 19 standby function user?s manual u17830ee1v0um00 836 19.3 idle1 mode 19.3.1 setting and operation status the idle1 mode is set when the psm1 and psm0 bits of the psmr register are cleared to ?00? and the stp bit of the psc register is set to 1 in the normal operation mode. in the idle1 mode, the clock oscillator, pll, and flash me mory continue operating, but clock supply to the cpu and the other on-chip periphe ral functions is stopped. as a result, program execution is stopped, and the conten ts of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral func tions stop operating. however, the on-chip peripheral functions that can operate on the subclock or external clock continue operating. table 19-5 shows the operation status in the idle1 mode. the idle1 mode can reduce current consumption more than the halt mode because the operations of the on- chip peripheral functions are stopped. because the main clock oscillator is not stopped, however, the normal mode can be restored without having to secure oscillation stabiliza tion time, in the same manner as in the halt mode, when the idle1 mode is released. caution insert five or more nop inst ructions after the store instructi on that manipulates the psc register to set the idle2 mode. 19.3.2 releasing idle1 mode the idle1 mode is released by a non-maskable interrup t request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked inter nal interrupt request signal of a peripheral function that can operate in the idle1 mode, or reset signal (reset by reset pin input, wdt2res signal, low voltage detector (lvi), or clock monitor (clm)). when the idle1 mode has been released, the normal operation mode is restored. cautions 1. interrupt request signals that are set (di sabled) by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the idle1 mode. 2. when digital noise elimination is selected by setting of nfc register, and the sampling clock can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, idle1 mode can not released using intp3 pin. for de tail, refer to 17.3.10 (13) noise elimination control register. (1) non-maskable interrupt request signal an d unmasked maskable interrupt request signal the idle1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle1 mode is set in an interrupt routine, however, the operation is performed as follows. (a) if an interrupt request signal having a priority lowe r than that of the interrupt request currently being serviced is generated, the idle1 mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held. (b) if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt request currently being se rviced is generated, the idle1 mode is released, and this interrupt request signal is acknowledged. chapter 19 standby function user?s manual u17830ee1v0um00 837 table 19-4. operation after idle1 mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed. the next instruction is executed. (2) releasing by reset input the operation is the same as the normal reset operation. table 19-5. operation status in idle1 mode operation status setting of idle1 mode item without subclock with subclock main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll operable cpu stops operation dma stops operation interrupt controller stops operation (however, can be used to release standby mode). timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq3) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when fr/8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable csib0 to csib2 operable when sckbn input clock is selected as the operating clock (n = 0 to 2) serial interface uart0-uart3 stop operation (however, operable when ascka0 input clock is selected as the operating clock) can controller stops operation a/d converter stops operation note key interrupt function (kr) operable external bus interface refer to chapter 5 bus control function . port function holds status before idle1 mode is set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before idle1 mode was set. note to realize low power consumption, stop the a/ d converter before shifting to the idle1 mode. chapter 19 standby function user?s manual u17830ee1v0um00 838 19.4 idle2 mode 19.4.1 setting and operation status the idle2 mode is set when the psm1 and psm0 bits of the psmr register are set to ?10? and the stp bit of the psc register is set to 1 in the normal operation mode. in the idle2 mode, the clock oscillator continues operatin g, but clock supply to the cpu, pll, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution is stopped, and the conten ts of the internal ram before the idle2 mode was set are retained. not only the cpu but also the other on-chop peripheral functions stop operating. however, the on-chip peripheral functions that can o perate on the subclock or external clock continue operating. table 19-7 shows the operation status in the idle2 mode. the idle2 mode can reduce current consumption more than the idle1 mode because the operations of the on- chop peripheral functions and flash memory are stopped. because the pll and flash memory are stopped, however, setup time for the pll and flash memory is required after the idle2 mode is released. caution insert five or more nop inst ructions after the store instructi on that manipulates the psc register to set the idle2 mode. 19.4.2 releasing idle2 mode the idle2 mode is released by a non-maskable interrup t request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked inter nal interrupt request of a peripheral function that can operate in the idle2 mode, or reset signal (reset by rese t pin input, wdt2res signal, low voltage detector (lvi), or clock monitor (clm)). the pll returns to t he operation status before the idle2 mode was set. when the idle2 mode has been released, the normal operation mode is restored. cautions 1. interrupt request signals that are set (di sabled) by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the idle2 mode. 2. when digital noise elimination is selected by setting of nfc register, and the sampling clock can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, idle2 mode can not released using intp3 pin. for de tail, refer to 17.3.10 (13) noise elimination control register. (1) non-maskable interrupt request signal an d unmasked maskable interrupt request signal the idle2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle2 mode is set in an interrupt routine, however, the operation is performed as follows. (a) if an interrupt request signal having a priority lowe r than that of the interrupt request currently being serviced is generated, the idle2 mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held. (b) if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt request currently being se rviced is generated, the idle2 mode is released, and this interrupt request signal is acknowledged. chapter 19 standby function user?s manual u17830ee1v0um00 839 table 19-6. operation after idle2 mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler addres s after the specified setup time is secured. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed after the specified setup time is secured. the next instruction is executed after the specified setup time is secured. (2) releasing by reset input the operation is the same as the normal reset operation. table 19-7. operation status in idle2 mode operation status setting of idle2 mode item without subclock with subclock main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (however, can be used to release standby mode). timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq3) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable csib0 to csib2 operable when sckbn input clock is selected as the operating clock (n = 0 to 2) serial interface uart0-uart3 stop operation (however, operable when ascka0 input clock is selected as the operating clock) can controller stops operation a/d converter stops operation note key interrupt function (kr) operable external bus interface refer to chapter 5 bus control function . port function holds status before idle2 mode is set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before idle2 mode was set. note to realize low power consumption, stop the a/ d converter before shifting to the idle2 mode. chapter 19 standby function user?s manual u17830ee1v0um00 840 19.4.3 securing setup time after release of idle2 mode the main clock oscillator stops operating when the idle2 mode is set. therefore, secure the setup time of rom (flash memory) after re leasing the idle2 mode. (1) releasing by non-maskable interrupt request si gnal or unmasked maskable in terrupt request signal the setup time is secured by setting the osts register. when a source that releases the idle2 mode occurs , an internal dedicated timer starts counting in accordance with the setting of the osts register. when this counter overflows, the normal operation mode is restored. oscillation waveform rom circuit stops. counting of setup time main clock idle mode status interrupt request (2) releasing by reset input (reset pin input or wd t2res occurrence) the operation is the same as the normal reset operation. the oscillation stabilization time is the default value of the osts register, 2 16 /f x . chapter 19 standby function user?s manual u17830ee1v0um00 841 19.5 software stop mode 19.5.1 setting and operation status the software stop mode is set when the psm1 and psm0 bits of the psmr register are set to ?01? or ?11?, and the stp bit of the psc register is set to 1 in the normal operation mode. in the software stop mode, the subclock oscillator cont inues operating, but the main clock oscillator stops operating. moreover, clock supply to the cpu and t he other on-chip peripheral functions is stopped. as a result, program execution is st opped, and the contents of the internal ram before the software stop mode was set are retained. not only the cpu but also the other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that c an operate on the subclock or exte rnal clock continue operating. table 19-9 shows the operation status in the software stop mode. the software stop mode can reduce curr ent consumption more than the id le2 mode because the operation of the main clock oscillator is stopped. when the subclock oscillator, ring-osc, and external clock are not used, the current consumption can be substantially reduc ed with only a leakage current flowing. caution insert five or more nop inst ructions after the store instructi on that manipulates the psc register to set the software stop mode. chapter 19 standby function user?s manual u17830ee1v0um00 842 19.5.2 releasing software stop mode the software stop mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked in ternal interrupt request signal of a peripheral function that can operate in the software stop mode, or reset signal (reset by reset pin input, wdt2res signal, or low voltage detector (lvi)). when the software stop mode has been releas ed, the normal operation mode is restored. cautions 1. interrupt request signals that are set (disabled) by the nm i1m, nmi0m, and intm bits of the psc register are invalid and do not release the software stop mode. 2. when digital noise eliminatio n is selected by setting of nfc register, and the sampling clock can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, software stop mode can not released using intp3 pin. for detail, refe r to 17.3.10 (13) noi se elimination control register. (1) non-maskable interrupt request signal an d unmasked maskable interrupt request signal the software stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the software stop mode is set in an interrupt routine, however, t he operation is performed as follows. (a) if an interrupt request signal having a priority lowe r than that of the interrupt request currently being serviced is generated, the software stop mode is re leased, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held. (b) if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt reques t currently being serviced is generated, the software stop mode is released, and this interrupt request signal is acknowledged. table 19-8. operation after software stop mo de is released by in terrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after the oscillation stabilization time is secured. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed the after the oscillation stabilization time is secured. the next instruction is executed after the oscillation stabilization time is secured. chapter 19 standby function user?s manual u17830ee1v0um00 843 (2) releasing by reset input the operation is the same as the normal reset operation. table 19-9. operation status in software stop mode operation status setting of software stop mode item without subclock with subclock main clock oscillator stops oscillation subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq3) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r is selected as the count clock csib0 to csib2 operable when sckbn input clock is selected as the operating clock (n = 0 to 2) serial interface uart0-uart3 stop operation (however, operable when ascka0 input clock is selected as the operating clock) can controller stops operation a/d converter stops operation note key interrupt function (kr) operable external bus interface refer to chapter 5 bus control function . port function holds status before software stop mode is set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before software stop mode was set. notes: 1. if the stop mode is set while the a/d conv erter is operating, the a/d converter is automatically stopped and it starts operating again after the stop mode is released. however, in that case, the a/d conversion results up to the second conversion after the stop mode is released are invalid (the third or later conversion results are valid). all the a/d co nversion results before the stop mode is set are invalid. 2. even if the stop mode is set while the a/d converter is operating, the power consumption is reduced equivalently to when the a/d conver ter is stopped before the stop mode is set. chapter 19 standby function user?s manual u17830ee1v0um00 844 19.5.3 securing setup time after release of software stop mode the main clock oscillator stops operating when the software stop mode is set. therefore, secure the oscillation stabilization time of the main clock oscillat or after releasing the software stop mode. (1) releasing by non-maskable interrupt request si gnal or unmasked maskable in terrupt request signal the oscillation stabilization time is secured by setting the osts register. when a source that releases the software stop mode o ccurs, an internal dedicated timer starts counting in accordance with the setting of the osts register. when this counter overflows, the normal operation mode is restored. oscillation waveform rom circuit stops counting of setup time main clock idle mode status interrupt request (2) releasing by reset input the operation is the same as the normal reset operation. the oscillation stabilization time is the default value of the osts register, 2 16 /f x . chapter 19 standby function user?s manual u17830ee1v0um00 845 19.6 subclock operation mode 19.6.1 setting and operation status the subclock operation mode is set when the ck3 bit of the pcc register is set to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. check that the system clock has been changed by using the cl s bit of the pcc register. when the mck bit of the pcc register is set to 1, t he operation of the main clock oscillator is stopped. consequently, the entire system operates on only the subclock. in the subclock operation mode, the subclock is used as the internal system clock, so that the current consumption can be reduced from that in the normal operation mode. in addition, a current consumption close to that in the software stop mode can be realized by stopping the operation of the main clock oscillator. table 19-10 shows the operation status in the subclock operation mode. caution changing the set value of the ck2 to ck0 bits of the pcc register is prohibited when the ck3 bit is manipulated (0 1 or 1 0) (set the ck3 bit by using a bit ma nipulation instruction). for details of the pcc register, refer to 6.3 (1) processor clock control register (pcc). 19.6.2 releasing subc lock operation mode the subclock operation mode is released by clearing the ck3 bit to 0 or by a reset signal (reset by reset pin input, wdt2res signal, low voltage detector (lvi), or clock monitor (clm)). when the main clock is stopped (mck bit = 1), clear the mck bit to 0, secure the oscillation stabilization time of the main clock by software, and then clear the ck3 bit to 0. when the subclock operation mode is released, the normal operation mode is restored. cautions 1. changing the set value of the ck2 to ck0 bits of the pcc register is prohibited when the ck3 bit is manipulated (0 1 or 1 0) (set the ck3 bit by using a bit manipulation instruction). for details of the pcc register, refer to 6.3 (1) processor clock control register (pcc). 2. when digital noise eliminat ion is selected, and the sampli ng clock can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, subclock operation mode can not released chapter 19 standby function user?s manual u17830ee1v0um00 846 table 19-10. operation status in subclock operation mode operation status setting of subclock operation mode item with main clock without main clock subclock oscillator oscillation enabled ring-osc generator oscillation enabled pll operable stops operation note cpu operable dma operable interrupt controller operable timer p (tmp0 to tmp3) operable stops operation timer q (tmq0 to tmq3) operable stops operation timer m (tmm0) operable operable when f r /8 or f xt is selected as the count clock watch timer operable operable when f xt is selected as the count clock watchdog timer 2 operable operable when f r is selected as the count clock csib1 to csib2 operable operable when sckbn input clock is selected as the operating clock (n = 0 to 2) serial interface uart0-uart3 operable stop operation (however, operable when ascka0 input clock is selected as the operating clock) can controller operable stops operation a/d converter operable stops operation key interrupt function (kr) operable external bus interface refer to chapter 5 bus control function . port function settable internal data settable note when stopping the main clock, be sure to stop the pll (by clearing the pllon bit of the pllctl register to 0). caution: when the cpu is operati ng on the subclock and main cloc k oscillation is stopped, accessing a register in which a wait occurs is disabled. if a wa it is generated, it can be released only by reset (see 3.4.10 (2)). chapter 19 standby function user?s manual u17830ee1v0um00 847 19.7 sub-idle mode 19.7.1 setting and operation status the sub-idle mode is set when the psm1 and psm0 bits of the psmr register are set to ?10? and the stp bit of the psc register is set to 1 in the subclock operation mode. in the sub-idle mode, the clock oscillator continues oper ating, but clock supply to the cpu, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution is st opped, and the contents of the internal ram before the sub-idle mode was set are retained. not only the cpu but also the other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can o perate on the subclock or external clock continue operating. the sub-idle mode can reduce current consumption more than the subc lock operation mode because the operations of the cpu, flash memory, and other on-chip peripheral functions are stopped. if the sub-idle mode is set after the main clock is stoppe d, a current consumption clos e to that in the software stop mode can be realized. table 19-12 shows the operation status in the sub-idle mode. caution insert five or more nop inst ructions after the store instructi on that manipulates the psc register to set the sub-idle mode. 19.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked inter nal interrupt request of a peripheral function that can operate in the sub-idle mode, or reset signal (reset by r eset pin input, wdt2res signal, low voltage detector (lvi), or clock monitor (clm)). the pll returns to t he operation status before t he sub-idle mode was set. when the sub-idle mode is released by an interrupt reques t signal, the subclock operation mode is restored. when the sub-idle mode is released by reset, the normal operation mode is restored. cautions: 1. interrupt request signals that are set (disabled) by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the sub-idle mode. 2. when digital noise eliminat ion is selected by setting of nf c register, and the sampling clock can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, sub idle mode can not released using intp3 pin. for de tail, refer to 17.3.10 (13) noise elimination control register. (1) non-maskable interrupt request signal an d unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable in terrupt signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the sub-idle mode is set in an interrupt routine, however, the operation is performed as follows. (a) if an interrupt request signal having a priority lowe r than that of the interrupt request currently being serviced is generated, the sub-idle mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held. (b) if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt request currently being se rviced is generated, the sub-idle mode is released, and this interrupt request signal is acknowledged. chapter 19 standby function user?s manual u17830ee1v0um00 848 table 19-11. operation after sub-idle mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed. the next instruction is executed. (2) releasing by reset input the operation is the same as the normal reset operation. table 19-12. operation status in sub-idle mode operation status setting of sub-idle mode item with main clock without main clock subclock oscillator oscillation enabled ring-osc generator oscillation enabled pll operation enabled stops operation note cpu stops operation dma stops operation interrupt controller stops operation (however, can be used to release standby mode) timer p (tmp0 to tmp3) stops operation timer q (tmq0 to tmq3) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer operation enabled operable when f xt is selected as the count clock watchdog timer 2 operable when f r is selected as the count clock csib0 to csib2 operable when sckbn input clock is selected as the operating clock (n = 0 to 2) serial interface uart0-uart3 stop operation (however, operable when ascka0 input clock is selected as the operating clock) can controller stops operation a/d converter stops operation key interrupt function (kr) operable external bus interface refer to chapter 5 bus control function (same operation status as in idle1 and idle2 modes). port function holds status before sub-idle mode is set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before sub-idle mode was set. note when stopping the main clock, be sure to stop the pll (b y clearing the pllon bit of the pllctl register to 0). chapter 19 standby function user?s manual u17830ee1v0um00 849 19.8 control registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register specifies the standby mode. this register is a special r egister and can be written only in a comb ination of specific sequences (refer to 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff1feh 7 6 5 4 3 2 1 0 psc 0 nmi1m nmi0m intm 0 0 stp 0 nmi1m standby mode release control by occurrence of intwdt2 signal 0 enable releasing standby mode by intwdt2 signal. 1 disable releasing standby mode by intwdt2 signal. nmi0m standby mode release control by nmi pin input 0 enable releasing standby mode by nmi pin input. 1 disable releasing standby mode by nmi pin input. intm standby mode release control by maskable interrupt request signal 0 enable releasing standby mode by maskable interrupt request signal. 1 disable releasing standby mode by maskable interrupt request signal. stp setting of standby mode note 0 normal mode 1 standby mode note standby modes that can be set by the stp bit: idle1 mode, idle2 mode, software stop mode, and sub-idle mode caution before setting the idle1, idle2, softw are stop mode, or sub-idle mode, set the psm1 and psm0 bits of the psmr register. chapter 19 standby function user?s manual u17830ee1v0um00 850 (2) power save mode register (psmr) this is an 8-bit register that contro ls the operating status of the powe r save mode and the operation of the clock. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff820h 7 6 5 4 3 2 1 0 psmr 0 0 0 0 0 0 psm1 psm0 psm1 psm0 specification of operation in software standby mode 0 0 idle1 mode, sub-idle mode 0 1 software stop mode, sub-idle mode 1 0 idle2 mode, sub-idle mode 1 1 software stop mode cautions 1. be sure to clear bits 2 to 7 to 0. 2. the psm0 and psm1 bits are va lid only when the stp bit = 1. remark idle1: mode used to stop all the operations except the oscillator and some circuits (flash memory and pll). when idle1 mode is released, the normal operation mode is restored without the lapse of t he oscillation stabilization time, in the same manner as in the halt mode. idle2: in this mode, all operations except the oscillator operation are stopped. after the idle2 mode is released, the normal operat ion mode is restored following the lapse of the setup time specified by the os ts register (flash memory and pll). sub-idle: mode used to stop all the operations ex cept the oscillator. after the sub-idle mode is released, the setup time (for flash memory and pll) specified by the osts register elapses, and then the norma l operation mode is restored. stop: mode used to stop all the operations ex cept the subclock oscillator. after the software stop mode is released, the oscill ation stabilization time specified by the osts register elapses, and then the normal operation mode is restored. chapter 19 standby function user?s manual u17830ee1v0um00 851 (3) oscillation stabilization time selection function the wait time until the oscillation st abilizes after the software stop mode is released is controlled by the osts register. the osts register can be read or written 8-bit units. reset input sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x setting prohibited note the oscillation stabilization time and setup time are required when the software stop mode and idle mode are released, respectively. cautions 1. the wait time following release of th e software stop mode does no t include the time until the clock oscillation starts (?a? in the figure below) following release of the software stop mode, regardless of whether the software stop mode is released by reset input or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to 0. 3. the oscillation stabilization time following reset release is 2 16 /f x (because the initial value of the osts register = 06h). remark f x = oscillation frequency user?s manual u17830ee1v0um00 852 chapter 20 reset function 20.1 overview remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. the reset function is outlined below. (1) five types of reset sources ? reset function by reset pin input ? reset function by overflow of watchdog timer 2 (wdt2res) ? system reset by low voltage detector (lvi) (see chapter 23 low voltage detector ) ? system reset by clock monitor (clm) (see chapter 21 clock monitor ) ? system reset by power-on clear circuit (poc) (see chapter 22 power-on clear circuit ) it can be check reset source by reset source fl ag register (resf) after reset has been released. (2) emergency operation mode if the wdt2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock oscillation anomaly is judged and the cpu starts operating on the internal oscillation clock. caution: when the cpu is being opera ted via the internal oscillator, access to the register in which a wait state is generated is prohibited. for the register in which a wait state is generated, refer to 3.4.10 (2) accessing specific on-chip peripheral i/o registers. chapter 20 reset function user?s manual u17830ee1v0um00 853 20.2 register to check reset source (1) reset source flag register (resf) the resf register is a special regist er that can be written only by a comb ination of specific sequences (see 3.4.9 special registers ). the resf register indicates the source from which a reset signal is generated. this register is read or written in 8-bit or 1-bit units. reset pin input clears this register to 00h. the default value differs if t he source of reset is other than the reset pin signal. after reset: 00h note r/w address: fffff888h 7 6 5 4 3 2 1 0 resf 0 0 0 wdt2rf 0 0 clmrf lvirf wdt2rf generation of reset signal from wdt2 0 not generated 1 generated clmrf generation of reset signal from clock monitor 0 not generated 1 generated lvirf generation of reset signal from low voltage detector 0 not generated 1 generated note this register holds 00h after a reset by the reset pin, or sets its reset flags (wdt2rf, clmrf, and lvirf bits) after a reset by the wdt2res signal, low voltage detector (lvi), or clock monitor (clm) (the other sources are held). caution only 0 can be written to each bit. if writing 0 and flag setting (occurrence of reset) conflict, flag setting takes precedence. chapter 20 reset function user?s manual u17830ee1v0um00 854 20.3 operation 20.3.1 reset operation by reset pin when a low level is input to the reset pin, t he system is reset, and each hardware is initialized. when the level of the reset pin input is changed fr om low to high, the reset status is released. if the reset status is released by input to the reset pin, the oscillation stabilization time (reset value of the osts register: 2 16 /f x ) elapses, and then the cpu starts program execution. table 20-1. hardware status when signal is input to reset pin item during reset after reset main clock oscillator (f x ) stops oscillation starts oscillation subclock oscillator (f xt ): x'tal rc x'tal ->continues oscillation rc ->stops oscillation x'tal ->continues oscillation rc ->starts oscillation ring-osc generator stops oscillation starts oscillation peripheral clock (f x to f x /1,024) stops operation starts operation after oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) stops operation starts operation after oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after oscillation stabilization time watchdog timer 2 stops operation starts operation internal ram undefined after a reset while power is on or if a data access to ram (by the cpu) and a reset input conflict (data co rrupted). otherwise, retains value immediately before reset input note . i/o lines (port/alternate-function pins) high impedance on-chip peripheral i/o registers initialized to spec ified status. ocdm register is reset (01h). other on-chip peripheral functions stop operation start operation after oscillation stabilization time note because the v850es/fx2 supports a boot swap function, the firmware uses part of the internal ram after the internal system reset is released. for details see 20.4 ram usage after reset release. caution the on-chip debug mode (flash memory produc ts only) may be set depending on the pin status after reset has been released. for deta ils, refer to chapter 4 port functions. chapter 20 reset function user?s manual u17830ee1v0um00 855 figure 20-1. timing of reset operation by reset pin input counting of oscillation stabilization time initialized to f xx /8 operation timer for oscillation stabilization overflows internal system reset signal analog delay (eliminated as noise) reset f x f clk analog delay analog delay analog delay figure 20-2. timing of power-on reset operation counting of oscillation stabilization time must be 1 s or more. initialized to f xx /8 operation timer for oscillation stabilization overflows reset f x v dd f clk analog delay internal system reset signal chapter 20 reset function user?s manual u17830ee1v0um00 856 20.3.2 reset operation by wdt2res signal if the mode in which a reset operation is performed when watchdog timer 2 overflows is set, if watchdog timer 2 overflows (generating the wdt2 res signal), the system is reset and each hardware is initialized to the specified status. after watchdog timer 2 overflows, the reset status lasts for a specific time (analog delay) . then the reset status is automatically released. after the reset status is released, the oscillation stabiliz ation time of the main clock oscillator elapses (default value of osts register: 2 16 /f x ), and the cpu starts program execution. the main clock oscillator is stopped during the reset period. table 20-2. hardware status a fter generation of wdt2res signal item during reset after reset main clock oscillator (f x ) stops oscillation starts oscillation subclock oscillator (f xt ): x'tal rc x'tal ->continues oscillation rc ->stops oscillation x'tal ->continues oscillation rc ->starts oscillation ring-osc generator stops oscillation starts oscillation peripheral clock (f x to f x /1,024) stops operation starts operation after oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) stops operation starts operation after oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after oscillation stabilization time watchdog timer 2 stops operation starts operation internal ram undefined after a reset while power is on or if a data access to ram (by the cpu) and a reset input conflict (data co rrupted). otherwise, retains value immediately before reset input note . i/o lines (port/alternate-function pins) high impedance on-chip peripheral i/o registers initialized to specified value. ocdm register retains its value. other on-chip peripheral functions stop operation start operation after oscillation stabilization time note because the v850es/fx2 supports a boot swap function, the firmware uses part of the internal ram after the internal system reset is released. for details see 20.4 ram usage after reset release. chapter 20 reset function user?s manual u17830ee1v0um00 857 figure 20-3. timing of reset operat ion by generation of wdt2res signal counting of oscillation stabilization time initialized to f xx /8 operation timer for oscillation stabilization overflows wdt2res f x f clk analog delay analog delay internal system reset signal 20.3.3 reset operation by power-on clear (only on -chip products of the power-on clear function) if the supply voltage falls below t he voltage detected by comparison su pply voltage and detection voltage when power-on clear operation is enabled (incl. when power i nput), a system reset is executed, and the hardware is initialized to the initial status. the reset status lasts from when a supply voltage drop has been detected until the su pply voltage rises above the detection voltage. then, reset status is released automatically. after reset releas e, the oscillation stabilization time of main clock oscillator (default value of osts register: 2^ 16/fx) is ensured, and cpu is st arted program execution. for details, refer to chapter 22 power-on clear . 20.3.4 reset operation by low-voltage detector if the supply voltage falls below the vo ltage detected by the low-voltage dete ctor when lvi operation is enabled, a system reset is executed (when the lvim.lvimd bit is set to 1), and the hardware is initia lized to the initial status. the reset status lasts from when a supply voltage drop has been detected until the su pply voltage rises above the lvi detection voltage. after reset release, the oscillation stabilization time of main clock oscillator (default valu e of osts register: 2^16/fx) is ensured, and cpu is started program execution. for details, refer to chapter 23 low-voltage detector. 20.3.5 reset operation by clock monitor when operation of the clock monitor is enabled, the main cl ock is monitored by using the internal oscillator. then, when oscillation stop of the main clock is detected, system reset is executed a nd each hardware is initialized to the initial status. for details, refer to chapter 21 clock monitor . chapter 20 reset function user?s manual u17830ee1v0um00 858 20.4 ram usage after reset release because the v850es/fx2 supports a boot sw ap function, the firmware uses part of the internal ram after the internal system reset is released. therefore the contents of some ar eas of the ram are not retained even when power-on reset is executed. the used ram areas after reset are for all products the first 150 bytes at the lower side and the last 100 bytes at the upper side. the detailed affected addresses are: part number (ram) 150 byte lower side 100 byte upper side d70f3231 (6k) 3ffd800 3ffd895 3ffef9b 3ffefff d70f3232 (12k) 3ffc000 3ffc095 3ffef9b 3ffefff d70f3233 (12k) 3ffc000 3ffc095 3ffef9b 3ffefff d70f3234 (6k) 3ffd800 3ffd895 3ffef9b 3ffefff d70f3235 (12k) 3ffc000 3ffc095 3ffef9b 3ffefff d70f3236 (16k) 3ffb000 3ffb095 3ffef9b 3ffefff d70f3237 (16k) 3ffb000 3ffb095 3ffef9b 3ffefff d70f3238 (20k) 3ffa000 3ffa095 3ffef9b 3ffefff d70f3239 (20k) 3ffa000 3ffa095 3ffef9b 3ffefff user?s manual u17830ee1v0um00 859 chapter 21 clock monitor 21.1 function of clock monitor the clock monitor samples the main clock by using the on-chip ring-osc and generates a reset request signal when oscillation of the main clock is stopped. once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. the clock monitor automatically stops under the following conditions. ? while oscillation stabilization time is being counted after software stop mode is released ? when the main clock is stopped (from when the pcc.mck bit = 1 during subclock operation, until the pcc.cls bit = 0 during main clock operation) ? when the sampling clock is stopped (ring-osc) ? when the cpu operates with ring-osc 21.2 configuration of clock monitor the clock monitor consists of the following hardware. table 21-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 21-1. clm block diagram main clock ring-osc clock internal reset signal enable/disable clme clock monitor mode register (clm) chapter 21 clock monitor user?s manual u17830ee1v0um00 860 21.3 register controlling clock monitor the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) this register is a special register and can be written only in a combination of specific sequences (refer to 3.4.9 special registers). this register is used to set the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff870h 7 6 5 4 3 2 1 0 clm 0 0 0 0 0 0 0 clme clme clock monitor operation enable or disable 0 disable clock monitor operation. 1 enable clock monitor operation. cautions 1. once the clme bit h as been set to 1, it cannot be cleared to 0 by any means other than reset. 2. if reset is occurred for clock monitor, clme bit is clear (0), and resf, clmrf bit is set (1). chapter 21 clock monitor user?s manual u17830ee1v0um00 861 21.4 operation of clock monitor this section explains the functions of the clock m onitor. the start and stop conditions are as follows. chapter 21 clock monitor user?s manual u17830ee1v0um00 862 (1) operation when main clock osc illation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bit = 1, an internal reset signal is generated as shown in figure 21-2. figure 21-2. when oscillation of main clock is stopped four ring-osc clocks main clock ring-osc clock internal reset signal chapter 21 clock monitor user?s manual u17830ee1v0um00 863 (2) operation in software stop mode or after software stop mode is released if the software stop mode is set with the clme bit = 1, the monitor operation is stopped in the software stop mode and while the oscillation stabilizat ion time is being counted. after the oscillation stabilization time, the monitor operation is aut omatically started. figure 21-3. operation in software stop mode or after software stop mode is released clock monitor status during monitor monitor stops during monitor clme ring-osc clock main clock cpu operation normal operation software stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) (3) operation when main clock is stopped (arbitrary) during subclock operation (cls bit of the pcc register = 1) or when the main clock is stopped by setting the mck bit of the pcc register to 1, the monitor operation is stopped until t he main clock operation is started (cls bit of pcc register = 0). the monitor operation is automatically started when the main clock operation is started. figure 21-4. operation when main clock is stopped (arbitrary) clock monitor status during monitor monitor stops monitor stops during monitor clme ring-osc clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time count by software pccmck bit = 1 (4) operation while cpu is operating on ring-osc clock (cclsf bit of ccls register = 1) the monitor operation is not stopped when the cclsf bi t is 1, even if the clme bit is set to 1. user?s manual u17830ee1v0um00 864 chapter 22 power-on clear circuit 22.1 functions of power-on clear circuit the power-on clear (poc) circuit has the following functions. ? generates an internal reset signal upon power application. ? compares the supply voltage (v dd ) and detected voltage (v poc0 ), and generates an inte rnal reset signal when v dd < v poc0 . the following choice can be made depending on the product. ? poc is disabled. ? poc can be used (detected voltage: v poc0 = 3.7 v (typ.)) caution if the internal reset signal is generated by th e poc circuit, the reset sour ce flag register (resf) is cleared (to 00h). remarks 1. this product has several hardware units that generate an internal reset signal. when reset is effected by watchdog timer 2 (wdt2res), the low-vo ltage detector (lvi), or the clock monitor (clm), a flag that identifies the rese t source is provided in the reset source flag register (resf). if an internal reset signal is generated by wdt2res, lvi, or the clock monitor, resf is not cleared (00h) but the corresponding flag is set (1 ). for details of resf, refer to chapter 20 reset function . 2. the time when it consumes to the program start from the power supply input is the time from power supply input to reset released + 16 ms in ca se of the frequency that is connected outside is 5 mhz. but this time is influenced by the outside factor (the condition of pow er supply that supplies to microcomputer). chapter 22 power-on clear circuit preliminary user?s manual u17830ee1v0um00 865 22.2 configuration of power-on clear circuit figure 22-1 shows the block diagram of the power-on clear circuit. figure 22-1. block diagram of power-on clear circuit ? + detected voltage source (v poc0 ) internal reset signal v dd 22.3 operation of power-on clear circuit the power-on clear circuit compares the supply voltage (v dd ) and detected voltage (v poc0 ), and generates an internal reset signal when v dd < v poc0 . figure 22-2. timing of internal reset si gnal generation by powe r-on clear circuit time delay supply voltage (v dd ) poc detected voltage (v poc0 ) internal reset signal reset period (excluding oscillation stabilization time) reset period (excluding oscillation stabilization time) reset period (excluding oscillation stabilization time) user?s manual u17830ee1v0um00 866 chapter 23 low-voltage detector 23.1 functions of low-voltage detector the low-voltage detector (lvi) has the following functions. ? compares the supply voltage (v dd ) and detected voltage (v lv i i ) and generates an internal interrupt signal or internal reset signal when v dd < v lv i . ? the level of the supply voltage to be detecte d can be changed by software (in two steps). ? interrupt or reset signal c an be selected by software. ? can operate in stop mode too. ? operation can be stopped by software. if the low-voltage detector is used to generate a reset signal , bit 0 (lvirf) of the reset source flag register (resf) is set to 1 when the reset signal is g enerated. for details of resf, refer to chapter 20 reset function . 23.2 configuration of low-voltage detector figure 23-1 shows the block diagram of the low-voltage detector. figure 23-1. block diagram of low-voltage detector lvis0 lvion detected voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low voltage detection level selection register (lvis) low voltage detection register (lvim) lvimd lvif internal reset signal selector low voltage detection level selector ? + chapter 23 low-voltage detector user?s manual u17830ee1v0um00 867 23.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low voltage detection register (lvim) ? low voltage detection level selection register (lvis) (1) low voltage detection register (lvim) this register is a special register and can be written only in a combination of specific sequences (refer to 3.4.9 special registers). the lvim register is used to enable or disable low volt age detection, and to set the operation mode of the low- voltage detector. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff890h 7 6 5 4 3 2 1 0 lvim lvion 0 0 0 0 0 lvimd lvif lvion low voltage detection operation enable or disable 0 disable operation. 1 enable operation. lvimd selection of operation mode of low voltage detection 0 generate interrupt request signal intlvi when supply voltage < detected voltage. 1 generate internal reset signal lvires when supply voltage < detected voltage. lvif low voltage detection flag 0 when supply voltage > detected voltage, or when operation is disabled 1 supply voltage of connected power supply < detected voltage cautions 1. after setting the lvion bit to 1, wa it for 0.2 ms (max.) before checking the voltage using the lvif bit. 2. the value of the lvif flag is output as the output signal intlvi when the lvion bit = 1 and lvimd bit = 0. 3. the lvif bit is read-only. 4. be sure to clear bits 2 to 6 to 0. chapter 23 low-voltage detector user?s manual u17830ee1v0um00 868 (2) low voltage detection level selection register (lvis) the lvis register is used to select t he level of low voltage to be detected. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff891h 7 6 5 4 3 2 1 0 lvis 0 0 0 0 0 0 0 lvis0 lvis0 detection level 0 4.4 v (typ.) 1 4.2 v (typ.) cautions: 1. this register cannot be written until a reset request due to something other than low-voltage detection is generated after the lvim.lvion and lvim.lvimd bits are set to 1. 2. be sure to clear bits 7 to 1 to 0. (3) internal ram data status register (rams) the rams register is a flag register that indi cates whether the internal ram is valid or not. this register can be read or written in 8-bit or 1-bit units note 1 . reset input note 2 sets this register to 01h. notes 1. this register can be written only in a specific sequence. 2. setting conditions: detection of voltage lower than specified level set by instruction generation of reset signal by wdt2 generation of reset signal while ram is being accessed generation of reset signal by clock monitor clearing condition: writing of 0 in specific sequence after reset: 01h r/w address: fffff892h 7 6 5 4 3 2 1 0 rams 0 0 0 0 0 0 0 ramf ramf internal ram data valid/invalid 0 valid 1 invalid chapter 23 low-voltage detector user?s manual u17830ee1v0um00 869 (4) peripheral emulation register 1 (pemu1) when an in-circuit emulator is used, the operation of t he ram retention flag (ramf bit: bit 0 of rams register) can be pseudo-controlled and emulated by manipulating this register on the debugger. this register is valid only in the emulation mode. it is invalid in the normal mode. after reset: 00h r/w address: fffff9feh 7 6 5 4 3 2 1 0 pemu1 0 0 0 0 0 evaramin 0 0 evaramin pseudo specification of ram retention voltage detection signal 0 do not detect voltage lower than ram retention voltage. 1 detect voltage lower than ram retention voltage (set ramf flag). caution this bit is not automatically cleared. [usage] when an in-circuit emulator is used, pseudo emulation of ramf is realiz ed by rewriting this register on the debugger. <1> cpu break (cpu operation stops.) <2> set the evaramin bit to 1 by using a register write command. by setting the evaramin bit to 1, the ramf bit is se t to 1 on hardware (the internal ram data is invalid). <3> clear the evaramin bit to 0 by using a register write command again. unless this operation is performed (clearing the evaram in bit to 0), the ramf bit cannot be cleared to 0 by a cpu operation instruction. <4> run the cpu and resume emulation. chapter 23 low-voltage detector user?s manual u17830ee1v0um00 870 23.4 operation of low-voltage detector depending on the setting of the lvimd bit, an interrupt sign al (intlvi) or an internal reset signal is generated. how to specify each operation is described below, together with timing charts. 23.4.1 to use for inte rnal reset signal chapter 23 low-voltage detector user?s manual u17830ee1v0um00 871 23.4.2 to use for interrupt chapter 23 low-voltage detector user?s manual u17830ee1v0um00 872 23.5 ram retention voltage detection operation the supply voltage and detected voltage are compared. w hen the supply voltage drops below the detected voltage (including on power application), the ramf bit is set. when the poc function is not used and when the ram ret ention voltage detection function is used, be sure to input an external reset signal if the detect ed voltage falls below the operating voltage. figure 23-4. operation timing of ram retention voltage detection function supply voltage (v dd ) poc detected voltage ram retention detected voltage poc detected voltage set condition detection signal ram retention voltage detection signal ram retention flag (ramf bit) delay clear delay time delay set set cleared by instruction cleared by instruction user?s manual u17830ee1v0um00 873 chapter 24 regulator 24.1 overview this product has an on-chip regulator to lower the power consumption and noise. this regulator supplies a voltage lower than the supply voltage v dd to the oscillator block and internal logic circuits (except the a/d converter and i/o buffers). the output voltage of the regulator is set to 2.5 v (typ.). figure 24-1. regulator ev dd i/o buffer (normal port) 3.5 to 5.5 v bv dd i/o buffer (external access port) 3.5 to 5.5 v regulator a/d converter 4.0 to 5.5 v bv dd av ref0 v dd ev dd regc flash memory main and sub oscillators internal digital circuit 2.5 v bidirectional level shifter note note: bv dd not available for v850es/fe2 and v850es/ff2 24.2 operation the regulator of this product operates in all operation mo des (normal operation, halt, idle1, idle2, software stop, and sub-idle modes, and during reset). to stabilize the output voltage of the r egulator, connect a capacitor (4.7 f (re commended value)) to the regc pin. connect the regc pin as illustrated below. chapter 24 regulator preliminary user?s manual u17830ee1v0um00 874 figure 24-2. connection of regc pin (regc = capacitance) reg input voltage 3.5 to 5.5 v supply voltage to oscillators/internal logic 2.5 v (typ.) v dd regc 4.7 f (recommended value) v ss v ss user?s manual u17830ee1v0um00 875 chapter 25 flash memory the following products are flash memory versions of the v850es/fx2 remark: for the whole chapter it shall be agreed t hat v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2. caution there are differences in the amount of noise tolerance a nd noise radiation between flash memory versions and mask rom versions. when considering changing from a flash memory version to a mask rom version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (cs) (not engineering samples (es)) of the mask rom versions. ? pd70f3231, 70f3232, 70f3234 on-chip 128 kb flash memory ? pd70f3233, 70f3235, 70f3237 on-chip 256 kb flash memory ? pd70f3236 on-chip 384 kb flash memory ? pd70f3238 on-chip 376 kb flash memory ? pd70f3239 on-chip 512 kb flash memory when fetching an instruction, 4 bytes of the flash memory c an be accessed in 1 clock in the same manner as the mask rom versions. the flash memory can be written mounted on the target board (on-board write) , by connecting a dedicated flash programmer to the target system. flash memory is commonly used in the following development environments and applications. ? for altering software after solder-mounting the v850es/fx2 on the target system ? for differentiating software in small-scale production of various models. ? for data adjustment when starting mass production 25.1 features ? 4-byte/1-clock access (when instruction is fetched) ? capacity: 512/376(384)/256/128 kb ? write voltage: erase/write with a single power supply ? rewriting method ? rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) ? flash memory write prohibit f unction supported (security function) ? safe rewriting of entire flash memory area by self programming using boot swap function ? interrupts can be acknowledged during self programming. chapter 25 flash memory user?s manual u17830ee1v0um00 876 25.1.1 erasure unit the units in which the 128, 256, 384, 376 or 512 kb flash memory can be erased are as follows. (1) all-area erasure the areas of flash memory xx 000000h to xx01ffffh, xx000000h to xx03ffffh, xx000000h to xx05ffffh, xx000000h to xx05dfffh and xx 000000h to xx07ffffh can be er ased at the same time. (2) block erasure the flash memory can be erased in block units block / flash 128k flash 256k flash 384k fl ash 376k flash 512k flash block 15 4 kb block 14 4 kb block 13 4 kb block 12 4 kb block 11 32 kb 60 kb block 10 32 kb 60 kb block 9 32 kb 60 kb 60 kb block 8 32 kb 60 kb 60 kb block 7 8 kb 8 kb 8 kb 8 kb block 6 8 kb 8 kb 8 kb 8 kb block 5 56 kb 56 kb 56 kb 56 kb block 4 56 kb 56 kb 56 kb 56 kb block 3 8 kb 8 kb 8 kb 8 kb 8 kb block 2 56 kb 56 kb 56 kb 56 kb 56 kb block 1 8 kb 8 kb 8 kb 8 kb 8 kb block 0 56 kb 56 kb 56 kb 56 kb 56 kb chapter 25 flash memory user?s manual u17830ee1v0um00 877 25.1.2 functional outline the internal flash memory of the v850es/fx2 can be rewrit ten by using the rewrite function of the dedicated flash programmer, regardless of whether the v850es/fx2 has al ready been mounted on the target system or not (off- board/on-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/sh ipment of the target syst em. a boot swap function t hat rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various co nditions, such as while communicating with an external device. table 25-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 25 flash memory user?s manual u17830ee1v0um00 878 table 25-2. basic functions support ( : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. chip erasure the contents of the entire memory area are erased all at once. write writing to specified addresses, and a verify check to see if write level is secured are performed. verify/checksum data read from the flash memory is compared with data transferred from the flash programmer. (can be read by user program) blank check the erasure status of the entire memory is checked. security setting use of the block erase command, chip erase command, and program command can be prohibited. (only values set by on- board/off-board programming can be retained) the following table lists the security functions. the bl ock erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 25-3. security functions rewriting operation when prohibited ( : executable, : not executable) function function outline on-board/off-board programming self programming block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. block erase command: chip erase command: program command: chip erase command prohibit execution of block erase and chip erase commands on all the blocks are prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command: chip erase command: program command: program command prohibit write and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. block erase command: chip erase command: program command: can always be rewritten regardless of setting of prohibition chapter 25 flash memory user?s manual u17830ee1v0um00 879 25.2 writing with flash programmer a dedicated flash programmer can be used for on-bo ard or off-board writing of the flash memory. (1) on-board programming the contents of the flash memory c an be rewritten with the v850es/fx2 m ounted on the target system. mount a connector that connects the dedicated flash programmer on the target system. (2) off-board programming the flash memory of the v850es/fx2 can be written before the device is mounted on the target system, by using a dedicated program adapter (fa series). remark the fa series is a product of na ito densei machida mfg. co., ltd. 25.3 programming environment the environment necessary to write a program to t he flash memory of the v850es/fx2 is shown below. figure 25-1. environment to wr ite program to flash memory host machine rs-232c dedicated flash programmer v850es/fx2 flmd1 note v dd v ss reset uarta0/csib0/csib3 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x xx x x xx xx x xx x x xxxx yy yy statve flmd0 usb note connect the flmd1 pin to the flash programmer or conn ect to a gnd via a pull-down resistor on the board. a host machine is required for controlling the dedicated flash programmer. uarta0 or csib0 is used as the interface between the dedicated flash programmer and the v850es/fx2 to manipulate the flash programmer by writing or erasing. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. remark the fa series is a product of naito densei machida mfg. co., ltd. chapter 25 flash memory user?s manual u17830ee1v0um00 880 25.4 communication mode serial communication is performed between the dedica ted flash programmer and the v850es/fx2 by using uarta0 or csib0 of the v850es/fx2. (1) uarta0 transfer rate: 9,600 - 153,600 bps figure 25-2. communication with dedicated flash programmer (uarta0) dedicated flash programmer v850es/fx2 v dd v ss reset txda0 rxda0 flmd1 flmd1 note v dd gnd reset rxd txd pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x yy y x xx xx x x x x xx xx x x xxx x y yy y statve flmd0 flmd0 note connect the flmd1 pin to the flash programmer or conn ect to gnd via a pull-down resistor on the board. cautions 1. process the pins no t shown in accordance with processing of unused pins (see 2.4 pin i/o circuit types, i/o buffer power supplies and handlin g of unused pins). to connect a resistor, a resistor of 1 k to 10 k ? is recommended. 2. please do not input high level in drst pin. (2) csib0 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 25-3. communication with de dicated flash programmer (csib0) dedicated flash programmer v850es/fx2 flmd1 note v dd v ss reset sob0, sob3 sib0, sib3 sckb0, sckb3 flmd1 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x xx x x xx xx x xx x x x x x y y y y s tat v e flmd0 flmd0 note connect the flmd1 pin to the flash programmer or conn ect to gnd via a pull-down resistor on the board. chapter 25 flash memory user?s manual u17830ee1v0um00 881 cautions 1. process the pins no t shown in accordance with processing of unused pins (see 2.4 pin i/o circuit types, i/o buffer power supplies and handlin g of unused pins). to connect a resistor, a resistor of 1 k to 10 k ? is recommended. 2 please do not input high level in drst pin. (3) csib0 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 25-4. communication with dedi cated flash programmer (csib0+hs) dedicated flash programmer v850es/fx2 v dd v ss reset sob0, sob3 sib0, sib3 sckb0, sckb3 pcm0 v dd flmd1 flmd1 note gnd reset si so sck hs pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x xx x x x x xx xx x x x x x x y y y y statve flmd0 flmd0 note connect the flmd1 pin to the flash programmer or conn ect to gnd via a pull-down resistor on the board. cautions 1. process the pins no t shown in accordance with processing of unused pins (see 2.4 pin i/o circuit types, i/o buffer power supplies and handlin g of unused pins). to connect a resistor, a resistor of 1 k to 10 k ? is recommended. 2. please do not input high level in drst pin. chapter 25 flash memory user?s manual u17830ee1v0um00 882 the dedicated flash programmer outputs a transfer clock and the v850es/fx2 operates as a slave. if the pg-fp4 is used as the flash pr ogrammer, it generates the following signa ls for the v850es/fx2. for details, refer to the pg-fp4 user?s manual (u15260e) . table 25-4. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/fx2 note 1 processing for connection signal name i/o pin function pin name uarta0 csib0 csib0 + hs, flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 2 note 2 note 2 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/fx2 x1, x2 note 3 note 3 note 3 reset output reset signal reset si/rxd input receive signal sob0, txda0 so/txd output transmit signal sib0, rxda0 sck output transfer clock sckb0 hs input handshake signal for csib0 + hs communication pcm0 notes 1. v850es/fx2 stands for v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2, 2. wire these pins as shown in figure 25-6, or connect then to gnd via pull-down resistor on board. 3. clock cannot be supplied via the clk pin of the flash programmer. create an oscillator on board and supply the clock. remark : must be connected. : does not have to be connected. chapter 25 flash memory user?s manual u17830ee1v0um00 883 figure 25-5. example of wi ring of v850es/fj2 flash writ ing adapter (fa-144gj-uen) (in csib0 + hs mode) (1/2) v850es/fj2 vdd gnd gnd vdd gnd vdd vdd gnd connect to vdd connect to gnd 25 30 20 15 75 80 85 90 95 100 105 35 40 45 50 55 60 65 70 110 115 120 125 130 135 140 1 5 10 rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs x1 x2 note 3 note 1 note 2 4.7 f chapter 25 flash memory user?s manual u17830ee1v0um00 884 figure 25-5. example of wi ring of v850es/fj2 flash writ ing adapter (fa-144gj-uen) (in csib0 + hs mode) (2/2) notes 1. wire the flmd1 pin as shown below, or connect it to gnd on board via a pull-down resistor. 2. supply a clock by creating an oscillator on the fl ash writing adapter (enclos ed by the broken lines). here is an example of the oscillator. example x1 x2 3. pins used when uarta0 is used. caution do not input a high level to the drst pin. remarks 1. process the pins not shown in accordan ce with processing of unused pins (see 2.4 pin i/o circuit types and recommended connection of unused pins ). 2. this adapter is for the 144-pin plastic lqfp package. chapter 25 flash memory user?s manual u17830ee1v0um00 885 25.5 pin connection a connector must be mounted on the tar get system to connect the dedicated flas h programmer for on-board writing. in addition, a function to switch between the normal ope ration mode and flash memory programming mode must be provided on the board. when the flash memory programming mode is set, all the pi ns not used for flash memory programming are in the same status as that immediately after re set. therefore, all the ports go into an output high-impedance state, and the pins must be processed correctly if the external device does not recognize the output high-impedance state. 25.5.1 flmd0 pin because the flmd0 pin serves as a write protection pi n in the self programming mode, a voltage of vdd level must be supplied to the flmd0 pin via port control, etc ., before writing to the flash memory. for details, see 25.7.5 (1) flmd0 pin . in the normal operation mode, 0 v is input to the flmd 0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. an example of connection of the flmd0 pin is shown below. figure 25-6. example of connection of flmd0 pin flmd0 dedicated flash programmer connection pin pull-down resistor (p flmd0 ) v850es/fj2 chapter 25 flash memory user?s manual u17830ee1v0um00 886 25.5.2 flmd1 pin if 0 v is input to the flmd0 pin, t he flmd1 pin does not function. if v dd is supplied to the flmd0 pin, 0 v must be input to the flmd1 pin to set the flash memory programmi ng mode. an example of the connection of the flmd1 pin is shown below. figure 25-7. example of connection of flmd1 pin flmd1 pull-down resistor (r flmd1 ) other device v850es/fj2 caution if a v dd signal is input to the flmd1 pi n from other device during on-board writing and immediately after reset, isolate this signal. table 25-5. relationship between flmd0 and flmd1 pins and operation mode flmd0 flmd1 operation mode 0 normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited 25.5.3 serial interface pins the pins used by each serial interface are shown in the table below. table 25-6. pins used by each serial interface serial interface pins csib0 sob0, sib0, sckb0 csib0 + hs sob0, sib0, sckb0, pcm0 uarta0 txda0, rxda0 when connecting a dedicated flash programmer to a serial in terface pin that is connected to another device on board, exercise care so that signal conflict an d malfunction of the other device do not occur. (1) conflict of signals when the dedicated flash programmer (output) is connec ted to a serial interface pin (input) connected to another device (output), a signal conflict occurs. to avoid this signal c onflict, isolate the connection with the other device, or place the other devi ce in an output high-impedance state. chapter 25 flash memory user?s manual u17830ee1v0um00 887 figure 25-8. signal conflict (input pin of serial interface) input pin signal conflict dedicated flash programmer connection pin other device output pin in the flash memory programming mode, the signal output by an other device conflicts with the signal output by the dedicated flash programmer. isolate the signal of the other device. v850es/fj2 (2) abnormal operation of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) connected to another device (input), a signal is output to the other device, causing a malfunction. to avoid this malfunction, isolate the connection with th e other device, or set so that the signal input to the other device is ignored. figure 25-9. abnormal operation of other device pin dedicated flash programmer connection pin other device input pin if the signal output by the v850es/fj2 affects another device in the flash memory programming mode, isolate the signal of the other device. pin dedicated flash programmer connection pin other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signal of the other device. v850es/fj2 v850es/fj2 chapter 25 flash memory user?s manual u17830ee1v0um00 888 25.5.4 reset pin when the reset signal of the dedicated flash programmer is connected to the reset pin connected to a reset signal generator on board, a signal conflict occurs. to avoid this signal conflict, isolate the connection with the reset signal generator. if a reset signal is input from the user system in flas h memory programming mode, the programming operation is not performed correctly. do not input a reset signal other than that from the dedicated flash programmer. figure 25-10. signal conflict (reset pin) reset dedicated flash programmer connection pin reset signal generator signal conflict output pin because the signal output by the reset signal generator conflicts with the signal output by the dedicated flash programmer in the flash programming mode, isolate the signal of the reset signal generator. v850es/fj2 25.5.5 port pins (including nmi) all the port pins, including the pin connected to the dedicated flash programmer, go into an output high-impedance state in the flash memory programming mode. if there is a pr oblem such as that the external device connected to a port prohibits the output high-imped ance state, connect the port to v dd or v ss via a resistor. 25.5.6 other signal pins connect x1, x2, xt1, xt2, and regc in the same status as that in the normal operation mode. during flash memory programming, input a low level to the dr st pin or leave it open. do not input a high level. 25.5.7 power supply supply the same power to the power supply pins (vdd, vss, evdd, evss, bvdd, bvss, avss and avref0) as in the normal operation mode. chapter 25 flash memory user?s manual u17830ee1v0um00 889 25.6 programming method 25.6.1 flash memory control the procedure to manipulate the flash memory is illustrated below. figure 25-11. flash memory manipulation procedure start select communication mode manipulation of flash memory end? yes flmd0 pulse supply no end transition to flash memory programming mode chapter 25 flash memory user?s manual u17830ee1v0um00 890 25.6.2 selecting communication mode in the v850es/fx2., the communication mode is selected by inputting pulses (up to 11 pulses) to the flmd0 pin after the flash memory programming mode is set. these flmd0 pulses are generated by the dedicated flash programmer. the relationship between the number of pulses and t he communication mode is shown in the figure below. figure 25-12. flash memory programming mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v ( note ) power supply on oscillation stabilization communication mode selection flash control command communication (such as erase and write) reset released note the number of clocks to be inserted differs depending on the communication mode. flmd0 pulse communication mode remark 8 csib0 v850es/fx2 operates as slave. msb first 11 csib0 + hs v850es/fj2 operates as slave. msb first 0 uarta0 communication rate: 9,600 bps (after reset), lsb first others - setting prohibited caution when uarta is selected, th e receive clock is calculated b ased on the reset command that is sent from the dedicated flash programme r after reception of the flmd0 pulse. chapter 25 flash memory user?s manual u17830ee1v0um00 891 25.6.3 communication commands the v850es/fx2. communicates with the dedicated flas h programmer via commands. the commands sent by the dedicated flash programmer to the v850es/fx2 are calle d commands, and the response signals sent by the v850es/fx2 to the flash programmer are called response commands. figure 25-13. communication commands dedicated flash programmer command response command pg-fp4 (flash pr o4) cxxxxxx bxxxxx axxxx x x x y y y x x x xx x x xx x x x x x x x x x x y y y y statve v850es/fx2 the following table lists the flash memory control comm ands of the v850es/fx2. all these commands are issued by the programmer, and the v850es/fx2 performs the corresponding processing. table 25-7. flash memory control commands support classification command name csib csib + hs uarta function blank check block blank check command checks erasure status of entire memory. chip erase command erases all memory contents. erase block erase command erases memory contents of specified block. write write command writes data by specifying write address and number of bytes to be written, and executes verify check. verify verify command compares input data with all memory contents. reset command escapes from each status. oscillation frequency setting command sets oscillation frequency. baud rate setting command ? ? sets baud rate when uart is used. silicon signature command reads silicon signature information. version acquisition command reads version information of device. status command ? acquires operation status. system setting and control security setting command sets security of chip erasure, block erasure, and writing. the v850es/fx2 returns a response command in response to the command issued by the flash programmer. the response commands sent by the v850es/fx2 are listed below. table 25-8. response commands response command name function ack acknowledges command/data. nak acknowledges illegal command/data. chapter 25 flash memory user?s manual u17830ee1v0um00 892 25.7 rewriting by self programming 25.7.1 overview the v850es/fx2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming library that is used to rewrit e the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program c an be upgraded and constant data can be rewritten in the field. figure 25-14. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write chapter 25 flash memory user?s manual u17830ee1v0um00 893 25.7.2 features (1) secure self programming (boot swap function) the v850es/fx2 supports a boot swap f unction that can exchange the physica l memory of blocks 0 and 1 with the physical memory of blocks 2 and 3. by writing t he start program to be rewritten to blocks 2 and 3 in advance and then swapping the physical memory, the ent ire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 and 1. figure 25-15. rewriting entire memory area (boot swap) block 15 block 5 block 4 block 3 block 2 block 1 block 0 block 15 block 5 block 4 block 3 block 2 block 1 block 0 block 15 boot swap rewriting blocks 2 and 3 block 5 block 4 block 3 block 2 block 1 block 0 (2) interrupt support instructions cannot be fetched from the flash memory during self programming. c onventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. with the v850es/fx2, a user handler can be registered to an en try ram area by using a library function, so that interrupt servicing can be performed by inte rnal ram or external memory execution. chapter 25 flash memory user?s manual u17830ee1v0um00 894 25.7.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 25-16. standard self programming flow flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swap processing note 2 flash environment end processing flash memory manipulation end of processing all blocks end? ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock yes no notes 1. if a security setting is not performed, flash in formation setting processing does not have to be executed. 2. if boot swap is not used, flash information setting processing and boot swap processing do not have to be executed. chapter 25 flash memory user?s manual u17830ee1v0um00 895 25.7.4 flash functions table 25-9. flash function list function name outline support flashenv initialization of flash control macro flashblockerase erasure of only specified one block flashwordwrite writing from specified address flashblockiverify internal verification of specified block flashblockblankcheck blank check of specified block flashflmdcheck check of flmd pin flashstatuscheck status check of o peration specified immediately before flashgetinfo reading of flash information flashsetinfo setting of flash information flashbootswap swapping of boot area flashsetuserhandler user interrup t handler registration function 25.7.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when re set is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is exec uted. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming m ode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 25-17. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released. chapter 25 flash memory user?s manual u17830ee1v0um00 896 25.7.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 25-10. internal resources used resource name description entry ram area (124 bytes of either internal ram/external ram) routines and parameters used for the flash macr o service are located in this area. the entry program and default parameters are copied by calling a library initialization function. stack area (user stack + 300 bytes) an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code (1900 bytes) program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in user application execution status or self programming status. to use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self programming status the interrupt servicing start address must be registered in advance by a registration function. user?s manual u17830ee1v0um00 897 chapter 26 option function 26.1 mask options this product series has an option data area where a block subject to mask options is specified. when writing a program to a flash memory version or a mask rom version, be sure to set the option data corresponding to the following option in the program at address 007ah as default data. the data in this area cannot be re written during program execution. 7 6 5 4 3 2 1 0 007ah subclock7 subclock6 0 0 0 mp2 wdtmd1 rmopin subclock7 subclock6 selection of subclock 0 0 sub-crystal connection 0 1 setting prohibited 1 0 setting prohibited 1 1 rc oscillation connection mp2 poc function for mask rom 0 without poc function 1 with poc function remarks: 1. mp2 bit is only used for mask rom product. 2. setting of mp2 bit does not affect flash rom product function. 3. for flash product poc function is dist inguished by device name ?m1? and ?m2?. wdtmd1 wdt2 mask option 0 count clock for wdt2 can be selected by software and overflow signal can be selected from intwdt2 or wdt2res. 1 count clock is fixed to ring-osc and overflow signal is fixed to wdt2res. rmopin ring-osc mask option 0 ring-osc can be stopped by software 1 ring-osc cannot be stopped caution: do not make any settings other than the above. remark: in case of mask products, set the option data same as flash memory products. chapter 26 option function preliminary user?s manual u17830ee1v0um00 898 some examples for possible settings are described in table 26-1 (selection is not complete). table 26-1. example settings for mask option (assortment) address set value setting 007ah 00h ring-osc: can be stopped. wdt2: count clock can be selected. overflow signal can be selected from intwdt2 or wdt2res. subclock: crystal resonator connection poc function for mask rom product disabled 03h ring-osc: cannot be stopped. wdt2: count clock is fixed to ring-osc. overflow signal is fixed to wdt2res. subclock: crystal resonator connection poc function for mask rom product disabled c2h ring-osc: can be stopped. wdt2: count clock is fixed to ring-osc. overflow signal is fixed to wdt2res. subclock: rc oscillation connection poc function for mask rom product disabled c7h ring-osc: cannot be stopped. wdt2: count clock is fixed to ring-osc. overflow signal is fixed to wdt2res. subclock: rc oscillation poc function for mask rom product user?s manual u17830ee1v0um00 899 chapter 27 on-chip debug function the v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2 include an on-chip debug unit. by connecting an n-wire emulator, on-chip debugging can be execut ed with the v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2 alone. cautions: 1 the on-chip debug function is provided only in the flash memory version. it is not provided with the mask rom version. however, the ocdm register also exists in the mask rom version and it controls the pull-down resistor connected to the p05/intp2 pin, so set the ocdm register even for the mask rom version. 2. the following debug functions are supported and whether they are usable or not differs depending on the debugger. for details of the debugging function, refer to the user?s manual of the debugger to be used. 27.1 functional outline 27.1.1 type of on-chip debug unit the on-chip debug unit is rcu1 (run control unit 1). 27.1.2 debug functions (1) debug interface communication with the host machine is establish ed by using the drst, dck, dms, ddi, and ddo signals via an n-wire emulator. the communication specif ications of n-wire are used for the interface. (2) on-chip debug on-chip debugging can be executed by preparing wiring and a connector for on-chip debugging on the target system. an n-wire emulator is used as t he connector that conn ects the emulator. clear the ocdm0 bit of the ocdm register (special re gister) to 0 when you use on-chip debug mode. please refer to table 4-3 alternate-function pins of port 0 for details. (3) forced reset function the v850es/fe2, v850es/ff2, v850es/fg2 a nd v850es/fj2 can be forcibly reset. (4) break reset function the cpu can be started in the debug mode immedi ately after reset of the cpu is released. (5) forced break function execution of the user program can be forcibly aborted (however, the illegal operation code exception handler (first address: 00000060h) cannot be used). (6) hardware break function two breakpoints for instruction and access can be us ed. the instruction br eakpoint can abort program execution at any address. the access breakpoint can a bort program execution by data access to any address. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 900 (7) software break function up to four software breakpoints can be set in the internal rom area. the number of software breakpoints that can be set in the ram area differs depending on the debugger to be used. (8) debug monitor function a memory space for debugging that is different fr om the user memory space is used during debugging (background monitor mode). the user progra m can be executed starting from any address. while execution of the user program is aborted, the user resources (suc h as memory and i/o) can be read and written, and the user pr ogram can be downloaded. (9) mask function each signal can be masked. the correspondence with the mask func tions of the debugger (id850nwc) for the n-wire emulator (ie- v850e1-cd-nw) of nec electronics is shown below. nmi0 mask function: nmi pin nmi1 mask function: wdt2 interrupt nmi2 mask function: ? stop mask function: ? hold mask function: hldrq pin reset mask function: reset pin, wdt2 reset, poc reset note , lvi reset, clock monitor reset dbint mask function: ? wait mask function: masks wait pin note this applies only to the products with a power-on clear function. (10) timer function the execution time of the us er program can be measured. (11) peripheral macro operation/st op selection function during break depending on the debugger to be used, whether the perip heral macro operates or is stopped during a break can be selected. ? functions that are al ways stopped during break ? clock monitor ? watchdog timer 2 ? functions that can operate or be stopped during break (however, eac h function cannot be selected individually) ? a/d converter ? timer m ? timer p ? timer q ? watch timer ? peripheral functions that c ontinue operating during break (func tions that cannot be stopped) ? peripheral functions other than above chapter 27 on-chip debug function user?s manual u17830ee1v0um00 901 27.2 connection circuit example ie-v850e1-cd-nw v850es/fj2 vdd dck dms ddi ddo drst reset flmd0 gnd ev dd dck dms ddi ddo drst note 2 reset flmd0 note 3 flmd1/pdl5 ev ss note 1 notes 1. example of pin processing when n-wire emulator is connected 2. a pull-down resistor is provided on chip. 3. for flash memory rewriting 27.3 interface signals the interface signals are described below. (1) drst this is a reset input signal for the on-chip debug un it. it is a negative-logic signal that asynchronously initializes the debug control unit. the ie-v850e1-cd-nw raises the drst signal when it detects v dd of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. when the drst signal goes high, a reset signal is also generated in the cpu. when starting debugging by starti ng the integrated debugger, a cpu reset is always generated. (2) dck this is a clock input signal. it supplies a 20 mhz clo ck from the ie-v850e1-cd-nw. in the on-chip debug unit, the dms and ddi signals are sampled at the rising edg e of the dck signal, and the data ddo is output at its falling edge. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 902 (3) dms this is a transfer mode select signal. the transfer st atus in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in the on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on- chip debug unit at the falling edge of the dck signal. (6) ev dd this signal is used to detect vdd of the target system. if vdd from t he target system is not detected, the signals output from the ie-v850e1-cd-nw (drst, dck, dms, ddi, flmd0, and reset) go into a high- impedance state. (7) flmd0 the flash self programming function is used for the function to download data to the flash memory via the integrated debugger. during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from ie-v850e1-cd-nw connect the flmd0 signal of the ie-v850e1-cd-nw to the flmd0 pin. in the normal mode, nothing is driven by the ie-v850e1-cd-nw (high impedance). during a break, the ie-v850e1-cd-nw raises t he flmd0 pin to the high level when the download function of the integrated debugger is executed. <2> to control from port connect any port of the device to the flmd0 pin. the same port as the one used by the user program to realize the fl ash self programming function may be used. on the console of the integrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. for details, refer to the id850qb ver. 2.80 integrated deb ugger operation user ?s manual (u16973e) . (8) reset this is a system reset input pin. if the drst pin is ma de invalid by the value of the ocdm0 bit of the ocdm register set by the user program, on-chip debugging ca nnot be executed. therefore, reset is effected by the ie-v850e1-cd-nw, using the reset pin, to make the drst pin valid (initialization). chapter 27 on-chip debug function user?s manual u17830ee1v0um00 903 27.4 register (1) on-chip debug m ode register (ocdm) this register is used to select the normal operation m ode or on-chip debug mode. this register is a special register and can be written only in a combination of specific sequences (refer to 3.4.9 special registers ). if the ocdm0 bit is 1 and if the drst pin is high, the on-chip debug mode is selected. this register can be read or written in 8-bit or 1-bit units. after reset: 01h note 1 r/w address: fffff9fch 7 6 5 4 3 2 1 0 ocdm 0 0 0 0 0 0 0 ocdm0 ocdm0 specification of alternate- function pin of on-chip debug function note 2 0 selects normal operation mode (in which a pin that functions alternately as on- chip debug function pin is used as a por t/peripheral function pin) and disconnects the on-chip pull-down resistor of the p05/intp2/drst pin. 1 when drst pin is low: normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) when drst pin is high: on-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) notes 1. reset input sets this register to 01h. on reset by power-on clear: ocdm0 = 0 on occurrence of internal s ource reset (other than power-on clear): the ocdm register holds the value before occurrence of reset. 2. p05/intp2/drst p52/kr2/tiq03/toq03/ddi p53/kr3/tiq00/toq00/ddo p54/kr4/dck p55/kr5/dms chapter 27 on-chip debug function user?s manual u17830ee1v0um00 904 cautions 1. when using the ddi, ddo, dck, and dms pins not as on-chip debug pins but as port pins after external reset, any of the following actions must be taken. ? input a low level to the p05/intp2/drst pin. ? set the ocdm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p05/intp2/drst pin to the low level until <1> is completed. 2. the drst pin has an on-chip pull-down resist or. this resistor is disconnected when the ocdm0 flag is cleared to 0. the mask rom version do es not have an on-chip debug function but it has the ab ove pull-down resistor. wi th the mask rom version also, therefore, the on-chip pull-down resistor must be disconnect ed by clearing the ocdm0 bit to 0. ocdm0 flag (1: pull-down on, 0: pull-down off) 10 to 100 k ? (30 k ? (typ.)) drst 27.5 operation the on-chip debug function is made invalid under the conditions shown in the table below. when this function is not used, keep the drst pin low until the ocdm.ocdm0 flag is cleared to 0. ocdm0 flag drst pin 0 1 l invalid invalid h invalid valid remark l: low-level input h: high-level input the default value of the ocdm0 bit after the pin is reset is 1. it is therefore necessary to clear the ocdm0 bit to 0 when the on-chip debug function is not used, and until then, the drst pin must be kept low (see figure 27-1 ). the drst pin is internally pulled down while the ocdm 0 bit is 1, and therefore, it can be left open. after poc reset, the default value of t he ocdm0 bit is 0, and the normal operation mode is selected. therefore, it is necessary to set the ocdm0 bit to 1 by re setting the pin to use the on-chip debug mode. if poc reset occurs during on-chip debugging, communica tion with the emulator is di srupted. therefore, poc reset cannot be emulated (see figure 27-2 ). chapter 27 on-chip debug function user?s manual u17830ee1v0um00 905 figure 27-1. timing chart of selecting normal operation mode normal operation mode reset (external reset input) ocdm0 drst (on-chip debug reset input) poc (internal reset) normal operation mode write 0 from cpu (to specify normal operation mode) figure 27-2. timing chart of selecting on-chip debug mode reset (external reset input) ocdm0 drst (on-chip debug reset input) poc (internal reset) normal operation mode on-chip debug mode to use the on-chip debug mode by using the power-on clear function, input the external reset signal longer than the power-on clear detection signal (internal reset) occurrence of power-on clear detection signal (internal reset) clears the ocdm0 bit to 00 (normal operation mode) caution to use the on-chip debug func tion in a product with a power-on cl ear function, inpu t a low level to the reset input pin for 2,000 ms or longer after power application. (afte r power-on, from power- voltage is upper 4v, please rel ease the reset input pin.). chapter 27 on-chip debug function user?s manual u17830ee1v0um00 906 27.6 rom security function 27.6.1 security id the flash memory versions of the v850es/fe2, v850es/ff2, v850es/fg2 and v850es/fj2 perform authentication using a 10-byte id code to prevent t he contents of the flash memory from being read by an unauthorized person during on-chip debugging by the n-wire emulator. set the id code in the 10-byte on-chip flash memory area from 0000070h to 0000079h to allow the debugger perform id authentication. ? when the n-wire emulator is start ed, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if t he n-wire emulator enable flag is 0, even if the id codes match. if the ids match, the security is released and reading flas h memory and using the n-wire emulator are enabled. (1) id code be sure to write an id code when writing a program to the internal rom. the area of the id code is 10 bytes wide and in the range of addresses 00000070h to 00000079h. the id code when the memory is erased is shown below. address id code 00000079h ffh 00000078h ffh 00000077h ffh 00000076h ffh 00000075h ffh 00000074h ffh 00000073h ffh 00000072h ffh 00000071h ffh 00000070h ffh (2) security bit bit 7 of address 00000079h enables or disables use of the n-wire emulator. ? bit 7 of address 00000079h 0: disable 1: enable cautions 1. if the value of addr ess 00000079h is 00h to 7fh, the n-wire emulator cannot be connected. 2. if the value of address 0000007 9h is 80h to ffh, the n-wire em ulator can be connected if the 10-byte id code to be input when the n-wire emulator is connected matches. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 907 27.6.2 setting example when the following values are set to addresses 0x70 to 0x79 address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 0x7a flash mask option (see chapter 26: option function .) the following shows program exampl es when the ca850 is used. [program example 1] following the ?ilgop? section (address 0x60); enter the 10 -byte security code and 1-byte system reserved area data (00h). #--------------------------------------- # ilgop handler #--------------------------------------- .section "ilgop" -- interrupt handler address 0x60 -- input ilgop handler code .org 0x10 -- skip handler address to 0x70 #--------------------------------------- # securityid (continue ilgop handler) #--------------------------------------- .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code .byte 0x00 --flash mask option code caution when using the ca850 ver. 3.00 or later, sp ecify the option for disab ling the generation of the security id the security id addition function by linker is adde d from the ca850 ver. 3.00. as a result, errors occur during linking in th e above program example. error message: f4264: start address (0x00000070) of section "security_id" overlaps previous section "ilgop" ended before address (0xxxxxxxxx). chapter 27 on-chip debug function user?s manual u17830ee1v0um00 908 [program example 2] enter the 10-byte security code using t he ?security_id? section (address 0x70). #--------------------------------------- # security_id #--------------------------------------- .section "security_id" .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code caution data that can be set to th e ?security_id? section is limited to 10 bytes. for this reason, data cannot be set to the system rese rved area (0x7a) following the security code. consequently, when using a device that needs to set data to the system reser ved area, set the security code and system reserved area data using th e method shown in ?p rogram example 1?. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 909 27.7 connection to n-wire emulator to connect the n-wire emulator, a connector for emulator connection and a connection circuit must be mounted on the target system. select the kel connector, mictor connector (product na me: 2-767004-2, tyco electron ics amp k.k.), or a 20-pin general-purpose connector with a 2.54 mm pitch as the emul ator connection connector. connectors other than the kel connector may not be supported by some emulators. re fer to the user?s manual of the emulator to be used. 27.7.1 kel connector o product name ? 8830e-026-170s (kel): straight type ? 8830e-026-170l (kel): right-angle type figure 27-3. connection to n-wire emulator (nec electronics ie-v850e1-cd-nw: n-wire card) host machine pcmcia card slot target system n-wire card emulator connection connector 8830e-026-170s (kel) chapter 27 on-chip debug function user?s manual u17830ee1v0um00 910 (1) pin configuration figure 27-4 shows the pin configuration of the conn ector for emulator connection (target system side), and table 27-1 shows the pin functions. figure 27-4. pin configuration of connector for emulator connection (target system side) (top view) b12 a12 b2 a2 b13 a13 b1 a1 board side caution evaluate the dimensions of the connector when actually mounting the connector on the target board. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 911 (2) pin functions the following table shows the pin functions of the connec tor for emulator connection (target system side). ?i/o? indicates the direction viewed from the device. table 27-1. pin functions of connector for emulator connection (target system side) pin no. pin name i/o pin function a1 (reserved 1) ? (connect to gnd) a2 (reserved 2) ? (connect to gnd) a3 (reserved 3) ? (connect to gnd) a4 (reserved 4) ? (connect to gnd) a5 (reserved 5) ? (connect to gnd) a6 (reserved 6) ? (connect to gnd) a7 ddi input data input for n-wire interface a8 dck input clock input for n-wire interface a9 dms input transfer mode select input for n-wire interface a10 ddo output data output for n-wire interface a11 drst input on-chip debug unit reset input a12 reset input reset input. (in a system that uses only poc reset and not pin reset, some emulators input an external reset signal as shown in figure 27-5 to set the ocdm0 bit to 1.) a13 flmd0 input control signal for flash download (flash memory versions only) b1 gnd ? ? b2 gnd ? ? b3 gnd ? ? b4 gnd ? ? b5 gnd ? ? b6 gnd ? ? b7 gnd ? ? b8 gnd ? ? b9 gnd ? ? b10 gnd ? ? b11 (reserved 8) ? (connect to gnd) b12 (reserved 9) ? (connect to gnd) b13 v dd ? 5 v input (for monitoring power supply to target) cautions 1. the connection of the pins not sup ported depends upon the emulator to be used. 2. the pattern of the target board must satisfy the following conditions. ? the pattern length must be 100 mm or less. ? the clock signal must be shielded by gnd. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 912 (3) example of recommended circuit an example of the recommended circuit of the connector for emulator connection (target system side) is shown below. figure 27-5. example of recommended emulator connection circuit v850es/fj2 flmd0 (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) ddi dck dms ddo drst flmd0 reset v dd note 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd (reserved 8) (reserved 9) note 2 note 1 note 1 note 1 note 1 note 4 5 v 5 v a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a13 a12 b13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 ddi dck dms ddo drst kel connector 8830e-026-170s reset note 1 notes 1. the pattern length must be 100 mm or less. 2. shield the dck signal by enclosing it with gnd. 3. this pin is used to detect power to the target board. connect the voltage of the n-wire interface to this pin. 4. in a system that uses only poc reset and not pin rese t, some emulators input an external reset signal as shown in figure 27-5 to set the ocdm0 bit to 1. caution the n-wire emulator may not support a 5 v interface and may require a level shifter. refer to the user?s manual of the emulator to be used. chapter 27 on-chip debug function user?s manual u17830ee1v0um00 913 27.8 cautions (1) if a reset signal is input (from the target system or a reset signal from an internal reset source) during run (program execution), the br eak function may malfunction. (2) even if the reset signal is masked by the mask function, the i/o buffer (port pin) ma y be reset if a reset signal is input from a pin. (3) with a debugger that can set software breakpoints in the internal flash memory, the breakpoints temporarily become invalid when pin reset or internal reset is e ffected. the breakpoints becom e valid again if a break such as a hardware break or forced break is ex ecuted. until then, no software break occurs. (4) pin reset during a break is masked and the cpu and per ipheral i/o are not reset. if pi n reset or internal reset is generated as soon as the flash memo ry is rewritten by dma or read by the ram monitor function while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. (5) the poc reset operation cannot be emulated. (6) when the following conditions (a) and (b) are satisfied and operation is stopped on the emulator due to a break, etc., the watchdog timer 2 does not stop and a reset or non-maskable interrupt occurs. when a reset occurs, the debugger hangs up. (a) the main clock or subclock is used as the source clock for watchdog timer 2. (b) the internal oscillation clock is stopped (rcm.rstop bit = 1). to avoid this, perform either of the following. ? when an emulator is used, the internal osci llation clock is used as the source clock. ? when an emulator is used, disable the internal oscillator oscillation. (7) when the following conditions (a) and (b) are satisfied and operation is stopped on the emulator due to a break, etc., tmm does not stop even if the periphe ral break function is set to ?break?. (a) either the intwt, internal oscillation clock (f r /8), or subclock are selected as the tmm source clock. (b) the main clock is stopped. to avoid this, perform either of the following. ? when an emulator is used, the main clock (f xx , f xx /2, f xx /4, f xx /64, f xx /512) is used as the source clock. ? when an emulator is used, disable the main clock oscillation. (8) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output. (9) when break command is based, an d application software accesses for uarta/csib/afcan peripheral i/o register, to restart without reset, csib, uart a and afcan that may be not correct operation. (10) do not mount a device that was used for debugging on a mass-produced product (this is because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed). user?s manual u17830ee1v0um00 914 appendix a register index (1/15) symbol function register name unit page ada0cr0 a/d conversion result register 0 adc 469 ada0cr0h a/d conversion result register 0h adc 469 ada0cr1 a/d conversion result register 1 adc 469 ada0cr10 a/d conversion result register 10 adc 469 ada0cr10h a/d conversion result register 10h adc 469 ada0cr11 a/d conversion result register 11 adc 469 ada0cr11h a/d conversion result register 11h adc 469 ada0cr12 a/d conversion result register 12 adc 469 ada0cr12h a/d conversion result register 12h adc 469 ada0cr13 a/d conversion result register 13 adc 469 ada0cr13h a/d conversion result register 13h adc 468 ada0cr14 a/d conversion result register 14 adc 468 ada0cr14h a/d conversion result register 14h adc 469 ada0cr15 a/d conversion result register 15 adc 469 ada0cr15h a/d conversion result register 15h adc 469 ada0cr16 a/d conversion result register 16 adc 469 ada0cr16h a/d conversion result register 16h adc 469 ada0cr17 a/d conversion result register 17 adc 469 ada0cr17h a/d conversion result register 17h adc 469 ada0cr18 a/d conversion result register 18 adc 469 ada0cr18h a/d conversion result register 18h adc 469 ada0cr19 a/d conversion result register 19 adc 469 ada0cr19h a/d conversion result register 19h adc 469 ada0cr1h a/d conversion result register 1h adc 469 ada0cr2 a/d conversion result register 2 adc 469 ada0cr20 a/d conversion result register 20 adc 469 ada0cr20h a/d conversion result register 20h adc 469 ada0cr21 a/d conversion result register 21 adc 469 ada0cr21h a/d conversion result register 21h adc 469 ada0cr22 a/d conversion result register 22 adc 469 ada0cr22h a/d conversion result register 22h adc 469 ada0cr23 a/d conversion result register 23 adc 469 ada0cr23h a/d conversion result register 23h adc 469 ada0cr2h a/d conversion result register 2h adc 469 ada0cr3 a/d conversion result register 3 adc 469 ada0cr3h a/d conversion result register 3h adc 469 ada0cr4 a/d conversion result register 4 adc 469 ada0cr4h a/d conversion result register 4h adc 469 ada0cr5 a/d conversion result register 5 adc 469 appendix a user?s manual u17830ee1v0um00 915 (2/15) symbol function register name unit page ada0cr5h a/d conversion result register 5h adc 469 ada0cr6 a/d conversion result register 6 adc 469 ada0cr6h a/d conversion result register 6h adc 469 ada0cr7 a/d conversion result register 7 adc 469 ada0cr7h a/d conversion result register 7h adc 469 ada0cr8 a/d conversion result register 8 adc 469 ada0cr8h a/d conversion result register 8h adc 469 ada0cr9 a/d conversion result register 9 adc 469 ada0cr9h a/d conversion result register 9h adc 469 ada0m0 a/d converter mode register 0 adc 465 ada0m1 a/d converter mode register 1 adc 466 ada0m2 a/d converter mode register 2 adc 467 ada0pfm power-fail comparison mode register adc 472 ada0pft power-fail comparison threshold value register adc 472 ada0s a/d converter channel specification register 0 adc 468 awc address wait control register bcu 302 bcc bus cycle control register bcu 303 bpc peripheral i/o area select control register cpu 176 bsc bus size configuration register bus bcu 293 c0brp can0 module bit rate prescaler register can 678 c0btr can0 module bit rate register can 679 c0ctrl can0 module control register can 668 c0erc can0 module error counter register can 674 c0gmabt can0 global block transmission control register can 663 c0gmabtd can0 global block transmission delay setting register can 665 c0gmcs can0 global clock select register can 662 c0gmctrl can0 global control register can 660 c0ie can0 module interrupt enable register can 675 c0info can0 module information register can 673 c0ints can0 module interrupt status register can 677 c0lec can0 module last error information register can 672 c0lipt can0 module last in-pointer register can 681 c0lopt can0 module last out-pointer register can 683 c0mask1h can0 module mask 1 register h can 666 c0mask1l can0 module mask 1 register l can 666 c0mask2h can0 module mask 2 register h can 666 c0mask2l can0 module mask 2 register l can 666 c0mask3h can0 module mask 3 register h can 666 c0mask3l can0 module mask 3 register l can 666 c0mask4h can0 module mask 4 register h can 666 c0mask4l can0 module mask 4 register l can 665 c0mconfm can0 message configuration register m can 690 c0mctrlm can0 message control register m can 692 appendix a user?s manual u17830ee1v0um00 916 (3/15) symbol function register name unit page c0mdata01m can0 message data byte 01 register m can 687 c0mdata0m can0 message data byte 0 register m can 687 c0mdata1m can0 message data byte 1 register m can 687 c0mdata23m can0 message data byte 23 register m can 687 c0mdata2m can0 message data byte 2 register m can 687 c0mdata3m can0 message data byte 3 register m can 687 c0mdata45m can0 message data byte 45 register m can 687 c0mdata4m can0 message data byte 4 register m can 687 c0mdata5m can0 message data byte 5 register m can 687 c0mdata67m can0 message data byte 67 register m can 687 c0mdata6m can0 message data byte 6 register m can 687 c0mdata7m can0 message data byte 7 register m can 687 c0mdlcm can0 message data length code register m can 689 c0midhm can0 message id register hm can 691 c0midlm can0 message id register lm can 691 c0rgpt can0 module receive history list register can 682 c0tgpt can0 module transmit history list register can 684 c0ts can0 module time stamp register can 685 c1brp can1 module bit rate prescaler register can 678 c1btr can1 module bit rate register can 679 c1ctrl can1 module control register can 668 c1erc can1 module error counter register can 674 c1gmabt can1 global block transmission control register can 663 c1gmabtd can1 global block transmission delay setting register can 665 c1gmcs can1 global clock select register can 662 c1gmctrl can1 global control register can 660 c1ie can1 module interrupt enable register can 675 c1info can1 module information register can 673 c1ints can1 module interrupt status register can 677 c1lec can1 module last error information register can 672 c1lipt can1 module last in-pointer register can 681 c1lopt can1 module last out-pointer register can 683 c1mask1h can1 module mask 1 register h can 666 c1mask1l can1 module mask 1 register l can 666 c1mask2h can1 module mask 2 register h can 666 c1mask2l can1 module mask 2 register l can 666 c1mask3h can1 module mask 3 register h can 666 c1mask3l can1 module mask 3 register l can 666 c1mask4h can1 module mask 4 register h can 665 c1mask4l can1 module mask 4 register l can 666 c1mconfm can1 message configuration register m can 690 c1mctrlm can1 message control register m can 692 appendix a user?s manual u17830ee1v0um00 917 (4/15) symbol function register name unit page c1mdata01m can1 message data byte 01 register m can 687 c1mdata0m can1 message data byte 0 register m can 687 c1mdata1m can1 message data byte 1 register m can 687 c1mdata23m can1 message data byte 23 register m can 687 c1mdata2m can1 message data byte 2 register m can 687 c1mdata3m can1 message data byte 3 register m can 687 c1mdata45m can1 message data byte 45 register m can 687 c1mdata4m can1 message data byte 4 register m can 687 c1mdata5m can1 message data byte 5 register m can 687 c1mdata67m can1 message data byte 67 register m can 687 c1mdata6m can1 message data byte 6 register m can 687 c1mdata7m can1 message data byte 7 register m can 687 c1mdlcm can1 message data length code register m can 689 c1midhm can1 message id register hm can 691 c1midlm can1 message id register lm can 691 c1rgpt can1 module receive history list register can 682 c1tgpt can1 module transmit history list register can 684 c1ts can1 module time stamp register can 685 c2brp can2 module bit rate prescaler register can 678 c2btr can2 module bit rate register can 679 c2ctrl can2 module control register can 668 c2erc can2 module error counter register can 674 c2erric interrupt control register can 686 c2gmabt can2 global block transmission control register can 663 c2gmabtd can2 global block transmission delay setting register can 665 c2gmcs can2 global clock select register can 662 c2gmctrl can2 global control register can 660 c2ie can2 module interrupt enable register can 675 c2info can2 module information register can 673 c2ints can2 module interrupt status register can 677 c2lec can2 module last error information register can 672 c2lipt can2 module last in-pointer register can 681 c2lopt can2 module last out-pointer register can 683 c2mask1h can2 module mask 1 register h can 666 c2mask1l can2 module mask 1 register l can 666 c2mask2h can2 module mask 2 register h can 666 c2mask2l can2 module mask 2 register l can 666 c2mask3h can2 module mask 3 register h can 666 c2mask3l can2 module mask 3 register l can 666 c2mask4h can2 module mask 4 register h can 666 c2mask4l can2 module mask 4 register l can 666 c2mconfm can2 message configuration register m can 690 c2mctrlm can2 message control register m can 692 appendix a user?s manual u17830ee1v0um00 918 (5/15) symbol function register name unit page c2mdata01m can2 message data byte 01 register m can 687 c2mdata0m can2 message data byte 0 register m can 687 c2mdata1m can2 message data byte 1 register m can 687 c2mdata23m can2 message data byte 23 register m can 687 c2mdata2m can2 message data byte 2 register m can 687 c2mdata3m can2 message data byte 3 register m can 687 c2mdata45m can2 message data byte 45 register m can 687 c2mdata4m can2 message data byte 4 register m can 687 c2mdata5m can2 message data byte 5 register m can 687 c2mdata67m can2 message data byte 67 register m can 687 c2mdata6m can2 message data byte 6 register m can 687 c2mdata7m can2 message data byte 7 register m can 687 c2mdlcm can2 message data length code register m can 689 c2midhm can2 message id register hm can 691 c2midlm can2 message id register lm can 691 c2rgpt can2 module receive history list register can 682 c2tgpt can2 module transmit history list register can 684 c2ts can2 module time stamp register can 685 c3brp can3 module bit rate prescaler register can 678 c3btr can3 module bit rate register can 679 c3ctrl can3 module control register can 668 c3erc can3 module error counter register can 674 c3gmabt can3 global block transmission control register can 663 c3gmabtd can3 global block transmission delay setting register can 665 c3gmcs can3 global clock select register can 662 c3gmctrl can3 global control register can 660 c3ie can3 module interrupt enable register can 675 c3info can3 module information register can 673 c3ints can3 module interrupt status register can 677 c3lec can3 module last error information register can 672 c3lipt can3 module last in-pointer register can 681 c3lopt can3 module last out-pointer register can 683 c3mask1h can3 module mask 1 register h can 666 c3mask1l can3 module mask 1 register l can 666 c3mask2h can3 module mask 2 register h can 666 c3mask2l can3 module mask 2 register l can 666 c3mask3h can3 module mask 3 register h can 666 c3mask3l can3 module mask 3 register l can 666 c3mask4h can3 module mask 4 register h can 666 c3mask4l can3 module mask 4 register l can 666 c3mconfm can3 message configuration register m can 690 c3mctrlm can3 message control register m can 692 appendix a user?s manual u17830ee1v0um00 919 (6/15) symbol function register name unit page c3mdata01m can3 message data byte 01 register m can 687 c3mdata0m can3 message data byte 0 register m can 687 c3mdata1m can3 message data byte 1 register m can 687 c3mdata23m can3 message data byte 23 register m can 687 c3mdata2m can3 message data byte 2 register m can 687 c3mdata3m can3 message data byte 3 register m can 687 c3mdata45m can3 message data byte 45 register m can 687 c3mdata4m can3 message data byte 4 register m can 687 c3mdata5m can3 message data byte 5 register m can 687 c3mdata67m can3 message data byte 67 register m can 687 c3mdata6m can3 message data byte 6 register m can 687 c3mdata7m can3 message data byte 7 register m can 687 c3mdlcm can3 message data length code register m can 689 c3midhm can3 message id register hm can 691 c3midlm can3 message id register lm can 691 c3rgpt can3 module receive history list register can 682 c3tgpt can3 module transmit history list register can 684 c3ts can3 module time stamp register can 685 cb0ctl0 csib0 control register 0 csi 533 cb0ctl1 csib0 control register 1 csi 535 cb0ctl2 csib0 control register 2 csi 536 cb0rx csib0 receive data register csi 532 cb0rxl csib0 receive data register l csi 532 cb0str csib0 status register csi 537 cb0tx csib0 transmit data register csi 532 cb0txl csib0 transmit data register l csi 532 cb1ctl0 csib1 control register 0 csi 533 cb1ctl1 csib1 control register 1 csi 535 cb1ctl2 csib1 control register 2 csi 536 cb1rx csib1 receive data register csi 532 cb1rxl csib1 receive data register l csi 532 cb1str csib1 status register csi 537 cb1tx csib1 transmit data register csi 532 cb1txl csib1 transmit data register l csi 532 cb2ctl0 csib2 control register 0 csi 533 cb2ctl1 csib2 control register 1 csi 535 cb2ctl2 csib2 control register 2 csi 536 cb2rx csib2 receive data register csi 532 cb2rxl csib2 receive data register l csi 532 cb2str csib2 status register csi 537 cb2tx csib2 transmit data register csi 532 cb2txl csib2 transmit data register l csi 532 ccls cpu operating clock status register bcu 318 clm clock monitor mode register cm 860 appendix a user?s manual u17830ee1v0um00 920 (7/15) symbol function register name unit page dadc0 dma addressing control register 0 dma 760 dadc1 dma addressing control register 1 dma 760 dadc2 dma addressing control register 2 dma 760 dadc3 dma addressing control register 3 dma 760 dbc0 dma transfer count register 0 dma 759 dbc1 dma transfer count register 1 dma 759 dbc2 dma transfer count register 2 dma 759 dbc3 dma transfer count register 3 dma 759 dchc0 dma channel control register 0 dma 759 dchc1 dma channel control register 1 dma 761 dchc2 dma channel control register 2 dma 761 dchc3 dma channel control register 3 dma 761 dda0h dma destination address register 0h dma 758 dda0l dma destination address register 0l dma 758 dda1h dma destination address register 1l dma 758 dda1l dma destination address register 1h dma 758 dda2h dma destination address register 2h dma 758 dda2l dma destination address register 2l dma 758 dda3h dma destination address register 3h dma 758 dda3l dma destination address register 3l dma 758 dsa0h dma source address register 0h dma 757 dsa0l dma source address register 0l dma 757 dsa1h dma source address register 1h dma 757 dsa1l dma source address register 1l dma 757 dsa2h dma source address register 2h dma 757 dsa2l dma source address register 2l dma 757 dsa3h dma source address register 3h dma 757 dsa3l dma source address register 3l dma 757 dtfr0 dma trigger source register 0 dma 763 dtfr1 dma trigger source register 1 dma 763 dtfr2 dma trigger source register 2 dma 763 dtfr3 dma trigger source register 3 dma 763 dwc0 data wait control register 0 bcu 300 imr0 interrupt mask register 0 intc 804 imr0h interrupt mask register 0h intc 804 imr0l interrupt mask register 0l intc 804 imr1 interrupt mask register 1 intc 804 imr1h interrupt mask register 1h intc 804 imr1l interrupt mask register 1l intc 804 imr2 interrupt mask register 2 intc 804 imr2h interrupt mask register 2h intc 804 imr2l interrupt mask register 2l intc 804 imr3 interrupt mask register 3 intc 804 imr3h interrupt mask register 3h intc 804 imr3l interrupt mask register 3l intc 804 appendix a user?s manual u17830ee1v0um00 921 (8/15) symbol function register name unit page imr4 interrupt mask register 4 intc 804 imr4h interrupt mask register 4h intc 804 imr4l interrupt mask register 4l intc 804 imr5l interrupt mask register 5l intc 804 intf0 external interrupt falling edge specification register 0 intc 808 intf1 external interrupt falling edge specification register 1 intc 810 intf3 external interrupt falling edge specification register 3 intc 812 intf3h external interrupt falling edge specification register 3h intc 812 intf3l external interrupt falling edge specification register 3l intc 812 intf6l external interrupt falling edge specification register 6l intc 814 intf8 external interrupt falling edge specification register 8 intc 815 intf9h external interrupt falling edge specification register 9h intc 816 intr0 external interrupt rising edge specification register 0 intc 809 intr1 external interrupt rising edge specification register 1 intc 811 intr3 external interrupt rising edge specification register 3 intc 813 intr3h external interrupt rising edge specification register 3h intc 813 intr3l external interrupt rising edge specification register 3l intc 813 intr6l external interrupt rising edge specification register 6l intc 814 intr8 external interrupt rising edge specification register 8 intc 815 intr9h external interrupt rising edge specification register 9h intc 816 ispr in-service priority register intc 806 kric interrupt control register intc 686 krm key return mode register kr 828 lockr lock register bcu 321 lviic interrupt control register intc 686 lvim low-voltage detection register lvd 867 lvis low-voltage detection level select register lvd 868 nfc noise elimination control register intc 817 ocdm on-chip debug mode register debug 903 osts oscillation stabilization time select register wdt 457 p0 port 0 port 196 p00nfc tip00 noise eliminator control register timer 338 p01nfc tip01 noise eliminator control register timer 338 p1 port 1 port 202 p10nfc tip10 noise eliminator control register timer 338 p11nfc tip11 noise eliminator control register timer 338 p12 port 12 port 258 p20nfc tip20 noise eliminator control register timer 338 p21nfc tip21 noise eliminator control register timer 338 p3 port 3 port 207 p30nfc tip30 noise eliminator control register timer 338 p31nfc tip31 noise eliminator control register timer 338 p3h port 3h port 207 p3l port 3l port 207 appendix a user?s manual u17830ee1v0um00 922 (9/15) symbol function register name unit page p4 port 4 port 217 p5 port 5 port 221 p6 port 6 port 228 p6h port 6h port 228 p6l port 6l port 228 p7 port 7 port 237 p7h port 7h port 237 p7l port 7l port 237 p8 port 8 port 240 p9 port 9 port 246 p9h port 9h port 246 p9l port 9l port 246 pcc processor clock control register bcu 316 pcd port cd port 260 pclm programmable clock mode register bcu 323 pcm port cm port 262 pcs port cs port 266 pct port ct port 270 pdl port dl port 275 pdlh port dlh port 275 pdll port dll port 275 pemu1 peripheral emulation register 1 lvd 869 pfc0 port function control register 0 port 198 pfc3l port function control register 3l port 211 pfc5 port function control register 5 port 223 pfc6 port function control register 6 port 232 pfc6h port function control register 6h port 232 pfc6l port function control register 6l port 232 pfc9 port function control register 9 port 251 pfc9h port function control register 9h port 251 pfc9l port function control register 9l port 251 pfce3l port function control expansion register 3l port 211 pfce5 port function control expansion register 5 port 223 pfce9 port function control expansion register 9 port 252 pfce9h port function control expansion register 9h port 252 pfce9l port function control expansion register 9l port 252 pic0 interrupt control register intc 783 pic1 interrupt control register intc 783 pic10 interrupt control register intc 783 pic11 interrupt control register intc 783 pic12 interrupt control register intc 783 pic13 interrupt control register intc 783 pic14 interrupt control register intc 783 pic2 interrupt control register intc 783 appendix a user?s manual u17830ee1v0um00 923 (10/15) symbol function register name unit page pic3 interrupt control register intc 783 pic4 interrupt control register intc 783 pic5 interrupt control register intc 783 pic6 interrupt control register intc 783 pic7 interrupt control register intc 783 pic8 interrupt control register intc 783 pic9 interrupt control register intc 783 pllctl pll control register bcu 320 plls pll lockup time specification register bcu 322 pm0 port mode register 0 port 196 pm1 port mode register 1 port 202 pm12 port mode register 12 port 258 pm3 port mode register 3 port 208 pm3h port mode register 3h port 208 pm3l port mode register 3l port 208 pm4 port mode register 4 port 217 pm5 port mode register 5 port 221 pm6 port mode register 6 port 229 pm6h port mode register 6h port 229 pm6l port mode register 6l port 229 pm7 port mode register 7 port 238 pm7h port mode register 7h port 238 pm7l port mode register 7l port 238 pm8 port mode register 8 port 240 pm9 port mode register 9 port 247 pm9h port mode register 9h port 247 pm9l port mode register 9l port 247 pmc0 port mode control register 0 port 197 pmc1 port mode control register 1 port 203 pmc3 port mode control register 3 port 209 pmc3h port mode control register 3 h port 209 pmc3l port mode control register 3 l port 209 pmc4 port mode control register 4 port 218 pmc5 port mode control register 5 port 222 pmc6 port mode control register 6 port 230 pmc6h port mode control register 6 h port 230 pmc6l port mode control register 6 l port 230 pmc8 port mode control register 8 port 241 pmc9 port mode control register 9 port 248 pmc9h port mode control register 9 h port 248 pmc9l port mode control register 9 l port 248 pmccm port mode control register cm port 264 pmccs port mode control register cs port 268 pmcct port mode control register ct port 272 appendix a user?s manual u17830ee1v0um00 924 (11/15) symbol function register name unit page pmcd port mode register cd port 260 pmcdl port mode control register dl port 277 pmcdlh port mode control register dlh port 277 pmcdll port mode control register dll port 277 pmcm port mode register cm port 263 pmcs port mode register cs port 267 pmct port mode register ct port 271 pmdl port mode register dl port 276 pmdlh port mode register dlh port 276 pmdll port mode register dll port 276 prcmd command register cpu 179 prscm0 prescaler compare register 0 wt 455 prsm0 prescaler mode register 0 wt 454 psc power save control register standby 849 psmr power save mode register standby 850 pu0 pull-up resistor option register 0 port 198 pu1 pull-up resistor option register 1 port 203 pu3 pull-up resistor option register 3 port 213 pu3h pull-up resistor option register 3h port 213 pu3l pull-up resistor option register 3l port 213 pu4 pull-up resistor option register 4 port 218 pu5 pull-up resistor option register 5 port 225 pu6 pull-up resistor option register 6 port 234 pu6h pull-up resistor option register 6h port 234 pu6l pull-up resistor option register 6l port 234 pu8 pull-up resistor option register 8 port 242 pu9 pull-up resistor option register 9 port 255 pu9h pull-up resistor option register 9h port 255 pu9l pull-up resistor option register 9l port 255 q00nfc tiq00 noise eliminator control register timer 397 q01nfc tiq01 noise eliminator control register timer 397 q02nfc tiq02 noise eliminator control register timer 397 q03nfc tiq03 noise eliminator control register timer 397 q10nfc tiq10 noise eliminator control register timer 397 q11nfc tiq11 noise eliminator control register timer 397 q12nfc tiq12 noise eliminator control register timer 397 q13nfc tiq13 noise eliminator control register timer 397 q20nfc tiq20 noise eliminator control register timer 397 q21nfc tiq21 noise eliminator control register timer 397 q22nfc tiq22 noise eliminator control register timer 397 q23nfc tiq23 noise eliminator control register timer 397 rams internal ram data status register lvd 868 rcm ring osc mode register bcu 318 resf reset source flag register reset 853 appendix a user?s manual u17830ee1v0um00 925 (12/15) symbol function register name unit page sar successive approximation register adc 463 selcnt0 selector operation control register 0 timer 374 selcnt1 selector operation control register 1 timer 376 sys system status register cpu 180 tm0cmp0 tmm0 compare register 0 timer 442 tm0ctl0 tmm0 control register 0 timer 443 tm0eqic0 interrupt control register intc 783 tp0ccic0 interrupt control register intc 783 tp0ccic1 interrupt control register intc 783 tp0ccr0 tmp0 capture/compare register 0 timer 327 tp0ccr1 tmp0 capture/compare register 1 timer 328 tp0cnt tmp0 counter read buffer register timer 238 tp0ctl0 tmp0 control register 0 timer 330 tp0ctl1 tmp0 control register 1 timer 332 tp0ioc0 tmp0 i/o control register 0 timer 334 tp0ioc1 tmp0 i/o control register 1 timer 335 tp0ioc2 tmp0 i/o control register 2 timer 336 tp0opt0 tmp0 option register timer 337 tp0ovic interrupt control register intc 783 tp1ccic0 interrupt control register intc 783 tp1ccic1 interrupt control register intc 783 tp1ccr0 tmp1 capture/compare register 0 timer 327 tp1ccr1 tmp1 capture/compare register 1 timer 328 tp1cnt tmp1 counter read buffer register timer 329 tp1ctl0 tmp1 control register 0 timer 330 tp1ctl1 tmp1 control register 1 timer 332 tp1ioc0 tmp1 i/o control register 0 timer 334 tp1ioc1 tmp1 i/o control register 1 timer 335 tp1ioc2 tmp1 i/o control register 2 timer 336 tp1opt0 tmp1 option register timer 337 tp1ovic interrupt control register intc 783 tp2ccic0 interrupt control register intc 783 tp2ccic1 interrupt control register intc 783 tp2ccr0 tmp2 capture/compare register 0 timer 327 tp2ccr1 tmp2 capture/compare register 1 timer 328 tp2cnt tmp2 counter read buffer register timer 329 tp2ctl0 tmp2 control register 0 timer 330 tp2ctl1 tmp2 control register 1 timer 332 tp2ioc0 tmp2 i/o control register 0 timer 334 tp2ioc1 tmp2 i/o control register 1 timer 335 tp2ioc2 tmp2 i/o control register 2 timer 336 tp2opt0 tmp2 option register timer 337 tp2ovic interrupt control register intc 783 tp3ccic0 interrupt control register intc 783 appendix a user?s manual u17830ee1v0um00 926 (13/15) symbol function register name unit page tp3ccic1 interrupt control register intc 783 tp3ccr0 tmp3 capture/compare register 0 timer 327 tp3ccr1 tmp3 capture/compare register 1 timer 328 tp3cnt tmp3 counter read buffer register timer 329 tp3ctl0 tmp3 control register 0 timer 330 tp3ctl1 tmp3 control register 1 timer 332 tp3ioc0 tmp3 i/o control register 0 timer 334 tp3ioc1 tmp3 i/o control register 1 timer 335 tp3ioc2 tmp3 i/o control register 2 timer 336 tp3opt0 tmp3 option register timer 337 tp3ovic interrupt control register intc 783 tq0ccic0 interrupt control register intc 783 tq0ccic1 interrupt control register intc 783 tq0ccic2 interrupt control register intc 783 tq0ccic3 interrupt control register intc 783 tq0ccr0 tmq1 capture/compare register 0 timer 383 tq0ccr1 tmq1 capture/compare register 1 timer 384 tq0ccr2 tmq1 capture/compare register 2 timer 385 tq0ccr3 tmq1 capture/compare register 3 timer 386 tq0cnt tmq0 counter read buffer register timer 387 tq0ctl0 tmq0 control register 0 timer 388 tq0ctl1 tmq0 control register 1 timer 390 tq0ioc0 tmq0 i/o control register 0 timer 392 tq0ioc1 tmq0 i/o control register 1 timer 393 tq0ioc2 tmq0 i/o control register 2 timer 395 tq0opt0 tmq0 option register 0 timer 396 tq0ovic interrupt control register intc 783 tq1ccic0 interrupt control register intc 783 tq1ccic1 interrupt control register intc 783 tq1ccic2 interrupt control register intc 783 tq1ccic3 interrupt control register intc 783 tq1ccr0 tmq0 capture/compare register 0 timer 383 tq1ccr1 tmq0 capture/compare register 1 timer 384 tq1ccr2 tmq0 capture/compare register 2 timer 385 tq1ccr3 tmq0 capture/compare register 3 timer 386 tq1cnt tmq1 counter read buffer register timer 387 tq1ctl0 tmq1 control register 0 timer 388 tq1ctl1 tmq1 control register 1 timer 390 tq1ioc0 tmq1 i/o control register 0 timer 392 tq1ioc1 tmq1 i/o control register 1 timer 393 tq1ioc2 tmq1 i/o control register 2 timer 395 tq1opt0 tmq1 timer option register 0 timer 396 tq1ovic interrupt control register intc 783 tq2ccic0 interrupt control register intc 783 appendix a user?s manual u17830ee1v0um00 927 (14/15) symbol function register name unit page tq2ccic1 interrupt control register intc 783 tq2ccic2 interrupt control register intc 783 tq2ccic3 interrupt control register intc 783 tq2ccr0 tmq2 capture/compare register 0 timer 383 tq2ccr1 tmq2 capture/compare register 1 timer 384 tq2ccr2 tmq2 capture/compare register 2 timer 385 tq2ccr3 tmq2 capture/compare register 3 timer 386 tq2cnt tmq2 counter read buffer register timer 387 tq2ctl0 tmq2 control register 0 timer 388 tq2ctl1 tmq2 control register 1 timer 390 tq2ioc0 tmq2 i/o control register 0 timer 392 tq2ioc1 tmq2 i/o control register 1 timer 393 tq2ioc2 tmq2 i/o control register 2 timer 395 tq2opt0 tmq2 option register timer 396 tq2ovic interrupt control register intc 783 ua0ctl0 uarta0 control register 0 uart 500 ua0ctl1 uarta0 control register 1 uart 502 ua0ctl2 uarta0 control register 2 uart 503 ua0opt0 uarta0 option control register 0 uart 504 ua0ric interrupt control register intc 783 ua0rx uarta0 receive data register uart 507 ua0str uarta0 status register uart 505 ua0tic interrupt control register intc 783 ua0tx uarta0 transmit data register uart 507 ua1ctl0 uarta1 control register 0 uart 500 ua1ctl1 uarta1 control register 1 uart 502 ua1ctl2 uarta1 control register 2 uart 503 ua1opt0 uarta1 option control register 0 uart 504 ua1ric interrupt control register intc 783 ua1rx uarta1 receive data register uart 507 ua1str uarta1 status register uart 505 ua1tic interrupt control register intc 783 ua1tx uarta1 receive data register uart 507 ua2ctl0 uarta2 control register 0 uart 500 ua2ctl1 uarta2 control register 1 uart 502 ua2ctl2 uarta2 control register 2 uart 503 ua2opt0 uarta2 option control register 0 uart 504 ua2ric interrupt control register intc 783 ua2rx uarta2 receive data register uart 507 ua2str uarta2 status register uart 505 ua2tic interrupt control register intc 783 ua2tx uarta2 transmit data register uart 507 ua3ctl0 uarta3 control register 0 uart 500 ua3ctl1 uarta3 control register 1 uart 502 appendix a user?s manual u17830ee1v0um00 928 (15/15) symbol function register name unit page ua3ctl2 uarta3 control register 2 uart 503 ua3opt0 uarta3 option control register 0 uart 504 ua3ric interrupt control register intc 783 ua3rx uarta3 receive data register uart 507 ua3str uarta3 status register uart 505 ua3tic interrupt control register intc 783 ua3tx uarta3 transmit data register uart 507 vswc system wait control register cpu 181 wdte watchdog timer enable register wdt 460 wdtm2 watchdog timer mode register 2 wdt 458 wtic interrupt control register intc 783 wtiic interrupt control register intc 783 wtm watch timer operation mode register wt 450 user?s manual u17830ee1v0um00 929 appendix b instruction set list b.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the re mainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list appendix b instruction set list user?s manual u17830ee1v0um00 930 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix b instruction set list user?s manual u17830ee1v0um00 931 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z 0 0 1 0 z = 1 zero nz 1 0 1 0 z = 0 not zero nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) s/n 0 1 0 0 s = 1 negative ns/p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix b instruction set list user?s manual u17830ee1v0um00 932 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r appendix b instruction set list user?s manual u17830ee1v0um00 933 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 appendix b instruction set list user?s manual u17830ee1v0um00 934 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 appendix b instruction set list user?s manual u17830ee1v0um00 935 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix b instruction set list user?s manual u17830ee1v0um00 936 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix b instruction set list user?s manual u17830ee1v0um00 937 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (accord ing to the number of wait states. also, if there are no wait states, n is the total num ber of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix b instruction set list user?s manual u17830ee1v0um00 938 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. appendix b instruction set list user?s manual u17830ee1v0um00 939 b.3 description of operating precautions if a conflict occurs between the decod e operation of the instruction (<2> in the examples mentioned below) immediately before the sld instruction (<3> in the examples) following a sp ecial instruction (<1> in the examples) and an interrupt request before execution of the special instruction is complete, the execution result of the special instruction may not be stored in a register as expected. this situation may only occur when the same register is us ed as the destination register of the special instruction and the sld instruction, and when the register value is re ferenced by the instruction followed by the sld instruction. conditions under which the conflict occurs: the situation may occur when all the follo wing conditions (1) to (3) are satisfied. (1) either condition (i) or (ii) is satisfied condition (i): the same register is used as the des tination register of a special instru ction (see below) and the subsequent sld instruction and as the source register (reg1) of an instruction shown below followed by the sld instruction (see example 1). mov reg 1,reg2 not reg 1,reg2 satsubr reg 1,reg2 satsub reg 1,reg2 satadd reg 1,reg2 or reg 1,reg2 xor reg 1,reg2 and reg 1,reg2 tst reg 1,reg2 subr reg 1,reg2 sub reg 1,reg2 add reg 1,reg2 cmp reg 1,reg2 mulh reg 1,reg2 condition (ii): the same register is used as the des tination register of a special instru ction (see below) and the subsequent sld instruction and as the source register (reg2) of an instruction shown below followed by the sld instruction (see examples 2 and 3). not reg1, reg2 satsubr reg1 ,reg2 satsub reg1 ,reg2 satadd reg1, reg2 satadd imm5, reg2 or reg1, reg2 xor reg1, reg2 and reg1, reg2 tst reg1 ,reg2 subr reg1, reg2 sub reg1, reg2 add reg1, reg2 add imm5, reg2 cmp reg1 ,reg2 cmp imm5, reg2 shr imm5 ,reg2 sar imm5, reg2 shl imm5, reg2 special instruction: ?ld instruction: ld.b, ld.h , ld.w, ld.bu, ld.hu sld instruction: sld.b, sld. h, sld.w, sld.bu, sld.hu multiply instruction: mul, mulh, mulhi, mulu (2) when the execution result of the s pecial instruction (see above) has not been stored in the destination register before execution of the instruction (instruction of condition (i) or (ii)) immediately before the sld instruction starts in the cpu pipeline. (3) when the decode operation of the in struction (instruction of condition (i ) or (ii)) immediately before the sld instruction and interrupt request servicing conflict. appendix b instruction set list user?s manual u17830ee1v0um00 940 examples of instruction sequence s that may cause the conflict: example 1: <1> ld.w [r11], r10 : <2> mov r10 , r28 <3> sld.w 0x28, r10 this situation occurs wh en the decode operation of mov (<2>) is done immediately before sld (<3>) and an interrupt request servicing conflict happens before the execut ion of the special instruction ld (<1>) is completed. example 2: (1) ld.w [r11], r10 : <2> cmp imm5, r10 <3> sld.w 0x28, r10 <4> bz label this situation occurs when the decode operation of comp (<2>) is done immediately before sld (<3>) and an interrupt request servicing conflict happens before the execut ion of the special instruction ld (<1>) is completed. as a result, the compare result of comp becomes illegal, which may cause an illegal op eration of the branch instruction bz (<4>). example 3: <1> ld.w [r11], r10 : <2> add imm5, r10 <3> sld.w 0x28, r10 <4> setf r16 this situation occurs when the decode operation of add (<2>) is done immediately before sld (<3>) and an interrupt request servicing conflict happens before the execut ion of the special instruction ld (<1>) is completed. as a result, the results of add and the flag become illegal, which may cause illegal operation of the setf (<4>). workaround (1) do not use the sld instruction (e. g. by avoiding code optimization that makes use of sld ). (2) if a code sequence as described above is used (a sld instruction following an instruction that can be executed in parallel), insert a nop instruction before the sld instruction. (3) if a code sequence as described above is used (a sld instruction following an instruction that can be executed in parallel), exchange the order of the prev ious two instructions as long as th e program algorithm is not disturbed: example: 1. (before implementing workaround) ld.w [r11], r10 appendix b instruction set list user?s manual u17830ee1v0um00 941 ... add r11, r12 mov r10, r28 sld.w 0x28, r10 2. (after implementing workaround) ld.w [r11], r10 ... mov r10, r28 add r11, r12 sld.w 0x28, r10 (4) when assembler code is used: avoid the critical code sequences as described above. please regard this item as a usage rest riction on the cpu function. a compiler that can automatically suppress the generation of the instructi on sequence that may cause the bug will be provided. please consult an nec electronics sales represent ative or distributor for further details. support for system developed: [support for system already developed] when the system has already been developed a judgment is nec essary whether or not the restriction applies to the system. please consult an nec electronics sales represent ative or distributor for further details. |
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